19-3217; Rev 1; 10/08 KIT ATION EVALU LE B A IL A AV 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems The MAXQ7665A–MAXQ7665D smart systems-on-a-chip (SoC) are data-acquisition systems based on a microcontroller (µC). As members of the MAXQ® family of 16bit, reduced instruction set computing (RISC) µCs, the MAXQ7665A–MAXQ7665D are ideal for low-cost, lowpower, embedded applications such as automotive, industrial controls, and building automation. The flexible, modular architecture design used in these µCs allows development of targeted products for specific applications with minimal effort. The MAXQ7665A–MAXQ7665D incorporate a high-performance 16-bit RISC core, a 12-bit 500ksps SAR ADC with a programmable gain amplifier (PGA), and a full CAN 2.0B controller supporting transfer rates up to 1Mbps. These devices include a 12-bit DAC with a buffered voltage output and on-chip oscillator circuitry to operate from an external high frequency (8MHz) crystal. There is also a built-in internal RC oscillator as an alternative to using an external crystal. The MAXQ7665A–MAXQ7665D contain an internal temperature sensor to measure die temperature and a remote temperature-sensor driver. The analog functions and digital I/O are powered from a +5V supply, while the internal digital core is powered from +3.3V, which can be supplied by an on-chip linear regulator. These devices also include a dual power-supply supervisor with reset and a JTAG interface for in-system programming and debugging. The 16-bit RISC µC includes up to 128KB (64K x 16) of flash memory and 512 bytes (256 x 16) of RAM. The MAXQ7665A–MAXQ7665D are available in a 7mm x 7mm 48-pin TQFN package and are specified to operate from -40°C to +125°C. Three Independent Data Pointers with Automatic Increment/Decrement ♦ Program and Data Memory Up to 128KB (64K x 16) Internal Flash 512 Bytes (256 x 16) Internal RAM ♦ Smart Analog Peripherals Low-Power, Eight Differential-Channel, 12-Bit, 500ksps ADC Programmable-Gain Amplifier, Software-Selectable Gain: 1V/V, 2V/V, 4V/V, 8V/V, 16V/V, 32V/V 12-Bit DAC with Buffered Voltage Output External References for ADC and DAC Internal (Die) and External Diode Temperature Sensing ♦ Timer/Digital I/O Peripherals Full CAN 2.0B Controller 15 Message Centers (256-Byte Dual Port Memory) Programmable Bit Rates from 10kbps to 1Mbps Standard 11-Bit or Extended 29-Bit Identification Modes Two Data Masks and Associated IDs for DeviceNET™, SDS and Other Higher Layer CAN Protocols External Transmit Disable for Autobaud SIESTA Low-Power Mode Wake-Up on CANRXD Edge Transition UART (LIN) with User-Programmable Baud Rate 16 x 16 Hardware Multiplier with 48-Bit Accumulator, Single Clock Cycle Operation Three 16-Bit (or Six 8-Bit) Programmable Timer/Counter/PWM Eight General-Purpose, Digital I/O Pins, with External Interrupt Capability All Interrupts Can Be Used as a Wake-Up ♦ Crystal/Clock Module Internal Oscillator for Use with External Crystal On-Chip RC Oscillator Eliminates External Crystal External Clock-Source Operation Programmable Watchdog Timer ♦ Power-Management Module Power-On Reset (POR) Power-Supply Supervisor/Brownout Detection for Digital I/O and Digital Core Supplies On-Chip +3.3V, 50mA Linear Regulator Applications Automotive Steering Sensors CAN- and LIN-Based Automotive Sensors Industrial Control ♦ JTAG Interface Extensive Debug and Emulation Support In-System Test Capability Flash-Memory-Program Download Software Bootstrap Loader for Flash Programming Features ♦ High-Performance, Low-Power, 16-Bit RISC Core 8MHz Operation, Approaching 1MIPS per MHz Low Power (< 3mA/MIPS, DVDD = +3.3V) 16-Bit Instruction Word, 16-Bit Data Bus 33 Instructions (Most Require Only One Clock Cycle) 16-Level Hardware Stack ♦ Ultra-Low-Power Consumption Low-Power, Stop Mode (CPU Shutdown) Ordering Information and Pin Configuration appear at end of data sheet. MAXQ is a registered trademark of Maxim Integrated Products, Inc. DeviceNet is a trademark of Open DeviceNet Vendor Association, Inc. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata. ________________________________________________________________ Maxim Integrated Products 1 For pricing delivery, and ordering information please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAXQ7665A–MAXQ7665D General Description MAXQ7665A–MAXQ7665D 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems ABSOLUTE MAXIMUM RATINGS DVDD to DGND, AGND, or GNDIO ..........................-0.3V to +4V DGND to GNDIO or AGND....................................-0.3V to +0.3V DVDDIO to DGND, AGND, or GNDIO .......................-0.3V to +6V AVDD to DGND, AGND, or GNDIO...........................-0.3V to +6V Digital Inputs/Outputs to DGND, AGND, or GNDIO ..............................................................-0.3V to (DVDDIO + 0.3V) Analog Inputs/Outputs to DGND, AGND, or GNDIO .................................................................-0.3V to (AVDD + 0.3V) RESET, XIN, XOUT to DGND, AGND, or GNDIO .................................................................-0.3V to (DVDD + 0.3V) Continuous Current into Any Pin.......................................±50mA Continuous Power Dissipation (TA = +70°C) 48-Pin TQFN (derate 40mW/°C above +70°C) ..........3200mW Operating Temperature Range .........................-40°C to +125°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX 2.7 3.3 3.6 UNITS POWER REQUIRMENTS DVDD Supply Voltage Range AVDD Supply Current Safe mode (RC/2 = 3.8MHz) 3.0 3.3 3.6 AVDD 4.75 5.0 5.25 DVDDIO 4.75 5.0 5.25 Shutdown (Note 2) 0.1 10 µA All analog functions enabled 6.7 8 mA ADC enabled, fADC = 1ksps, fSYSCLK = 8MHz 4.2 IAVDD Normal mode ADC enabled, fADC = 500ksps, fSYSCLK = 8MHz Analog Module Subfunction Incremental Supply Current DVDD Supply Current IDVDD 305 Internal temperature sensor enabled 502 Additional current when one or more of the ADC, DAC, and/or temperature sensor is enabled (only counted once) 128 PGA enabled 4.5 DVDDIO Supply Current DVDD supervisor and brownout monitor 2 IDVDDIO 3 High-speed mode (Note 3) Flash erase or write mode DVDD Module Subfunction Incremental Supply Current 1890 DAC enabled (zero scale) CPU in stop mode, all peripherals disabled V µA mA 20 28 35 50 µA mA 2 HF crystal oscillator 150 Internal RC oscillator 200 All digital I/Os static at GND or DVDDIO (Note 4) ________________________________________________________________________________________ µA 10 1000 µA 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS MEMORY SECTION Flash Memory Size Flash Erase/Write Endurance Flash Erase Timing Flash Program Timing Flash Data Retention Time MAXQ7665A 128 MAXQ7665B 64 MAXQ7665C 48 MAXQ7665D 32 KB DVDD = +3V, at +25°C 1 DVDD = +3V, at +85°C 100 MCycles kCycles DVDD = +3V, at +125°C 100 kCycles One sector 0.7 15 s Single word 11 360 µs Entire flash 1.5 4.5 s TA = +125°C, single write 20 First 100,000 cycles at +25°C, then retention tested at TA = +125°C 10 Years RAM Memory Size 512 Bytes Utility ROM Size 4096 Words ANALOG SENSE PATH Resolution NADC Integral Nonlinearity INLADC Differential Nonlinearity DNLADC Offset Error No missing codes 12 ±0.5 Gain = 8, unipolar mode, VIN = +400mV, 142ksps ±2.0 Gain = 16, bipolar mode, VIN = ±156mV, 142ksps ±2.0 Gain = 32, bipolar mode, VIN = ±50mV, 142ksps ±2.0 ±4.0 Gain = 1, bipolar, VIN = ±2500mV, 500ksps ±1.0 Gain = 16, bipolar, VIN = ±156mV, 142ksps ±1.0 LSB ±5 mV All other gain settings ±0.6 Input referred ±2.5 Zero-Code Error Bipolar, differential measurement of error for ideal ADC output of 0x000 Gain Error Exclude offset and reference error Gain-Error Temperature Coefficient Total Harmonic Distortion ±4.0 LSB Offset-Error Temperature Coefficient Signal-to-Noise Plus Distortion Bits Gain = 1, bipolar mode, VIN = ±2500mV, 500ksps ±8 µV/°C ±2.5 mV -1.0 +1.0 % ±8.5 ppm/°C SINAD PGA gain = 1V/V -71 dB THD PGA gain = 1V/V -85 dB _______________________________________________________________________________________ 3 MAXQ7665A–MAXQ7665D ELECTRICAL CHARACTERISTICS (continued) MAXQ7665A–MAXQ7665D 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL Spurious-Free Dynamic Range Conversion Clock Frequency fADCCLK Sample Rate fSAMPLE Conversion Time SFDR tCONV Channel/Gain Select Plus Conversion Time Track-and-Hold Acquisition Time Turn-On Time Aperture Delay Aperture Jitter tACQ CONDITIONS PGA gain = 1V/V fSYSCLK = 8MHz PGA gain = 1V/V, RSOURCE ≤ 1kΩ 0.5 8.0 500 142 tACQ + 1.625 PGA gain = 1V/V, RSOURCE ≤ 1kΩ Any PGA gain setting, RSOURCE ≤ 5kΩ PGA gain = 1V/V, RSOURCE ≤ 1kΩ 2 7 375 Any PGA gain setting > 1V/V, RSOURCE ≤ 5kΩ 5 tRECOV 5 30 50 Bipolar mode, AIN+ to AIN- 0 AVDD PGA gain = 2 0 1.6 PGA gain = 4 0 0.8 PGA gain = 8 0 0.4 PGA gain = 16 0 0.2 PGA gain = 32 0 PGA gain = 1 +VREFADC /2 PGA gain = 2 -VREFADC /4 +VREFADC /4 PGA gain = 4 -VREFADC /8 +VREFADC /8 PGA gain = 8 -VREFADC /16 +VREFADC /16 PGA gain = 16 -VREFADC /32 +VREFADC /32 PGA gain = 32 -VREFADC /64 +VREFADC /64 AGND VIN x gain = 100mVP-P dB MHz ksps µs µs ns µs 0.1 -VREFADC /2 AIN15–AIN0 UNITS µs ns psP-P PGA gain = 1 Absolute Input-Voltage Range 4 MAX -91 tACQ plus 13 ADCCLK cycles at 8MHz Input-Voltage Range Small-Signal Bandwidth (-3dB) TYP Any PGA gain setting > 1V/V, RSOURCE ≤ 5kΩ Unipolar mode Input Leakage Current MIN AVDD ±20 PGA gain = 1 180 PGA gain = 2 140 PGA gain = 4 120 PGA gain = 8 100 PGA gain = 16 82 PGA gain = 32 80 ________________________________________________________________________________________ V V nA MHz 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL Large-Signal Bandwidth (-3dB) CONDITIONS VIN x gain = 3.2VP-P Single-ended, any input of AIN0 to AIN15 Input Capacitance Crosstalk Between Channels VCT MIN TYP PGA gain = 1 180 PGA gain = 2 140 PGA gain = 4 120 PGA gain = 8 100 PGA gain = 16 82 PGA gain = 32 80 PGA gain = 1 13.6 PGA gain = 2 2 PGA gain = 4 4 PGA gain = 8 8 PGA gain = 16 16 PGA gain = 32 32 AIN15–AIN0, VIN = 1VP-P, 10kHz, RSOURCE = 5kΩ MAX UNITS kHz pF -80 dB Input Common-Mode Rejection Ratio CMRR AIN15–AIN0 (bipolar, differential), VCM = 100mV to 4.5V -70 -90 dB Power-Supply Rejection Ratio PSRR AVDD = +4.75V to +5.25V 67 75 dB DAC SECTION (DACOUT, RL = 5kΩ and CL = 100pF) Resolution NDAC Differential Nonlinearity DNLDAC Integral Nonlinearity INLDAC Offset Error Guaranteed monotonic 12 Code 147h to E68h ±1 LSB Code 147h to E68h ±0.5 ±4 LSB Reference to code 040h ±2.5 ±30 mV Offset-Error Temperature Coefficient ±5 Gain Error Excludes reference error, tested at E68h Gain-Error Temperature Coefficient Excludes offset and reference drift; calculated from FSR DAC Output Range No load DC Output Impedance Bits ±0.4 ZOUT Termination resistance to AGND ±3 µV/°C ±20 ±2 0 LSB ppm of FSR/°C VREFDAC V DAC enabled 0.5 Ω Power-down mode 105 kΩ V/µs Output Slew Rate 400h to C00h code swing, rising or falling 0.6 Output Settling Time 147h to E68h code swing, settling to ±0.5 LSB (Note 5) 8 Output Short-Circuit Current Short to AGND Short to AVDD -27 46 15 µs mA _______________________________________________________________________________________ 5 MAXQ7665A–MAXQ7665D ELECTRICAL CHARACTERISTICS (continued) MAXQ7665A–MAXQ7665D 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DAC Glitch Impulse From 7FFh to 800h 12 nV·s DAC Power-On Time Excluding reference, settling to ±0.5 LSB 14 µs Power-Supply Rejection AVDD step from +4.75V to +5.25V 62 µV/V Output Noise CL = 200pF 200 µVRMS EXTERNAL REFERENCE INPUTS REFADC Input-Voltage Range 1.0 5.0 AVDD REFDAC Input-Voltage Range 0 5.0 AVDD REFDAC Input Impedance REFADC Leakage Current ADC disabled V V 200 kΩ 1 µA TEMPERATURE SENSOR (Remote NPN Transistor 2N3904) Internal diode Temperature Error External diode, differential configuration (Note 6) TA = +25°C ±1 TA = -30°C to +85°C ±2 TA = -40°C to +125°C ±5 TA = +25°C, TRJ = +25°C ±2 TA = -30°C to +85°C, TRJ = +25°C ±3 TA = -40°C to +125°C, TRJ = +25°C ±3 TA = -30°C to +85°C, TRJ = -30°C to +85°C ±3 TA = -40°C to +125°C, TRJ = -40°C to +125°C ±5 Internal (Die) or External Temperature Measurement Error vs. VREFADC Variation External Diode Source Current °C 0.095 High level 74.7 Low level 4 External Diode Drive Current Ratio Conversion Time fADCCLK = fSYSCLK = 8MHz, no interrupts, internal utility ROM tempConv Temperature Resolution 12-bit ADC °C/mV µA 18.7:1 µA/µA 70 µs 0.125 °C/LSB +3.3V LINEAR REGULATOR (CDVDD = 4.7µF) DVDDIO Input-Voltage Range 4.25 5.0 3.4 5.25 V DVDD Output Voltage REGEN = GNDIO 3.0 DVDD Input-Voltage Range REGEN = DVDDIO 3.0 No-Load Quiescent Current CPU in sleep mode; all digital peripherals disabled 15 µA Output Short-Circuit Current Short to DGND 110 mA 6 ________________________________________________________________________________________ 3.6 V 3.6 V 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS V SUPPLY VOLTAGE SUPERVISORS AND BROWNOUT DETECTION DVDD Voltage-Supervisor Reset Rising Threshold Power-on default, DVDD voltage rising (Note 7) 2.70 2.99 VDBR = 00b (default) 2.70 2.99 DVDD Voltage-Supervisor Brownout Reset Falling Threshold DVDD voltage falling, firmware selectable, measured with CPU active at 8MHz (Note 8) VDBR = 01b 2.77 3.06 VDBR = 10b 2.84 3.13 VDBR = 11b 2.91 3.20 DVDD voltage falling, firmware selectable, measured with CPU active at 8MHz (Note 9) VDBI = 00b (default) 2.77 3.06 VDBI = 01b 2.84 3.13 VDBI = 10b 2.91 3.20 VDBI = 11b 2.99 3.27 DVDDIO voltage falling, firmware selectable, measured with CPU active at 8MHz (Note 10) VIOBI = 00b (default) 4.25 4.74 VIOBI = 01b 4.30 4.79 VIOBI = 10b 4.35 4.84 VIOBI = 11b 4.40 Software-Selectable DVDD Voltage-Supervisor Brownout Interrupt Falling Threshold DVDDIO Voltage-Supervisor Brownout Interrupt Threshold VVDBR VVDBI VVIOBI Voltage-Supervisor Hysteresis DVDD Brownout-Interrupt to Brownout Reset Falling Threshold DVDD, DVDDIO Voltage difference between VVDBI and VVDBR, time allowing software clean-up before reset asserted, VDBI = 11b and VDBR = 10b DVDD V V 4.89 1 % 155 mV 1.0 3.6 DVDDIO 0 5.25 DVDD Ramp-Up Rate DVDD must rise faster than this rate between +2.7V and +3.0V 35 RESET Hold Time After DVDD rises above the VVDBR voltage trip threshold Voltage Monitor Range V V mV/ms 16 ms CAN INTERFACE CAN Baud Rate CANCLK = 8MHz CANCLK Mean Frequency Error 50ppm external crystal error, 8MHz crystal 60 1 Mbps ppm CANCLK Total Frequency Error 50ppm external crystal error, 8MHz crystal, clock divided and measured over 500µs interval, mean plus peak cycle jitter < 0.5 % HIGH-FREQUENCY CRYSTAL OSCILLATOR Clock Frequency Using external crystal 7.6 8.12 External clock source 7.6 8.12 Crystal Oscillator Startup Time 8MHz crystal External Clock Input Duty Cycle Ratio high-to-low or low-to-high 10 45 MHz ms 55 % _______________________________________________________________________________________ 7 MAXQ7665A–MAXQ7665D ELECTRICAL CHARACTERISTICS (continued) MAXQ7665A–MAXQ7665D 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL Crystal Oscillator Stability XIN Input Load Capacitance XOUT Output Load Capacitance CONDITIONS MIN Excluding crystal TYP HFIC = 00b (default) 7 HFIC = 01b 18 HFIC = 10b 27 HFIC = 11b 34 HFOC = 00b (default) 6 HFOC = 01b 17 HFOC = 10b 27 HFOC = 11b 34 XIN Input Low Voltage Driven with external clock source XIN Input High Voltage Driven with external clock source MAX 3 UNITS ppm/V pF pF 0.3 x DVDD 0.7 x DVDD V V INTERNAL RC OSCILLATOR Oscillator Frequency 7.0 7.6 8.0 MHz Oscillator Startup Time 10 µs Oscillator Jitter 2.7 ns UART (LIN) INTERFACE (UTX, URX) UART Baud Rate 0 Minimum LIN Mode Operation Maximum LIN Mode Operation UART Baud Rates Error 2 Mbps 1 kbps 20 kbps Crystal clock source -0.5 +0.5 Using internal RC oscillator before autobaud -14.0 +14.0 Using internal RC oscillator after autobaud -0.5 +0.5 % RESET (RESET) RESET Internal Pullup Resistance RESET Output Voltage Pullup to DVDD High, RESET deasserted, no load 305 kΩ 0.9 x DVDD V Low, RESET asserted, no load 0.4 0.7 x DVDD RESET Input High Voltage V RESET Input Low Voltage 0.3 x DVDD V 0.3 x DVDDIO V DIGITAL INPUTS (P0._, CANRXD, URX, REGEN) Input Low Voltage 0.7 x DVDDIO Input High Voltage Input Hysteresis Input Leakage Current 8 V 500 VIN = GNDIO or DVDDIO, pullup disabled -1 ±0.01 ________________________________________________________________________________________ mV +1 µA 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fSYSCLK = 8MHz, VREFDAC = VREFADC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Pullup Resistance Pullup to DVDDIO 400 kΩ Input Capacitance VIN = GNDIO or DVDDIO 15 pF DIGITAL OUTPUTS (P0._, CANTXD, UTX) Output Low Voltage ISINK = 1.6mA Output High Voltage ISOURCE = 1.6mA Output Leakage Current I/O pins, three-state Output Capacitance I/O pins, three-state 15 Short to DVDDIO = +5.25V 29 Short to GNDIO 28 Output Short-Circuit Current 0.4 DVDDIO - 0.5 -1 V V ±0.01 +1 µA pF mA Note 1: All devices are 100% production tested at TA = +25°C. Note 2: All analog functions disabled and all digital inputs connected to supply or ground. Note 3: High-speed mode: CPU and three timers running at 8MHz from an external crystal oscillator, CAN enabled and communicating at 500kbps, all other peripherals disabled, all digital I/Os static at DVDDIO or GNDIO. Note 4: CAN transmitting at 500kbps, one timer output at 500kHz, all active I/Os are loaded with 20pF capacitor, all remaining digital I/Os are at DVDDIO or GNDIO. Note 5: Guaranteed by design and characterization. Note 6: Based on diode ideality factor of 1.008. Note 7: DVDD must rise above VVDBR for RESET to become deasserted. Caution: Operation is not guaranteed for DVDD below +2.7V (utility ROM) or +3.0V (flash). Note 8: RESET is asserted if DVDD falls below VVDBR. Caution: Operation is not guaranteed for DVDD below +2.7V (utility ROM) or +3.0V (flash). Note 9: An interrupt is generated if DVDD falls below VVDBI. Caution: Operation is not guaranteed for DVDD below +2.7V (utility ROM) or +3.0V (flash). Note 10: An interrupt is generated if DVDDIO falls below VVIOBI. Caution: Operation is not guaranteed if DVDDIO or AVDD is below 4.75V, except for the DVDDIO brownout monitor and +3.3V linear regulator, that still operate down to 0V and +4.25V, respectively. _______________________________________________________________________________________ 9 MAXQ7665A–MAXQ7665D ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fADCCLK = 8MHz, fADC = 500kHz, TA = +25°C, unless otherwise noted.) GPO._ OUTPUT LOW VOLTAGE vs. SINK CURRENT VOL (V) 3 2 0.3 TA = +85°C 1.5 1.0 TA = +85°C TA = +125°C 1 0.4 0.2 2.0 4 VOH (V) TA = +125°C MAXQ7665A toc03 TA = +25°C 2.5 0.5 INL (LSB) TA = -40°C 5 3.0 MAXQ7665A toc01 6 DAC INL vs. INPUT CODE (REFDAC = +5V) MAXQ7665A toc02 GPO._ OUTPUT HIGH VOLTAGE vs. SOURCE CURRENT 0.1 0 -0.1 -0.2 TA = +25°C TA = -40°C 0.5 -0.3 -0.4 0 0 2 4 6 8 10 2 4 6 8 10 0 1000 2000 3000 IOH (mA) IOL (mA) DIGITAL INPUT CODE DAC DNL vs. INPUT CODE (REFDAC = +5V) DAC OFFSET VOLTAGE vs. TEMPERATURE DAC GAIN ERROR vs. TEMPERATURE 0.2 0.1 0 -0.1 -0.2 2.0 1.5 1.0 4.0 3.5 3.0 2.5 0.5 -0.3 4000 MAXQ7665A toc06 0.3 2.5 GAIN ERROR (LSB) 0.4 MAXQ7665A toc05 MAXQ7665A toc04 0.5 DNL (LSB) -0.5 0 OFFSET VOLTAGE (mV) 0 -0.4 -40 -25 -10 5 20 35 50 65 80 95 110 125 DIGITAL INPUT CODE TEMPERATURE (°C) TEMPERATURE (°C) DAC OFFSET ERROR vs. AVDD SUPPLY VOLTAGE DAC GAIN ERROR vs. AVDD SUPPLY VOLTAGE DACOUT OUTPUT HIGH VOLTAGE vs. SOURCE CURRENT 3000 4000 4.0 MAXQ7665A toc07 1.8 DAC GAIN ERROR (LSB) 1.7 DACREF = +4.75V 1.6 1.5 DACREF = AVDD 3.5 VOH (V) 2000 3.0 DACREF = AVDD 2.5 DACREF = +4.75V 1.4 2.0 4.75 4.85 4.95 5.05 5.15 AVDD SUPPLY VOLTAGE (V) 5.25 4.75 4.85 4.95 5.05 5.15 AVDD SUPPLY VOLTAGE (V) 5.25 5.5 5.4 5.3 5.2 5.1 5.0 4.9 4.8 4.7 4.6 4.5 4.4 4.3 4.2 4.1 4.0 MAXQ7665A toc09 -40 -25 -10 5 20 35 50 65 80 95 110 125 1000 MAXQ7665A toc08 0 10 2.0 0 -0.5 DAC OFFSET ERROR (mV) MAXQ7665A–MAXQ7665D 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems REFDAC = +5V OUTPUT CODE = FFFh 0 1 2 IOH (mA) _______________________________________________________________________________________ 3 4 5 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems 0.4 1.5 1.0 DACOUT (1V/div) 0.3 BIPOLAR MODE VIN = -156mV TO +156mV REFDAC = +5V ADC INL (LSB) REFDAC = +5V OUTPUT CODE = 000h 0.2 MAXQ7665A toc12 MAXQ7665A toc10 MAXQ7665A toc11 0.5 VOL (V) ADC INL vs. OUTPUT CODE (REFADC = +5V, 142ksps, PGA GAIN = 16) DACOUT LARGE-SIGNAL STEP RESPONSE (CODE 000h TO FFFh) DACOUT OUTPUT LOW VOLTAGE vs. SINK CURRENT 0.5 0 -0.5 0.1 -1.0 -1.5 -2048 0 0 1 2 3 4 5 4.0µs/div -1024 ADC DNL vs. OUTPUT CODE (REFADC = +5V, 142ksps, PGA GAIN = 16) 0.4 0.2 0 -0.2 -0.4 1.0 1.4 0.8 0.6 1.2 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 0.4 -0.6 -0.8 0.2 -0.8 -1.0 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 DIGITAL OUTPUT CODE TEMPERATURE (°C) TEMPERATURE (°C) ADC BIPOLAR ZERO-CODE ERROR vs. TEMPERATURE ADC/PGA OFFSET ERROR (GAIN = 16) vs. AVDD SUPPLY VOLTAGE ADC/PGA GAIN ERROR (GAIN = 16) vs. AVDD SUPPLY VOLTAGE 2048 5.0 MAXQ7665A toc15b 0.6 1024 4.5 4.0 OFFSET ERROR (mV) 0.5 0.4 0.3 0.2 3.5 3.0 2.5 REFADC = AVDD 2.0 1.5 1.0 0.1 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 0 4.75 -0.1 -0.2 -0.3 REFADC = +4.75V REFADC = AVDD -0.4 -0.5 -0.6 -0.7 -0.8 REFADC = +4.75V -0.9 0.5 0 0 MAXQ7665A toc17 0 GAIN ERROR (% FSR) -1024 MAXQ7665A toc16 -1.0 -2048 2048 MAXQ7665A toc15 1.6 OFFSET ERROR (mV) ADC DNL (LSB) 0.6 ZERO-CODE ERROR (mV) 1.8 GAIN ERROR (% FSR) BIPOLAR MODE VIN = -156mV TO +156mV MAXQ7665A toc14 0.8 1024 ADC/PGA GAIN ERROR (GAIN = 16) vs. TEMPERATURE ADC/PGA OFFSET ERROR (GAIN = 16) vs. TEMPERATURE MAXQ7665A toc13 1.0 0 DIGITAL OUTPUT CODE IOL (mA) 4.85 4.95 5.05 AVDD (V) 5.15 5.25 -1.0 4.75 4.85 4.95 5.05 5.15 5.25 AVDD (V) ______________________________________________________________________________________ 11 MAXQ7665A–MAXQ7665D Typical Operating Characteristics (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fADCCLK = 8MHz, fADC = 500kHz, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fADCCLK = 8MHz, fADC = 500kHz, TA = +25°C, unless otherwise noted.) 1.25 1.00 REFADC = +4.75V 0.75 REFADC = AVDD 0.50 4 0.25 2 1 0 -1 -2 -3 4 4.85 4.95 5.05 5.15 5.25 2 1 0 -1 -2 -3 -5 -5 4.75 3 -4 -4 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 AVDD (V) TEMPERATURE (°C) TEMPERATURE (°C) REMOTE TEMPERATURE-SENSOR ERROR DUE TO CAPACITIVE LOADING DVDD, RESET POWER-UP CHARACTERISTICS DVDD, RESET POWER-DOWN CHARACTERISTICS MAXQ7665A toc21 MAXQ7665A toc20 16 TEMPERATURE-SENSOR ERROR (°C) 3 5 ERROR (ACTUAL - REPORTED °C) 1.50 MAXQ7665A toc18 ZERO-CODE ERROR (mV) 1.75 5 ERROR (ACTUAL - REPORTED °C) MAXQ7665A toc17b 2.00 EXTERNAL DIODE TEMPERATURE-SENSOR ERROR vs. TEMPERATURE INTERNAL DIODE TEMPERATURE-SENSOR ERROR vs. TEMPERATURE MAXQ7665A toc19 ADC/PGA ZERO-CODE ERROR (GAIN = 16) vs. AVDD SUPPLY VOLTAGE 14 12 MAXQ7665A toc22 DVBR[1:0] = [0:0] DVBR[1:0] = [0:0] DVDD (1V/div) DVDD (1V/div) RESET (2V/div) RESET (2V/div) 10 8 6 4 2 0 0 5 10 15 20 10ms/div 10ms/div MAXIMUM DVDD TRANSIENT DURATION vs. BOI THRESHOLD OVERDRIVE MAXIMUM DVDDIO TRANSIENT DURATION vs. BOI THRESHOLD OVERDRIVE 25 700 600 500 400 300 200 100 0 800 700 600 500 400 300 200 100 0 1 10 100 DVDD BOR THRESHOLD OVERDRIVE (mV) 12 BROWNOUT INTERRUPT (BOI) ASSERTED ABOVE THIS LINE 900 1000 1000 BOI ASSERTED ABOVE THIS LINE 900 800 MAXQ7665A toc25 800 1000 MAXIMUM TRANSIENT DURATION (µs) BROWNOUT RESET (BOR) ASSERTED ABOVE THIS LINE 900 MAXIMUM TRANSIENT DURATION (µs) 1000 MAXQ7665A toc23 MAXIMUM DVDD TRANSIENT DURATION vs. BOR THRESHOLD OVERDRIVE MAXQ7665A toc24 CAPACITIVE LOAD BETWEEN AIN0 AND AIN1 (nF) MAXIMUM TRANSIENT DURATION (µs) MAXQ7665A–MAXQ7665D 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems 700 600 500 400 300 200 100 0 1 10 100 DVDD BOI THRESHOLD OVERDRIVE (mV) 1000 1 10 100 DVDDIO BOI THRESHOLD OVERDRIVE (mV) _______________________________________________________________________________________ 1000 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems 2.88 2.94 2.93 VDVDD-BOI (V) 2.85 2.84 2.91 2.90 2.89 VIOBI[1:0] = [0:0] 4.44 4.43 4.42 4.41 4.40 4.39 2.83 2.88 4.38 2.82 2.87 4.37 2.81 2.86 4.36 2.80 2.85 4.35 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) DVDD LINEAR REGULATOR OUTPUT VOLTAGE vs. DVDDIO SUPPLY VOLTAGE DVDD LINEAR REGULATOR OUTPUT VOLTAGE vs. TEMPERATURE DVDD LINEAR REGULATOR OUTPUT VOLTAGE vs. LOAD CURRENT 3.50 3.5 2.5 3.45 DVDD (V) 3.0 ILOAD = 50mA 2.0 ILOAD = +25mA REGEN = GND 3.50 3.40 REGEN = GND 3.45 DVDD (V) REGEN = GND MAXQ7665A toc30 4.0 MAXQ7665A toc31 -40 -25 -10 5 20 35 50 65 80 95 110 125 MAXQ7665A toc29 VDVDD-BOR (V) 2.86 4.45 VDVDDIO-BOI (V) 2.92 2.87 DVDD (V) DVBI[1:0] = [0:0] REGEN = DVDDIO MAXQ7665A toc28 DVBR[1:0] = [0:0] REGEN = DVDDIO MAXQ7665A toc27 2.89 2.95 MAXQ7665A toc26 2.90 DVDDIO BOI THRESHOLD VOLTAGE vs. TEMPERATURE DVDD BOI THRESHOLD VOLTAGE vs. TEMPERATURE DVDD BOR THRESHOLD VOLTAGE vs. TEMPERATURE TA = -40°C TA = +25°C 3.40 1.5 ILOAD = 25mA 1.0 3.35 TA = +85°C 3.35 TA = +125°C 0.5 ILOAD = 0mA 3.30 0 3.2 3.7 4.2 4.7 3.30 -40 -25 -10 5 20 35 50 65 80 95 110 125 5.2 0 10 20 30 50 40 DVDDIO (V) TEMPERATURE (°C) LOAD CURRENT (mA) DVDD LINEAR REGULATOR OUTPUT VOLTAGE LINE TRANSIENT (DVDDIO = +4.75V TO +5.25V STEP) DVDD LINEAR REGULATOR OUTPUT VOLTAGE LOAD TRANSIENT (IDVDD = 0 TO 50mA STEP) DVDD LINEAR REGULATOR DROPOUT VOLTAGE vs. LOAD CURRENT MAXQ7665A toc32 MAXQ7665A toc33 REGEN = GND ILOAD = 25mA DVDDIO (200mV/div) TA = +125°C 500 VDROPOUT (mV) DVDD (5mV/div) AC-COUPLED REGEN = GND 600 DVDD (20mV/div) AC-COUPLED +4.75V OFFSET 700 REGEN = GND TA = +85°C 400 300 TA = -40°C TA = +25°C 200 ILOAD (50mA/div) 40µs/div VDROPOUT = DVDDIO - DVDD, WHEN DVDDIO IS LOWERED ENOUGH BELOW +5V TO MAKE DVDD DROP BY 100mV. 100 0 40µs/div MAXQ7665A toc34 2.7 0 10 20 30 40 50 LOAD CURRENT (mA) ______________________________________________________________________________________ 13 MAXQ7665A–MAXQ7665D Typical Operating Characteristics (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fADCCLK = 8MHz, fADC = 500kHz, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fADCCLK = 8MHz, fADC = 500kHz, TA = +25°C, unless otherwise noted.) 7.55 7.50 REGEN = DVDDIO 7.65 7.60 35 7.55 SEE NOTES AFTER ELECTRICAL CHARACTERISTICS TABLE. FLASH ERASE/PROGRAM 30 IDVDD (mA) 7.60 40 MAXQ7665A toc36 DVDD = +3.3V REGEN = DVDDIO FREQUENCY (MHz) FREQUENCY (MHz) 7.65 7.70 MAXQ7665A toc35 7.70 DVDD ACTIVE SUPPLY CURRENT vs. DVDD SUPPLY VOLTAGE RC OSCILLATOR OUTPUT FREQUENCY vs. DVDD SUPPLY VOLTAGE MAXQ7665A toc37 RC OSCILLATOR OUTPUT FREQUENCY vs. TEMPERATURE NOTE 3 25 20 15 7.50 10 7.45 7.45 7.40 2.7 3.6 3.0 3.6 3.3 DVDD (V) DVDD (V) DVDD ACTIVE SUPPLY CURRENT vs. TEMPERATURE DVDD STOP-MODE SUPPLY CURRENT vs. DVDD SUPPLY VOLTAGE DVDD STOP-MODE SUPPLY CURRENT vs. TEMPERATURE REGEN = DVDDIO CPU IN STOP MODE ALL PERIPHERALS DISABLED 1.5 15 REGEN = DVDDIO CPU IN STOP MODE ALL PERIPHERALS DISABLED NOTE 3 10 20 IDVDD (µA) FLASH ERASE/PROGRAM 2.0 MAXQ7665A toc40 SEE NOTES AFTER ELECTRICAL CHARACTERISTICS TABLE. IDVDD (µA) IDVDD (mA) 3.3 TEMPERATURE (°C) 30 25 3.0 MAXQ7665A toc39 35 0 2.7 MAXQ7665A toc38 40 5 7.40 -40 -25 -10 5 20 35 50 65 80 95 110 125 1.0 15 BOR ENABLED 10 0.5 5 BOR ENABLED BOR DISABLED BOR DISABLED 5 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) DVDD SUPPLY VOLTAGE (V) TEMPERATURE (°C) AVDD ENABLED SUPPLY CURRENT vs. AVDD SUPPLY VOLTAGE AVDD ENABLED SUPPLY CURRENT vs. TEMPERATURE AVDD DISABLED SUPPLY CURRENT vs. AVDD SUPPLY VOLTAGE 7.00 6.75 5 ALL ANALOG FUNCTIONS DISABLED 4 IAVDD (mA) 6.25 IAVDD (nA) 6.50 6.50 6.25 6.00 6.00 5.75 5.75 5.50 4.750 ALL ANALOG FUNCTIONS ENABLED MAXQ7665A toc42 ALL ANALOG FUNCTIONS ENABLED MAXQ7665A toc43 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 6.75 5.000 5.125 5.250 3 2 1 5.50 4.875 AVDD (V) 14 0 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 MAXQ7665A toc41 7.00 IAVDD (mA) MAXQ7665A–MAXQ7665D 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 0 4.750 4.875 5.000 5.125 AVDD SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 5.250 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems 300 200 0 100 4.875 5.000 -40 -25 -10 5 20 35 50 65 80 95 110 125 5.250 5.125 TEMPERATURE (°C) DVDDIO SUPPLY VOLTAGE (V) TEMPERATURE (°C) DVDDIO STATIC SUPPLY CURRENT vs. DVDDIO SUPPLY VOLTAGE DVDDIO STATIC SUPPLY CURRENT vs. TEMPERATURE AVDD SUPPLY CURRENT vs. ADC SAMPLING RATE IDVDDIO (nA) 200 150 2.5 2.0 150 100 50 50 5.125 10 PGA ENABLED AUTOMATIC SHUTDOWN OFF 3 2 PGA ENABLED AUTOMATIC SHUTDOWN ON 100 1000 1 MAXQ7665A toc51 5 IAVDD (mA) 1 SAMPLING ERROR vs. INPUT SOURCE IMPEDANCE PGA GAIN = 32 0 SAMPLING ERROR (LSB) MAXQ7665A toc50 6 AUTOMATIC SHUTDOWN MAX SAMPLING RATE fADC (ksps) AVDD SUPPLY CURRENT vs. ADC SAMPLING RATE (PGA ENABLED) 1 PGA DISABLED AUTOMATIC SHUTDOWN ON TEMPERATURE (°C) DVDDIO (V) 4 1.0 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 5.250 1.5 0.5 0 5.000 PGA DISABLED AUTOMATIC SHUTDOWN OFF 200 100 4.875 MAXQ7665A toc49 250 ALL DIGITAL I/O STATIC REGEN = DVDDIO IAVDD (mA) ALL DIGITAL I/O STATIC REGEN = DVDDIO MAXQ7665A toc48 300 MAXQ7665A toc47 300 0 4.750 150 125 100 4.750 -40 -25 -10 5 20 35 50 65 80 95 110 125 IDVDDIO (nA) 150 CAN COMMUNICATING AT 500kbps ONE TIMER OUTPUT AT 500kHz ALL ACTIVE I/O LOADED WITH 20pF CAPACITORS 175 125 100 250 CAN COMMUNICATING AT 500kbps ONE TIMER OUTPUT AT 500kHz ALL ACTIVE I/O LOADED WITH 20pF CAPACITORS IDVDDIO (µA) IDVDDIO (µA) 175 200 MAXQ7665A toc45 ALL ANALOG FUNCTIONS DISABLED 400 IAVDD (nA) 200 MAXQ7665A toc44 500 DVDDIO DYNAMIC SUPPLY CURRENT vs. TEMPERATURE DVDDIO DYNAMIC SUPPLY CURRENT vs. DVDDIO SUPPLY VOLTAGE MAXQ7665A toc46 AVDD DISABLED SUPPLY CURRENT vs. TEMPERATURE -1 -2 -3 -4 -5 0 1 10 100 fADC (ksps) 1000 1 10 100 SOURCE IMPEDANCE (kΩ) ______________________________________________________________________________________ 15 MAXQ7665A–MAXQ7665D Typical Operating Characteristics (continued) (AVDD = DVDDIO = +5.0V, DVDD = +3.3V, fADCCLK = 8MHz, fADC = 500kHz, TA = +25°C, unless otherwise noted.) 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems MAXQ7665A–MAXQ7665D Pin Description 16 PIN NAME 1 AIN11 Analog Input Channel 11. AIN11 is multiplexed to the PGA as a differential input with AIN10. FUNCTION 2 AIN10 Analog Input Channel 10. AIN10 is multiplexed to the PGA as a differential input with AIN11. 3 AIN9 Analog Input Channel 9. AIN9 is multiplexed to the PGA as a differential input with AIN8. 4 AIN8 5, 8 AGND 6 REFADC ADC External Reference Input. Connect an external reference voltage between 1V and AVDD to REFADC. 7 REFDAC DAC External Reference Input. Connect an external reference voltage between 0V and AVDD to REFDAC. Analog Input Channel 8. AIN8 is multiplexed to the PGA as a differential input with AIN9. Analog Ground 9 AIN7 Analog Input Channel 7. AIN7 is multiplexed to the PGA as a differential input with AIN6. 10 AIN6 Analog Input Channel 6. AIN6 is multiplexed to the PGA as a differential input with AIN7. 11 AIN5 Analog Input Channel 5. AIN5 is multiplexed to the PGA as a differential input with AIN4. 12 AIN4 Analog Input Channel 4. AIN4 is multiplexed to the PGA as a differential input with AIN5. 13 AIN3 Analog Input Channel 3. AIN3 is multiplexed to the PGA as a differential input with AIN2. AIN3–AIN0 have remote temperature sensor capability. 14 AIN2 Analog Input Channel 2. AIN2 is multiplexed to the PGA as a differential input with AIN3. AIN3–AIN0 have remote temperature sensor capability. 15 AIN1 Analog Input Channel 1. AIN1 is multiplexed to the PGA as a differential input with AIN0. AIN3–AIN0 have remote temperature sensor capability. 16 AIN0 Analog Input Channel 0. AIN0 is multiplexed to the PGA as a differential input with AIN1. AIN3–AIN0 have remote temperature sensor capability. 17 DACOUT DAC Buffer Output. DACOUT is the DAC voltage buffer output. 18, 19, 31 DGND 20 CANRXD CAN Bus Receiver Input. Control area network receiver input. Digital Ground for the Digital Core and Flash 21 CANTXD CAN Bus Transmitter Output. Control area network transmitter output. 22 UTX UART Transmitter Output 23 URX UART Receiver Input 24 P0.6/T0 Port 0 Bit 6/Timer 0. P0.6 is a general-purpose digital I/O with interrupt/wake-up input capability. T0 is a primary timer/PWM input or output. 25 P0.7/T1 Port 0 Bit 7/Timer 1. P0.7 is a general-purpose digital I/O with interrupt/wake-up input capability. T1 is a primary timer/PWM input or output. 26, 39 DVDDIO Digital I/O Supply Voltage. Supplies all digital I/O except for XIN, XOUT, and RESET. Bypass DVDDIO to GNDIO with a 0.1µF capacitor placed as close as possible to the device. DVDDIO is also connected to the input of the linear regulator. 27 GNDIO 28, 29 I.C. Internal Connection. Connect I.C. to GNDIO or DVDDIO. Digital I/O Ground 30 N.C. No Connection. No internal connection. Leave N.C. unconnected. 32 P0.0/TDO Port 0 Data 0/JTAG Serial Test Data Output. P0.0 is a general-purpose digital I/O with interrupt/wake-up capability. TDO is the JTAG serial test, data output. _______________________________________________________________________________________ 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems PIN NAME 33 P0.1/TMS Port 0 Data 1/JTAG Test Mode Select. P0.1 is a general-purpose digital I/O with interrupt/wakeup capability. TMS is the JTAG test mode, select input. 34 P0.2/TDI Port 0 Data 2/JTAG Serial Test Data Input. P0.2 is a general-purpose digital I/O with interrupt/wake-up capability. TDI is the JTAG serial test, data input. 35 P0.3/TCK Port 0 Data 3/JTAG Serial Test Clock Input. P0.3 is a general-purpose digital I/O with interrupt/wake-up capability. TCK is the JTAG serial test, clock input. 36 P0.4/ADCCNV 37 Port 0 Data 5/DAC Data Register Load/Update Input. P0.5 is a general-purpose digital I/O with P0.5/DACLOAD interrupt/wake-up capability. DACLOAD is firmware configurable for a rising or falling edge to update the DACOUT register. 38 REGEN FUNCTION Port 0 Data 4/ADC Start Conversion Control. P0.4 is a general-purpose digital I/O. ADCCNV is firmware configurable for a rising or falling edge start/convert to trigger ADC conversions. Active-Low Linear Regulator Enable Input. Connect REGEN to GNDIO to enable the linear regulator. Connect to DVDDIO to disable the linear regulator. 40 DVDD Digital Supply Voltage. DVDD supplies the internal digital core and flash memory. DVDD is internally connected to the output of the internal 3.3V linear regulator. Disable the internal regulator to connect DVDD to an external supply. When using the on-chip linear regulator, bypass DVDD to DGND with a 4.7µF ±20% capacitor with a maximum ESR of 0.5Ω. In addition, bypass DVDD with a 0.1µF capacitor. Place both bypass capacitors as close as possible to the device. 41 RESET Reset Input and Output. Active-low open-drain input/output with internal 360kΩ pullup to DVDD. Drive low to reset the µC. RESET is low during power-up reset and during DVDD brownout conditions. 42 XOUT High-Frequency Crystal Output. Connect an external crystal to XIN and XOUT for normal operation. Leave XOUT unconnected if XIN is driven with an external clock source. XOUT is not driven when using the internal RC oscillator. 43 XIN High-Frequency Crystal Input. Connect an external crystal or resonator to XIN and XOUT for normal operation, or drive XIN with an external clock source. XIN is not driven when using the internal RC oscillator. 44 AVDD Analog Supply Voltage Input. Connect AVDD to a +5V supply. Bypass AVDD to AGND with a 0.1µF capacitor placed as close as possible to the device. 45 AIN15 Analog Input Channel 15. AIN15 is multiplexed to the PGA as a differential input with AIN14. 46 AIN14 Analog Input Channel 14. AIN14 is multiplexed to the PGA as a differential input with AIN15. 47 AIN13 Analog Input Channel 13. AIN13 is multiplexed to the PGA as a differential input with AIN12. 48 AIN12 — EP Analog Input Channel 12. AIN12 is multiplexed to the PGA as a differential input with AIN13. Exposed Pad. EP is internally connected to AGND. Connect EP to AGND externally. ______________________________________________________________________________________ 17 MAXQ7665A–MAXQ7665D Pin Description (continued) MAXQ7665A–MAXQ7665D 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems Block Diagram IINT REMOTE TEMP-SENSE DIODE CURRENT DRIVE ADCMX3 1:2 CURRENT DEMUX MAXQ7665A–MAXQ7665D AIN0 AIN1 AIN2 AIN3 TEMPERATURE SENSORS REFADC INTERNAL TSE REFDAC ADCREF ADCMX0 DACREF ADCCLK PGAE AIN5 AIN6 AIN7 12-BIT ADC PGA DACOUT R DACE ADCRY GAIN = x1, x2, x4, x8, x16, x32 17:1 MUX AIN8 AIN9 + - 12-BIT DAC ADCE DACE ADCOV AIN4 R AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 AIN1 AIN3 AIN5 AIN7 AIN9 AIN11 AIN13 AIN15 AVDD 9:1 MUX ADCMX[3.0] WATCHDOG TIMER HFRCCLK WDI T0CLK T0I DVDD T1CLK T1I EWT DVDD POWER-ONRESET/ BROWNOUT MONITOR DGND XIN XOUT HF XTAL OSC. DGND P0.7/T1 P0.5/DACLOAD I/O BUFFERS PO0 PI0 PORT 0 I/O REGISTERS EIF0 JTAG INTERFACE PORT 0 I/O REGISTERS GNDIO HFFINT XHFRY XHFE M U X HFCLK CAN CLOCK PRESCALER CANCLK ADC CLOCK PRESCALER ADCCLK HF CLOCK PRESCALER INT HF R-C OSC HFRCCLK DGND TIMER1/PWM1 (2 x 8 BITS OR 1 x 16 BITS) PD0 512 BYTES DATA RAM I/O BUFFERS DVDD P0.6/T0 P0.4/ADCCNV 16-BIT MAXQ20 RISC CPU 32/48/64/128KB FLASH DVDDIO P0.3/TCK P0.2/TDI P0.1/TMS P0.0/TDO TIMER0/PWM0 (2 x 8 BITS OR 1 x 16 BITS) 8KB UTILITY ROM DVBI VDPE VDBE DVDDIO GNDIO DVDDIO BROWNOUT MONITOR TIMER2/PWM2 (2 x 8 BITS OR 1 x 16 BITS) T2CLK T2I RESET DVDD VIBE VIOBI WTR REGEN CANSTI CANERI DVBI DVDD +3.3V LINEAR REGULATOR T1I T2I SOFTWAREINTERRUPT CONTROLLER EIFO UARTI DVDDIO AGND T0I HFFINT 2:1 M U X SYSCLK 16 x 16 HW MULTIPLY UARTI TIMER CLOCK PRESCALERS T0CLK T1CLK T2CLK UTX UART INTERFACE URX DVDDIO GNDIO SYSCLK CAN 2.0B INTERFACE CANSTI RCE GNDIO DGND I/O BUFFERS CANERI CANCLK GNDIO 18 _______________________________________________________________________________________ CANTXD CANRXD 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems The MAXQ offers a low < 3mA/MIPS ratio. The on-chip 16-bit x 16-bit hardware multiplier with accumulator, performs single-cycle computations. Refer to the MAXQ7665/MAXQ7666 User’s Guide for more detailed information on configuring and programming the MAXQ7665A–MAXQ7665D. The µC arithmetic core of the MAXQ7665A– MAXQ7665D is a 16-bit RISC machine with digital and analog peripheral functions. They incorporate a 16-bit RISC ALU with a Harvard memory architecture that can address up to 128KB (64K x 16) of flash and 512 bytes (256 x 16) of RAM memory. They also contain a hardware multiplier, up to eight digital I/Os, a controller area network (CAN 2.0B) bus, a JTAG interface, three timers, an on-chip RC oscillator, a precision 12-bit 500ksps ADC with an 8-channel differential MUX and PGA, a 12-bit precision DAC, an internal temperature sensor and temperature-sensor driver, a linear regulator, watchdog timer, and a dual power-supply supervisor. Analog Input Peripheral The integrated 12-bit ADC employs an ultra-low-power, high-precision, SAR-based conversion method and can operate up to 500ksps (142ksps with PGA ≥ 2). The onchip 8-channel differential MUX and PGA allow the ADC to measure eight fully differential analog inputs with software-selectable input ranges through the PGA. See Figure 1. TIMERS 0, 1, 2 ADCBY P0.4/ADCCNV ADCS AIN0 2 CONVERSION CONTROL AIN2 1 0 ADCDUL AIN4 8:1 MUX AIN6 PGG AIN8 2 1 ADCBIP 0 ADCOV AIN10 ADCRDY AIN12 AIN14 PGA 1 TO 32 AIN1 12-BIT ADC 500ksps AIN3 AIN5 AIN7 DATA BUS PGAE 8:1 MUX AIN9 12 ADCDIF AIN11 AIN13 AIN15 ADCASD ADCE 4 ADCMX 3 2 1 ADC CLOCK DIV 0 SYSCLK SOURCE REFADC 2 MAXQ7665A–MAXQ7665D 1 0 ADCCD Figure 1. Simplified Analog Input Diagram (Eight Fully Differential Inputs) ______________________________________________________________________________________ 19 MAXQ7665A–MAXQ7665D Detailed Description MAXQ7665A–MAXQ7665D 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems The MAXQ7665A–MAXQ7665D ADC uses a fully differential SAR conversion technique and an on-chip T/H block to convert temperature and voltage signals into a 12-bit digital result. Differential configurations are supported using an analog input channel MUX that supports eight differential channels. The differential analog inputs are selected from the following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5, AIN6/AIN7, AIN8/AIN9, AIN10/AIN11, AIN12/AIN13, and AIN14/AIN15. Remote temperature-sensor configuration in differential mode uses analog input channel pairs AIN2/AIN3 and AIN0/AIN1. In single-ended remote temperature-sensor configuration, only channels AIN2 and AIN0 are used. Internal temperature-sensor configuration measures local die temperature and does not use any analog input channel. There are four ways to control the ADC conversion timing: 1) Software register bit control 2) Continuous conversion 3) Internal timers (T0, T1, or T2) 4) External input through pin ADCCNV Refer to the MAXQ7665/MAXQ7666 User’s Guide for more detailed information on the ADC and MUX. 12-Bit Digital-to-Analog Converter (DAC) The MAXQ7665A–MAXQ7665D contain a 12-bit voltageoutput DAC with its own output buffer. The data path to the DAC is double buffered and the output register can be updated using the DACLOAD digital input. Refer to the MAXQ7665/MAXQ7666 User’s Guide for detailed programming information. The DAC also supports a square-wave-output toggle mode with precise amplitude control for applications that require pulse-amplitude modulation (PAM) and/or pulse-width modulation (PWM) signals. See Figure 2 for a simplified block diagram of the DAC. 20 REFDAC DACE DAC INPUT REGISTER DAC OUTPUT REGISTER DACOUT 12-BIT DAC R P0.5/DACLOAD DAC LOAD CONTROL R MAXQ7665A–MAXQ7665D Figure 2. Simplified DAC Diagram The DAC output buffer is in a voltage follower configuration (gain of 1V/V from REFDAC). The buffer can be disabled when not in use. When the buffer is disabled, the output is connected internally to AGND through a 100kΩ resistor. The reference input REFDAC accepts an input voltage of less than or equal to AVDD for a maximum output swing of 0V to AVDD. Temperature Sensor The µC measures temperature by using the on-chip ADC and a ROM-based tempConv subroutine. Use the tempConv subroutine to initiate a measurement (refer to the MAXQ7665/MAXQ7666 User’s Guide for detailed information). The device supports conversions of two external and one on-chip (internal) temperature sensors. The external temperature sensor is typically a diode-connected small-signal transistor, connected between two analog inputs (differential) or one analog input and AGND (single-ended). Figures 3 and 4 illustrate these two configurations. _______________________________________________________________________________________ 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems CURRENT SOURCES MAXQ7665A–MAXQ7665D AIN15 ADCMX3 AIN3 AIN2 AIN1 12-BIT ADC 500ksps MUX AIN0 2N3904 2N3904 AGND ADCMX 3 2 1 4 0 MAXQ7665A–MAXQ7665D Figure 3. Temperature-Sensor Application Circuit—Single-Ended Configuration AIN15 CURRENT SOURCES AIN4 2N3904 AIN2 AIN3 2N3904 ADCMX3 12-BIT ADC 500ksps MUX AIN0 AIN1 4 AGND ADCMX 3 2 1 0 MAXQ7665A–MAXQ7665D Figure 4. Temperature-Sensor Application Circuit—Differential Configuration Power-On Reset and Brownout Power supplies DV DD and DV DDIO each include a brownout monitor that alerts the µC through interrupt when their corresponding supply voltages drop below a selectable threshold. This condition is generally referred to as brownout interrupt (BOI), and these thresholds are set by the VDBI and VIOBI bits for DVDD and DV DDIO, respectively. Continuous monitoring ensures that a valid supply is present at all times while the µC is executing code. For example, the brownout monitors check that DVDDIO does not drop during a CAN bus transfer, or DVDD is not disrupted while the µC core is executing. The DVDDIO brownout monitor also covers the analog peripherals if AVDD and DVDDIO are directly connected. The DVDD supply (internal core logic) also includes a voltage supervisor that controls the µC reset during power-up (DVDD rising) and brownout (DVDD falling) conditions (see Figure 5 for a POR and brownout timing example). ______________________________________________________________________________________ 21 MAXQ7665A–MAXQ7665D 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems NOMINAL DVDD (+3.3V) BROWNOUT INTERRUPT TRIGGER POINT DVDD BROWNOUT INTERRUPT THRESHOLD RANGE VDBI[1:0] = 01 +3.13V +3.06V +2.84V BROWNOUT RESET +2.77V TRIGGER POINT BROWNOUT INTERRUPT BROWNOUT RESET INTERNAL RESET POWER-UP* DELAY (8.6ms) DVDD BROWNOUT RESET THRESHOLD RANGE VDBR[1:0] = 01 BOR STATE RESET OUTPUT DGND DVLVL FLAG (ASR[14]) VDBE BIT SET BY µC DVBI FLAG (ASR[4]) FLAG ARBITRARILY CLEARED BY µC *POWER-UP DELAY IS ONLY PRESENT WHEN DVDD DROPS BELOW ~1.2V Figure 5. DVDD Brownout Interrupt Detection During power-up, RESET is held low once DVDD rises above +1.0V. All internal register bits are set to their default, POR state after DVDD exceeds a threshold of approximately +1.2V. This includes the VDBR bits which reset to 00b, resulting in a default, DV DD brownout reset (BOR) threshold in the +2.7V to +2.99V range following POR. Once DV DD rises above this DVDD brownout threshold, the 7.6MHz RC oscillator starts driving the power-up counter, and 8.6ms (typ) later, the RESET pin is released and allowed to go high if nothing external is holding it low. An important system-design consideration at power-up is the DV DD ramp-up rate should be at least 35mV/ms between +2.7V and +3.0V. This ensures RESET is not released before DVDD reaches a minimum flash operating level of +3.0V. After DVDD has reached a valid level and RESET is released, the µC jumps to the reset vector 22 (8000h in the utility ROM), and the desired BOI and BOR threshold values can be set by the user through the VIOBI, VDBI, and VDBR bits. If a valid DVDD drops below its BOI threshold (set by the VDBI bits), an interrupt is generated. This offers the possibility of limited software cleanup before the DV DD BOR occurs. The amount of cleanup time depends on the VDBI and VDBR brownout threshold bit settings, the size of the DVDD bypass capacitors, and the application-dependent, µC power management and software cleanup tasks. Note that if the internal, +3.3V linear regulator is being used to provide DVDD, additional software cleanup time is possible by using the DVDDIO brownout monitor as an early warning that the regulator’s DVDDIO (+5V) input voltage is falling, and its DVDD (+3.3V) will subsequently drop (unless DVDDIO recovers). _______________________________________________________________________________________ 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems Once DVDD has entered BOR, there are a few possible scenarios: • If DV DD remains below the BOR threshold, the RESET pin remains low, and the µC remains in the reset state. • If DV DD stops falling before reaching the POR threshold, then begins rising above the BOR threshold, the RESET pin is released, and the µC jumps to the reset vector (8000h in the utility ROM). This is similar to the DVDD power-up case described in the previous scenario, except there is no power-up counter delay and some of the register bits are set to BOR values rather than POR values. See Tables 3 and 5 for the reset behavior of specific bits. In particular, the retained VDBR setting, if higher than the default value of 00b, allows a potentially more robust brownout recovery closer to or above the minimum flash operating level of +3.0V. • If DVDD falls below the 1.2V POR threshold, all register bits are reset, and any DVDD recovery from that point is identical to the power-up case described above. See Tables 3 and 5 for reset behavior of specific bits. Refer to the MAXQ7665/MAXQ7666 User’s Guide for detailed programming information, and a more thorough description of POR and brownout behavior. Internal 3.3V Linear Regulator The MAXQ7665A–MAXQ7665D core logic supply, DVDD, can be supplied by a 3.3V external supply or the on-chip 3.3V, 50mA linear regulator. To use the on-chip linear regulator, ensure the DVDDIO supply can support a load of approximately 50mA and connect digital input REGEN to GNDIO. If using an external supply, connect the regulated 3.3V supply to DVDD and connect digital input REGEN to DVDDIO. If the linear regulator is not used, bring up DVDDIO before DVDD. System Clock Generator The MAXQ7665A–MAXQ7665D oscillator module is the master clock generator that supplies the system clock for the µC core and all of the peripheral modules. The high-frequency (HF) oscillator is designed to operate with an 8MHz crystal. Alternatively, the on-chip RC oscillator can be used in applications that do not require precise timing. Due to its RISC design, the MAXQ7665A–MAXQ7665D execute most instructions in a single SYSCLK period. The oscillator module contains all of the primary clock-generation circuitry. Figure 6 shows a block diagram of the system clock module. The MAXQ7665A–MAXQ7665D contain many features for generating a master clock signal timing source: • Internal, fast-starting, 7.6MHz RC oscillator eliminates external crystal • Internal high-frequency oscillator that can drive an external 8MHz crystal • External high-frequency clock input (8MHz) • Selectable internal capacitors for HF crystal oscillator • Power-up timer • Power-saving management modes • Fail-safe modes Watchdog Timer The watchdog timer serves as a time-base generator, an event timer, or a system supervisor. The primary function of the watchdog timer is to supervise software execution, watching for stalled or stuck software. The watchdog timer performs a controlled system restart when the µP fails to write to the watchdog timer register before a selectable timeout interval expires. In some designs, the watchdog timer is also used to implement a real-time operating system (RTOS) in the µC. When used to implement an RTOS, a watchdog timer typically has four objectives: 1) To detect if a system is operating normally 2) To detect an infinite loop in any of the tasks 3) To detect an arbitration deadlock involving two or more tasks 4) To detect if some lower priority tasks are not getting to run because of higher priority tasks HFE XIN HF XTAL OSC XOUT RCE XT EXTHF MUX RC OSC CLOCK DIVIDE SYSCLK CD0 HFRCCLK Figure 6. High-Frequency and RC Oscillator Block Diagram ______________________________________________________________________________________ 23 MAXQ7665A–MAXQ7665D As DVDD continues to fall below the DVDD BOR threshold set by the VDBR bits, the RESET pin is pulled low, µC and peripheral activity stops, and most, but not all of the register bits are set to their default state. This includes the VDBR bits, which retain their value if DVDD falls below the BOR threshold, but not below the POR threshold. MAXQ7665A–MAXQ7665D 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems As illustrated in Figure 7, the high-frequency internal RC oscillator (HFRCCLK) drives the watchdog timer through a series of dividers. The divider output is programmable and determines the timeout interval. When enabled, the interrupt flag WDIF is set when a timeout is reached. A system reset then occurs after a time delay (based on the divider ratio). The watchdog timer functions as the source of both the watchdog interrupt and the watchdog reset. The interrupt timeout has a default divide ratio of 212 of the HFR- HFRCCLK (7.6MHz) DIV 212 DIV 23 DIV 23 DIV 23 CCLK, with the watchdog reset set to timeout 29 clock cycles later. With the nominal RC oscillator value of 7.6MHz, an interrupt timeout occurs every 539µs, followed by a watchdog reset 67.4µs later. The watchdog timer is reset to the default divide ratio following any reset. Using the WD0 and WD1 bits in the WDCN register, other divide ratios can be selected for longer watchdog interrupt periods. If the WD[1:0] bits are changed before the watchdog interrupt timeout occurs (i.e. before the watchdog reset counter begins), the watchdog timer count is reset. All watchdog timer reset timeouts follow the programmed interrupt timeout 512 source clock cycles later. For more information on the MAXQ7665A–MAXQ7665D watchdog timer, refer to the MAXQ7665/MAXQ7666 User’s Guide. Timer and PWM WD1 WD0 RWT The MAXQ7665A–MAXQ7665D include three 16-bit timer channels. Each timer is a type 2 timer implemented in the MAXQ family (see Figure 8). Two of the timers are accessible through I/Os, and one is accessible only through software. Type 2 timers are auto-reload 16-bit timers/counters offering the following functions: • 8-bit/16-bit timer/counter 212 215 218 221 TIME TIMEOUT WDIF INTERRUPT EWDI • Up/down auto-reload • Counter function of external pulse WTRF RESET RESET • Capture • Compare EWT Figure 7. Watchdog Functional Diagram T2MD TR2L T2L COMPARE MATCH T2CL T2CH T2H:T2L COMPARE MATCH OR T2H COMPARE MATCH T2L T2L OVERFLOW T2H T2CLK T2H:T2L OVERFLOW OR T2H OVERFLOW T2RL T2RH C/T2 EDGE DETECTION AND GATING TIMER EVENT CCF[1:0] G2EN TR2 SS2 T2POL[0] Figure 8. Type 2 Timer Functional Diagram 24 _______________________________________________________________________________________ 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems 16-Bit x 16-Bit Hardware Multiplier A hardware multiplier supports high-speed multiplications. The multiplier is capable of completing a 16-bit x 16-bit multiply in a single cycle and contains a 48-bit accumulator that requires one more cycle. The multiplier is not part of the MAXQ core function but a peripheral that performs seven different multiply operations without interfering with the normal core functions: • Unsigned 16-bit multiplication (one cycle) • Unsigned 16-bit multiplication and accumulation (two cycles) • Unsigned 16-bit multiplication and subtraction (two cycles) • Signed 16-bit multiplication (one cycle) • Signed 16-bit multiplication and negate (one cycle) • Signed 16-bit multiplication and accumulation (two cycles) • Signed 16-bit multiplication and subtraction (two cycles) Figure 9 illustrates the simplified hardware multiplier circuitry. Two 16-bit parallel-load registers and a 48-bit 15 0 MA 15 0 MB SUS MMAC MCNT MSUB MULTIPLIER OPCS SQU CLD MCW OVERFLOW 15 0 15 0 15 0 15 0 15 0 MC1R MC0R MC2 MC1 MC0 Figure 9. 16-Bit Hardware Multiplier Functional Diagram accumulator are used: operand A (MA), operand B (MB), and accumulator (MC). The accumulator is formed by three 16-bit parallel registers (MC2, MC1, and MC0). The overflow bit is organized in the MCNT status/control register. The multiplicand and the multiplier are initially loaded into the MA and MB registers, respectively. Loading the required operands triggers the respective multiply, multiply-accumulate/subtract or multiply-negate operation. The multiply operation completes in a single cycle with the results in the read-only MC1R/MC0R register. The multiply-accumulate/subtract operation requires one extra wait cycle for the results to be stable in the MC2, MC1, and MC0 registers. The main arithmetic unit is the 16-bit x 16-bit multiplier, which processes operands feeding from the MA and MB registers and generates a 32-bit final product. The product value goes through the 32-bit adder to perform final accumulation with zeroes for multiply operation or with the contents from the MC1 and MC0 registers for multiply-accumulation. The final sum is accessible directly from the accumulator. To support negate operations including signed multiplynegate and signed and unsigned multiply-subtract, the operand in MA is negated by 1’s complement operation before being supplied to the arithmetic unit and the partial product terms are sign corrected. Refer to the MAXQ7665/MAXQ7666 User’s Guide for more detailed information. CAN Interface Bus The MAXQ7665A–MAXQ7665D incorporate a CAN controller that is fully compliant with the CAN 2.0B specification. The µC interface to the CAN controller is broken into two groups of registers. To simplify the software associated with the operation of the CAN controllers, most of the global CAN status and controls as well as the individual message center control/status registers are located in the peripheral register map. The remaining registers associated with the data identification, identification masks, format, and data are located in a dual port memory to allow the CAN controller and the processor access to the required functions. The CAN controller can directly access the dual port memory. A dedicated interface is incorporated to support dual port memory accessing by the processor through the CAN 0 data pointer (C0DP) and the CAN 0 data buffer (C0DB) special function registers. ______________________________________________________________________________________ 25 MAXQ7665A–MAXQ7665D Note: The MAXQ7665A–MAXQ7665D do not have secondary timer I/O pins (such as T0B and T1B) that are present in some other MAXQ products. MAXQ7665A–MAXQ7665D 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems CAN Functional Description The basic functions covered by the CAN controller include the use of 11-bit standard or 29-bit extended acceptance identifiers, as programmed by the µC for each message center, as shown in Figure 10. The CAN unit provides storage for up to 15 messages, with the standard 8-byte data field, in each message. Each of the first 14 message centers is programmable in either transmit or receive mode. Message center 15 is designed as a receive-only message center with a buffer FIFO arrangement to help prevent the inadver- tent loss of data when the µC is busy and is not allowed time to retrieve the incoming message prior to the acceptance of a second message into message center 15. Message center 15 also utilizes an independent set of mask registers and identification registers, which are only applied once an incoming message has not been accepted by any of the first 14 message centers. A second filter test is also supported for all message centers (1–15) to allow the CAN controller to use two separate 8-bit media masks and media arbitration fields to verify the contents of the first 2 bytes of data of CAN 0 CONTROLLER BLOCK DIAGRAM DUAL PORT MEMORY CAN PROCESSOR BUS ACTIVITY WAKE-UP MESSAGE CENTERS 1–15 MESSAGE CENTER 1 8-BIT Rx ARBITRATION 0–3 CRC CHECK BIT DESTUFF Rx SHIFT BIT TIMING CANRXD Tx SHIFT CANTXD DATA 0–7 FORMAT 8-BIT Tx CRC GENERATE BIT STUFF MESSAGE CENTER 2 ARBITRATION 0–3 CAN PROTOCOL FSM DATA 0–7 FORMAT CAN INTERRUPT SOURCES MESSAGE CENTER 14 ARBITRATION 0–3 DATA 0–7 FORMAT CAN 0 PERIPHERAL REGISTERS CAN 0 TRANSMIT ERROR COUNTER MESSAGE CENTER 15 ARBITRATION 0–3 DATA 0–7 FORMAT CAN 0 CONTROL REGISTER CAN 0 OPERATION CONTROL CAN 0 RECEIVE ERROR COUNTER CAN 0 STATUS REGISTER CONTROL/STATUS/MASK REGISTERS MEDIA ID MASK 0–1 STD GLOBAL MASK 0–1 CAN 0 MESSAGE 1–15 CONTROL REGISTERS MEDIA ARBITRATION 0–1 EXT GLOBAL MASK 0–3 CAN 0 DATA POINTER CAN 0 TRANSMIT MSG ACK BUS TIMING 0–1 MSG15 MASK 0–3 CAN 0 DATA BUFFER CAN 0 RECEIVE MSG ACK CAN 0 INTERRUPT REGISTER MAXQ7665A–MAXQ7665D Figure 10. CAN 0 Controller Block Diagram 26 _______________________________________________________________________________________ 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems MAXQ7665A–MAXQ7665D SBUF0 SYSCLK DIVIDE BY 12 0 URX INPUT LATCH S0 D7 D6 D5 D4 D3 D2 D1 D0 LOAD CLOCK OUTPUT SHIFT REGISTER DIVIDE BY 4 1 DATA BUS LDSBUF RDSBUF SHIFT READ SERIAL LOAD SERIAL BUFFER TI FLAG = SCON0.1 RD RECEIVE DATA BUFFER WR RECEIVE BUFFER DATA CLOCK CLOCK RI FLAG = SCON0.0 D7 D6 D5 D4 D3 D2 D1 D0 INTS BAUD CLOCK SERIAL I/O CONTROL SBUF0 SI RECEIVE SHIFT REGISTER SERIAL INTERRUPT UTX OUTPUT Figure 11a. UART Synchronous Mode (Mode 0) each incoming message, before accepting an incoming message. This feature allows the CAN unit to directly support the use of higher CAN protocols, which make use of the first and/or second byte of data as a part of the acceptance layer for storing incoming messages. Each message center can also be programmed independently to perform testing of the incoming data with or without the use of the global masks. Global controls and status registers in the CAN unit allow the µC to evaluate error messages, validate new data and the location of such data, establish the bus timing for the CAN bus, establish the identification mask bits, and verify the source of individual messages. In addition, each message center is individually equipped with the necessary status and controls to establish directions, interrupt generation, identification mode (standard or extended), data field size, data status, automatic remote frame request and acknowledg- ment, and masked or nonmasked identification acceptance testing. UART Interface Serial interfacing is provided through one (UTX/URX) 8051-style universal synchronous/asynchronous receiver/transmitter (UART) capable of interfacing with a LIN transceiver. Figure 11a shows the UART block diagram in synchronous mode and Figure 11b shows asynchronous mode. The UART allows the device to conveniently communicate with other RS-232 interface-enabled devices, as well as PCs and serial modems when paired with an external RS-232 line driver/receiver. The UART can detect framing errors and indicate the condition through a user-accessible software bit. The time base of the serial port is derived from either a division of the system clock or the dedicated baud clock generator. The UART is capable of supporting LIN protocol implementation in software when using one of the timers for autobaud ______________________________________________________________________________________ 27 MAXQ7665A–MAXQ7665D 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems SBUF0 1 START D7 D6 D5 D4 D3 D2 D1 D0 SYSCLK STOP LOAD CLOCK TRANSMIT SHIFT REGISTER UTX OUTPUT LATCH S0 0 DIVIDE BY 4 0 1 DATA BUS SMOD LDSBUF RDSBUF BAUD CLOCK GENERATOR DIVIDE BY 16 LOAD SERIAL BUFFER BAUD CLOCK SHIFT SERIAL I/O CONTROL SBUF0 READ SERIAL BUFFER RD RECEIVE DATA BUFFER WR LOAD RESET START SI D7 D6 D5 D4 D3 D2 D1 D0 RI FLAG = SCON0.0 START TI FLAG = SCON0.1 CLOCK INTS RB8 = SCON0.2 RECEIVE SHIFT REGISTER SERIAL INTERRUPT DIVIDE BY 16 BIT DETECTION URX INPUT Figure 11b. UART Asynchronous Mode (Mode 1) the TAP and TAP controller, refer to IEEE Standard 1149.1 on the IEEE website at http://standards.ieee.org. The JTAG on the MAXQ7665A–MAXQ7665D is used for in-circuit emulation and debug support, but does not support boundary scan test capability. The TAP controller communicates synchronously with the host system (bus master) through four digital I/O pins: test mode select (TMS), test clock (TCK), test data input (TDI), and test data output (TDO). The internal TAP module consists of several shift registers and a detection. Table 1 summarizes the operating characteristics as well as the maximum baud rate of each mode. JTAG Interface Bus The joint test action group (JTAG) IEEE 1149.1 standard defines a unique method for in-circuit testing and programming. The MAXQ7665A–MAXQ7665D conform to this standard, implementing an external test access port (TAP) and internal TAP controller for communication with a JTAG bus master, such as an automatic test equipment (ATE) system. For detailed information on Table 1. Operating Characteristics and Mode Baud Rate MODE 28 TYPE BAUD CLOCK START BITS DATA BITS STOP BITS MAX BAUD RATE AT 8MHz Mode 0 Synchronous 4 or 12 clock N/A 8 N/A 2Mbps Mode 1 Asynchronous Baud generation 1 8 1 250kbps Mode 2 Asynchronous 32 or 64 clock 1 8+1 1 250kbps Mode 3 Asynchronous Baud generation 1 8+1 1 250kbps _______________________________________________________________________________________ 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems ship between the on-chip state machines and the TAP. The on-chip state machines are clocked by the system clock. The four digital I/Os that form the TAP module are described as follows: • TDO—Serial output signal for test instruction and data. Data is driven out only on the falling edge of TCK and is forced in an inactive state when it is idle. This signal is used to serially transfer internal data to the host. Data is transferred LSB first. • TDI—Serial input signal for test instruction and data. Data should be driven in only on the rising edge of TCK. This signal is used to serially transfer data from READ TO DEBUG ENGINE SHADOW REGISTER MAXQ7665A–MAXQ7665D MUX 7 6 5 4 3 2 1 0 S1 S0 DEBUG REGISTER 4 3 2 1 0 SYSTEM PROGRAMMING REGISTER MUX WRITE BYPASS DVDDIO PO.2/TDI 2 1 0 INSTRUCTION REGISTER MUX MUX DVDDIO PO.0/TDO DVDDIO PO.1/TMS UPDATE-DR DVDDIO TAP CONTROLLER UPDATE-DR PO.3/TCK POWER-ON RESET Figure 12. JTAG Interface Block Diagram ______________________________________________________________________________________ 29 MAXQ7665A–MAXQ7665D TAP controller (see Figure 12). The shift registers serve as transmit-and-receive data buffers for a debugger. From a JTAG perspective, shift registers are userdefined optional data registers. The bypass register and the instruction register, for example, are realized as a set of shift-register-based elements connected in parallel between a common serial input (TDI) and a common serial output (TDO). The instruction register, through the TAP controller, selects one of the registers to form an active serial path. The maximum TCK clock frequency must be below 1/8 of the system clock frequency to work properly. The TAP operates asynchronously with on-chip system logic and may be affected by the timing relation- the host to the internal TAP module shift registers. Data is transferred LSB first. • TCK—Serial clock for the test logic. • TMS—Test mode selection. Test signals received at TMS are sampled at the rising edge of TCK and decoded by the TAP controller to control the test operation. General-Purpose Digital I/Os The MAXQ7665A–MAXQ7665D provide eight generalpurpose digital I/Os (GPIOs). All GPIOs have an additional special function (SF), such as a timer input/output, or TAP signal for JTAG communication. For example, the state of pin P0.6/T0 can be programmed to depend on timer channel 0 logic. When programmed as a port, each I/O is configurable for high-impedance or weak pullup to DVDDIO. At powerup, each GPIO is configured as an input with pullups to DVDDIO. Note that at power-up, the JTAG function is enabled and should be turned off before normal operation. In addition, each GPIO can be programmed to cause an interrupt (on falling or rising edges). In stop mode, any interrupt can be used to wake up the device. The data input/output direction in a port is independently controlled by the port direction register (PD). Each I/O within the port can be individually set as an output or input. The port output register (PO) contains the current state of the logic output buffers. When an I/O is configured as an output, writing to the PO register controls the output logic state. Reading the PO register shows the current state of the output buffers, independent of the data direction. The port input register (PI) is a read-only register that always reflects the logic state of the I/Os. When an I/O is configured as an input, writing to the PO register enables/disables the pull-up resistor. Refer to the MAXQ7665/MAXQ7666 User’s Guide for more detailed information. Port Characteristics The MAXQ7665A–MAXQ7665D contain only one port (P0). It is a bidirectional 8-bit I/O port, which contains the following features: • Schmitt trigger input circuitry with software-selectable high-impedance or weak pullup to DVDDIO • Software-selectable push-pull CMOS output drivers capable of sinking and sourcing 1.6mA • Software-selectable open-drain output drivers capable of sinking 1.6mA • Falling or rising edge interrupt capability • All I/Os contain an additional special function, such as a logic input/output for a timer channel. Selecting an I/O for a special function alters the port characteristics of that I/O (refer to the MAXQ7665/MAXQ7666 User’s Guide for more details). Figure 13 illustrates the functional blocks of an I/O. DVDDIO MAXQ7665A–MAXQ7665D I/O PAD MUX PD0._ PD DVDDIO 400kΩ SF DIRECTION SF ENABLE PO0._ MUX MAXQ7665A–MAXQ7665D 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems PO P0._ SF OUTPUT GNDIO PI0._ OR SF INPUT FLAG INTERRUPT FLAG DETECT CIRCUIT EIEO._ EIES._ Figure 13. Digital I/O Circuitry 30 _______________________________________________________________________________________ 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems The MAXQ7665A–MAXQ7665D are low-cost, high-performance, CMOS, fully static, 16-bit µCs with flash memory and are members of the MAXQ family of µCs. The MAXQ7665A–MAXQ7665D are structured on a highly advanced, accumulator-based, 16-bit RISC architecture. Fetch and execution operations are completed in one cycle without pipelining, because the instruction contains both the operation code and data. The result is a streamlined 8 million instructions-per-second (MIPS) µC. The highly efficient core is supported by a 16-level hardware stack, enabling fast subroutine calling and task switching. Data can be quickly and efficiently manipulated with three internal data pointers. Multiple data pointers allow more than one function to access data memory without having to save and restore data pointers each time. The data pointers can automatically increment or decrement following an operation, eliminating the need for software intervention. As a result, application speed is greatly increased. Instruction Set The instruction set is composed of fixed-length, 16-bit instructions that operate on registers and memory locations. The instruction set is highly orthogonal, allowing arithmetic and logical operations to use any register along with the accumulator. Special-function registers (also called peripheral registers) control the peripherals and are subdivided into register modules. The family architecture is modular, so that new devices and modules can reuse code developed for existing products. The architecture is transport-triggered. This means that writes or reads from certain register locations can also cause side effects to occur. These side effects form the basis for the higher level operation codes defined by the assembler, such as ADDC, OR, JUMP, etc. The operation codes are actually implemented as MOVE instructions between certain register locations, while the assembler handles the encoding, which need not be a concern to the programmer. The 16-bit instruction word is designed for efficient execution. Bit 15 indicates the format for the source field of the instruction. Bits 0 to 7 of the instruction represent the source for the transfer. Depending on the value of the format field, this can either be an immediate value or a source register. If this field represents a register, the lower 4 bits contain the module specifier and the upper 4 bits contain the register index in that module. Bits 8 to 14 represent the destination for the transfer. This value always represents a destination register, with the lower 4 bits containing the module specifier and the upper 3 bits containing the register subindex within that module. Any time that it is necessary to directly select one of the upper 24 registers as a destination, the prefix register, PFX, is needed to supply the extra destination bits. This prefix register write is inserted automatically by the assembler and requires only one additional execution cycle. Memory Organization The MAXQ7665A–MAXQ7665D incorporate several memory areas: • 8KB (4K x 16) utility ROM • Up to 128KB (64K x 16) of flash memory for program storage • 512 bytes (256 x 16) of SRAM for storage of temporary variables • 16-level stack memory for storage of program return addresses and general-purpose use The memory is arranged by default in a Harvard architecture, with separate address spaces for program and data memory (see Figure 14). A special mode allows data memory to be mapped into program space, permitting code execution from data memory. In addition, another mode allows program memory to be mapped into data space, permitting code constants to be accessed as data memory. The incorporation of flash memory allows the devices to be reprogrammed, eliminating the expense of throwing away one-time programmable devices during development and field upgrades (see Figure 15 for the flash memory sector maps). Flash memory can be password protected with a 16-word key, denying access to program memory by unauthorized individuals. ______________________________________________________________________________________ 31 MAXQ7665A–MAXQ7665D MAXQ Core Architecture MAXQ7665A–MAXQ7665D 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems DATA SPACE (BYTE MODE) PROGRAM SPACE DATA SPACE (WORD MODE) A0FFh 256 x 16 DATA SRAM A000h 8FFFh 9FFFh 8K x 8 UTILITY ROM 4K x 16 UTILITY ROM 8000h 8FFFh 4K x 16 UTILITY ROM 8000h 8000h 7FFFh EXECUTING FROM 64KB (32K x 16) PROGRAM FLASH OR MASKED ROM 01FFh 512 x 8 DATA SRAM 0000h 00FFh 256 x 16 DATA SRAM 0000h 0000h Figure 14. MAXQ7665B Memory Map A pseudo-Von Neumann memory map can also be enabled. This places the utility ROM, code, and data memory into a single contiguous memory map. This is useful for applications that require dynamic program modification or unique memory configurations. Stack Memory A 16-bit-wide x 16 deep internal hardware stack provides storage for program return addresses and general-purpose use. The stack is used automatically by the processor when the CALL, RET, and RETI instructions are executed and interrupts serviced. The stack can also be used explicitly to store and retrieve data by using the PUSH, POP, and POPI instructions. operations increment SP, then store a value at the location pointed to by SP. The RET, RETI, POP, and POPI operations retrieve the value at SP and then decrement SP. Utility ROM The utility ROM is an 8KB (4K x 16) block of internal ROM memory that defaults to a starting address of 8000h. The utility ROM consists of subroutines that can be called from application software. These include: • In-system programming (bootstrap loader) over JTAG • In-circuit debug routines • User-callable routines for in-application flash programming and fast table lookup On reset, the stack pointer, SP, initializes to the top of the stack (0Fh). The CALL, PUSH, and interrupt-vectoring 32 _______________________________________________________________________________________ 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems A single password lock (PWL) bit is implemented in the SC register. When the PWL is set to one (POR default), the password is required to access the utility ROM, including in-circuit debug and in-system programming routines that allow reading or writing of internal memory. When PWL is cleared to zero, these utilities are fully accessible without the password. The password is automatically set to all ones following a mass erase. Programming The flash memory of the µC can be programmed by two different methods: in-system programming and inapplication programming. Both methods afford great flexibility in system design as well as reduce the lifecycle cost of the embedded system. These features can be password protected to prevent unauthorized access to program memory. In-System Programming An internal bootstrap loader allows the device to be reloaded over a simple JTAG interface. As a result, software can be upgraded in-system, eliminating the need for a costly hardware retrofit when updates are required. Remote software uploads are possible that enable physically inaccessible applications to be frequently updated. The interface hardware can be a JTAG connection to another µC, or a connection to a PC serial port using a serial-to-JTAG converter such as the MAXQJTAG-001, available from Maxim Integrated Products, Inc. If in-system programmability is not required, a commercial gang programmer can be used for mass programming. After a power-up or reset, the JTAG interface is active and loading the TAP with the system programming instruction invokes the bootstrap loader. Setting the SPE bit to 1 during reset through the JTAG interface executes the bootstrap-loader-mode program that resides in the utility ROM. When programming is complete, the bootstrap loader can clear the SPE bit and reset the device, allowing the device to bypass the utility ROM and begin execution of the application software. The following bootstrap loader functions are supported: • • • • • Load Dump CRC Verify Erase In-Application Programming The in-application programming feature allows the µC to modify its own flash program memory while simultaneously executing its application software. This allows onthe-fly software updates in mission-critical applications that cannot afford downtime. Alternatively, it allows the application to develop custom loader software that can operate under the control of the application software. The utility ROM contains user-accessible flash programming functions that erase and program flash memory. These functions are described in detail in the MAXQ7665/MAXQ7666 User’s Guide for these devices. Register Set Most functions of these devices are controlled by sets of registers. These registers provide a working space for memory operations as well as configuring and addressing peripheral registers on the device. Registers are divided into two major types: system registers and peripheral registers. The common register set, also known as the system registers, includes the ALU, accumulator registers, data pointers, interrupt vectors and control, and stack pointer. The peripheral registers define additional functionality that may be included by different products based on the MAXQ architecture. This functionality is broken up into discrete modules so that only the features required for a given product need to be included. Tables 2 and 4 show the MAXQ7665A– MAXQ7665D register set. Tables 3 and 5 show the bit functions and reset values. ______________________________________________________________________________________ 33 MAXQ7665A–MAXQ7665D Following any reset, execution begins in the utility ROM. The ROM software determines whether the program execution should immediately jump to location 0000h, the start of user-application code, or to one of the special routines mentioned. Routines within the utility ROM are user-accessible and can be called as subroutines by the application software. More information on the utility ROM contents is contained in the MAXQ7665/MAXQ7666 User’s Guide. Some applications require protection against unauthorized viewing of program code memory. For these applications, access to in-system programming, inapplication programming, or in-circuit debugging functions is prohibited until a password has been supplied. The password is defined as the 16 words of physical program memory at addresses 0010h to 001Fh. MAXQ7665A–MAXQ7665D 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems MAXQ7665A (128KB TOTAL) MAXQ7665B (64KB TOTAL) 0x5FFF 0x7FFF 0xFFFF 4K x 16 FLASH 0x3000 0x2FFF 4K x 16 FLASH 4K x 16 FLASH 4K x 16 FLASH 4K x 16 FLASH 0x3FFF 0x5000 0x4FFF 0x7000 0x6FFF 0xEFFF MAXQ7665D (32KB TOTAL) 4K x 16 FLASH 4K x 16 FLASH 4K x 16 FLASH 0xF000 MAXQ7665C (48KB TOTAL) 0xE000 0x6000 0x4000 0x2000 0xDFFF 0x5FFF 0x3FFF 0x1FFF 0xC000 0x4000 0xBFFF 0x3FFF 8K x 16 FLASH 16K x 16 FLASH 8K x 16 FLASH 8K x 16 FLASH 0x0000 0x0000 16K x 16 FLASH 16K x 16 FLASH 0x8000 0x0000 0x7FFF 32K x 16 FLASH 0x0000 Figure 15. Flash Memory Sector Maps 34 _______________________________________________________________________________________ 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems Power consumption reaches its minimum in stop mode. In this mode, the external oscillator, internal RC oscillator, system clock, and all processing activity is halted. Stop mode is exited when an enabled external interrupt input is triggered or an external reset signal is applied to RESET. Upon exiting stop mode, the µC can choose to wait for the external high-frequency crystal to complete its warmup period, or it can start execution immediately from its internal RC oscillator while the warmup period completes. Table 2. System Register Map REGISTER INDEX MODULE NAME (BASE SPECIFIER) AP (8h) A (9h) PFX (Bh) 0h AP A[0] PFX[0] 1h APC A[1] PFX[1] 2h — A[2] PFX[2] 3h — A[3] 4h PSF A[4] 5h IC 6h 7h IP (Ch) SP (Dh) DPC (Eh) DP (Fh) IP — — — — SP — — — IV — — PFX[3] — — OFFS DP0 PFX[4] — — DPC — A[5] PFX[5] — — GR — IMR A[6] PFX[6] — LC0 GRL — — A[7] PFX[7] — LC1 BP DP1 8h SC A[8] — — GRS — 9h — A[9] — — — GRH — Ah — A[10] — — — GRXL — Bh IIR A[11] — — — FP — Ch — A[12] — — — — — Dh — A[13] — — — — — Eh CKCN A[14] — — — — — Fh WDCN A[15] — — — — — Note: Names that appear in italics indicate that all bits of a register are read-only. Names that appear in bold indicate that a register is 16 bits wide. ______________________________________________________________________________________ 35 MAXQ7665A–MAXQ7665D Power Management MAXQ7665A–MAXQ7665D 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems Interrupts Multiple interrupt sources are available for quick response to internal and external events. The MAXQ architecture uses a single interrupt vector (IV), single interrupt-service routine (ISR) design. For maximum flexibility, interrupts can be enabled globally, individually, or by module. When an interrupt condition occurs, its individual flag is set, even if the interrupt source is disabled at the local, module, or global level. Interrupt flags must be cleared within the user-interrupt routine to avoid repeated false interrupts from the same source. Application software must ensure a delay between the write to the flag and the RETI instruction to allow time for the interrupt hardware to remove the internal interrupt condition. Asynchronous interrupt flags require a one-instruction delay and synchronous interrupt flags require a two-instruction delay. When an enabled interrupt is detected, software jumps to a user-programmable interrupt vector location. The IV register defaults to 0000h on reset or power-up, so if it is not changed to a different address, the user program must determine whether a jump to 0000h came from a reset or interrupt source. Once software control has been transferred to the ISR, the interrupt identification register (IIR) can be used to determine if a system register or peripheral register was the source of the interrupt. The specified module can then be interrogated for the specific interrupt source and software can take appropriate action. Because the interrupts are evaluated by user software, the user can define a unique interrupt priority scheme for each application. The following interrupt sources are available. • Watchdog interrupt • External interrupts 0 to 7 • Serial port 0 receive and transmit interrupts 36 • Timer 0 low compare, low overflow, capture/compare, and overflow interrupts • Timer 1 low compare, low overflow, capture/compare, and overflow interrupts • Timer 2 low compare, low overflow, and overflow interrupts • CAN0 receive and transmit interrupts and a change in CAN0 status register interrupt • ADC data ready and overrun interrupts • Digital and I/O voltage brownout interrupts • High-frequency oscillator failure interrupt Reset Sources Several reset sources are provided for µC control. Although code execution is halted in the reset state, the high-frequency oscillator and the internal RC oscillator continue to oscillate. The high-frequency oscillator is turned off by a POR, but not by other reset sources. Internal resets such as the power-on and watchdog resets assert the RESET output low. Power-On Reset (POR) An internal POR circuit enhances system reliability. This circuit forces the device to perform a POR whenever a rising voltage on DVDD climbs above the POR threshold level of 2.7V. At this point the following events occur: • All registers and circuits enter their reset state • The POR flag (WDCN.POR) is set to indicate the source of the reset • The internal RC oscillator becomes the clock source • Code execution begins at location 8000h Watchdog Timer Reset The watchdog timer functions are described in the MAXQ7665/MAXQ7666 User’s Guide. Execution resumes at location 8000h following a watchdog timer reset. _______________________________________________________________________________________ 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems Crystal Selection The MAXQ7665A–MAXQ7665D require a crystal with the following specifications: Frequency: 8MHz CLOAD: 6pF (min) Drive level: 5µW Series resonance resistance: 30Ω max Note: Series resonance resistance is the resistance observed when the resonator is in the series resonant condition. This is a parameter often stated by quartz crystal vendors and is called R1. When a resonator is used in the parallel resonant mode with an external load capacitance, as is the case with the MAXQ7665A–MAXQ7665D oscillator circuit, the effective resistance is sometimes stated. This effective resistance at the loaded frequency of oscillation is: For typical CO and CLOAD values, the effective resistance can be greater than R1 by a factor of 2. Development and Technical Support A variety of highly versatile, affordably priced development tools for this µC are available from Maxim and third-party suppliers, including: • Compilers • Evaluation kits • Integrated development environments (IDEs) • JTAG-to-serial converters for programming and debugging A list of some development-tool vendors can be found at www.maxim-ic.com/microcontrollers. Technical support is available through email at [email protected]. R1 x ( 1 + (CO/CLOAD))2 ______________________________________________________________________________________ 37 MAXQ7665A–MAXQ7665D External System Reset Asserting the external RESET input low causes the device to enter the reset state. The external reset functions as described in the MAXQ7665/MAXQ7666 User’s Guide . Execution resumes at location 8000h after RESET is released. MAXQ7665A–MAXQ7665D 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems Table 3. System Register Bit Functions and Reset Values REGISTER 15 14 13 12 11 10 9 AP APC PSF IC IMR SC IIR CKCN WDCN A[n] (0..15) PFX[n] (0..15) IP SP IV LC[0] LC[1] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 — 0 0 — 0 0 — 0 0 — 0 0 — 0 0 — 0 0 — 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 — 0 GR.15 0 — 0 GR.14 0 — 0 GR.13 0 — 0 GR.12 0 — 0 GR.11 0 — 0 GR.10 0 — 0 GR.9 0 0 GR.7 0 0 GR.6 0 0 GR.5 0 0 GR.4 0 0 GR.3 0 0 GR.2 0 0 GR.1 0 GR.7 0 GR.7 0 GR.7 0 GR.7 0 GR.7 0 GR.7 0 GR.7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFS DPC GR GRL BP GRS GRH GRXL FP DP[0] DP[1] REGISTER BIT 8 7 6 — — 0 0 CLR IDS 0 0 Z S 1 0 — — 0 0 IMS — 0 0 TAP — 1 0 IIS — 0 0 XT — s* 0 POR EWDI s* s* A[n] (16 Bits) 0 0 0 PFX[n] (16 Bits) 0 0 0 IP (16 Bits) 0 0 0 — — — 0 0 0 IV (16 Bits) 0 0 0 LC[0] (16 Bits) 0 0 0 LC[1] (16 Bits) 0 0 0 0 0 — — 0 0 GR.7 GR.6 0 0 GR.7 GR.6 0 0 BP (16 Bits) 0 0 0 GR.0 GR.15 GR.14 0 0 0 GR.15 GR.14 0 0 GR.7 GR.7 GR.6 0 0 0 FP (16 Bits) 0 0 0 DP[0] (16 Bits) 0 0 0 DP[1] (16 Bits) 0 0 0 — 0 GR.8 0 5 — 0 — 0 — 0 CGDS 0 IM5 0 CDA1 0 II5 0 RGMD s* WD1 0 4 — 0 — 0 GPF1 0 — 0 IM4 0 CDA0 0 II4 0 STOP 0 WD0 0 0 — 0 GPF0 0 — 0 IM3 0 UPA 0 II3 0 SWB 0 WDIF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 — 0 0 — 0 0 0 1 0 0 SP (4 Bits) 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 3 2 1 AP (4 Bits) 0 0 MOD2 MOD1 0 0 OV C 0 0 — INS 0 0 IM2 IM1 0 0 ROD PWL 0 s* II2 II1 0 0 — — 0 0 WTRF EWT s* s* 0 0 MOD0 0 E 0 IGE 0 IM0 0 — 0 II0 0 CD0 1 RWT 0 1 0 0 0 0 — 0 GR.5 0 GR.5 0 0 0 OFFS (8 Bits) 0 0 WBS2 WBS1 1 1 GR.4 GR.3 0 0 GR.4 GR.3 0 0 0 WBS0 1 GR.2 0 GR.2 0 0 SDPS1 0 GR.1 0 GR.1 0 0 SDPS0 0 GR.0 0 GR.0 0 0 GR.13 0 GR.13 0 GR.5 0 0 GR.12 0 GR.12 0 GR.4 0 0 GR.11 0 GR.11 0 GR.3 0 0 GR.10 0 GR.10 0 GR.2 0 0 GR.9 0 GR.9 0 GR.1 0 0 GR.8 0 GR.8 0 GR.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 *Bits indicated by an "s" are only affected by a POR and not by other forms of reset. These bits are set to 0 after a POR. Refer to the MAXQ7665/MAXQ7666 User’s Guide for more information. 38 _______________________________________________________________________________________ 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems MAXQ7665A–MAXQ7665D Table 4. Peripheral Register Map MODULE NAME (BASE SPECIFIER) REGISTER INDEX M0 (0h) M1 (1h) M2 (2h) M3 (3h) M4 (4h) M5 (5h) 0h PO0 MCNT T2CNA0 T2CNA2 C0C VMC 1h — MA T2H0 T2H2 C0S APE 2h — MB T2RH0 T2RH2 C0IR ACNT 3h EIF0 MC2 T2CH0 T2CH2 C0TE DCNT 4h — MC1 T2CNA1 — C0RE DACI 5h — MC0 T2H1 — COR — 6h — — T2RH1 — C0DP DACO 7h SBUF0 — T2CH1 — C0DB — 8h PI0 — T2BNB0 T2CNB2 C0RMS ADCD 9h — — T2V0 T2V2 C0TMA TSO Ah — FCNTL T2R0 T2R2 — AIE Bh EIE0 FDATA T2C0 T2C2 — ASR Ch — MC1R T2CNB1 — — OSCC Dh — MC0R T2V1 — — — Eh — — T2R1 — — — Fh — — T2C1 — — — 10h PD0 — T2CFG0 T2CFG2 — — 11h — — T2CFG1 — C0M1C — 12h — — — — C0M2C — 13h EIES0 — — — C0M3C — 14h — — — — C0M4C — 15h — — — — C0M5C — 16h — — — — C0M6C — 17h — — — — C0M7C — 18h — — ICDT0 — C0M8C — 19h — — ICDT1 — C0M9C — 1Ah — — ICDC — C0M10C — — 1Bh — — ICDF — C0M11C 1Ch — Reserved ICDB — C0M12C — 1Dh SCON0 — ICDA — C0M13C — 1Eh SMD0 — ICDD — C0M14C — 1Fh PR0 — — — C0M15C — Note: Names that appear in bold indicate that the register is read-only. ______________________________________________________________________________________ 39 40 EIF0 (M0, 3h) SBUF0 (M0, 7h) PI0 (M0, 8h) EIE0 (M0, Bh) PD0 (M0, 10h) EIES0 (M0, 13h) SCON0 (M0, 1Dh) SMD0 (M0, 1Eh) PR0 (M0, 1Fh) MCNT (M1, 0h) MA (M1, 1h) MB (M1, 2h) MC2 (M1, 3h) MC1 (M1, 4h) MC0 (M1, 5h) FCNTL (M1, Ah) FDATA (M1, Bh) MC1R (M1, Ch) MC0R (M1, Dh) T2CNA0 (M2, 0h) T2H0 (M2, 1h) PO0 (M0, 0h) REGISTER 15 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 PR0.15 0 — 0 MA.15 0 MB.15 0 MC2.15 0 MC1.15 0 MC0.15 0 — 0 FDATA.15 0 MC1R.15 0 MC0R.15 0 — 0 — 0 14 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 PR0.14 0 — 0 MA.14 0 MB.14 0 MC2.14 0 MC1.14 0 MC0.14 0 — 0 FDATA.14 0 MC1R.14 0 MC0R.14 0 — 0 — 0 13 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 PR0.13 0 — 0 MA.13 0 MB.13 0 MC2.13 0 MC1.13 0 MC0.13 0 — 0 FDATA.13 0 MC1R.13 0 MC0R.13 0 — 0 — 0 12 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 PR0.12 0 — 0 MA.12 0 MB.12 0 MC2.12 0 MC1.12 0 MC0.12 0 — 0 FDATA.12 0 MC1R.12 0 MC0R.12 0 — 0 — 0 11 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 PR0.11 0 — 0 MA.11 0 MB.11 0 MC2.11 0 MC1.11 0 MC0.11 0 — 0 FDATA.11 0 MC1R.11 0 MC0R.11 0 — 0 — 0 10 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 PR0.10 0 — 0 MA.10 0 MB.10 0 MC2.10 0 MC1.10 0 MC0.10 0 — 0 FDATA.10 0 MC1R.10 0 MC0R.10 0 — 0 — 0 9 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 PR0.9 0 — 0 MA.9 0 MB.9 0 MC2.9 0 MC1.9 0 MC0.9 0 — 0 FDATA.9 0 MC1R.9 0 MC0R.9 0 — 0 — 0 REGISTER BIT 8 7 — PO0.7 0 1 — IE7 0 0 — SBUF0.7 0 0 — PI0.7 0 ST — EX7 0 0 — PD0.7 0 0 — IT7 0 0 — SM0/FE 0 0 — — 0 0 PR0.8 PR0.7 0 0 — OF 0 0 MA.8 MA.7 0 0 MB.8 MB.7 0 0 MC2.8 MC2.7 0 0 MC1.8 MC1.7 0 0 MC0.8 MC0.7 0 0 — FBUSY 0 1 FDATA.8 FDATA.7 0 0 MC1R.8 MC1R.7 0 0 MC0R.8 MC0R.7 0 0 — ET2 0 0 — T2H0.7 0 0 Table 5. Peripheral Register Bit Functions and Reset Values 6 PO0.6 1 IE6 0 SBUF0.6 0 PI0.6 ST EX6 0 PD0.6 0 IT6 0 SM1 0 — 0 PR0.6 0 MCW 0 MA.6 0 MB.6 0 MC2.6 0 MC1.6 0 MC0.6 0 FERR 0 FDATA.6 0 MC1R.6 0 MC0R.6 0 T2OE0 0 T2H0.6 0 5 PO0.5 1 IE5 0 SBUF0.5 0 PI0.5 ST EX5 0 PD0.5 0 IT5 0 SM2 0 — 0 PR0.5 0 CLD 0 MA.5 0 MB.5 0 MC2.5 0 MC1.5 0 MC0.5 0 FINE 0 FDATA.5 0 MC1R.5 0 MC0R.5 0 T2POL0 0 T2H0.5 0 4 PO0.4 1 IE4 0 SBUF0.4 0 PI0.4 ST EX4 0 PD0.4 0 IT4 0 REN 0 — 0 PR0.4 0 SQU 0 MA.4 0 MB.4 0 MC2.4 0 MC1.4 0 MC0.4 0 FBYP 0 FDATA.4 0 MC1R.4 0 MC0R.4 0 TR2L 0 T2H0.4 0 3 PO0.3 1 IE3 0 SBUF0.3 0 PI0.3 ST EX3 0 PD0.3 0 IT3 0 TB8 0 — 0 PR0.3 0 OPCS 0 MA.3 0 MB.3 0 MC2.3 0 MC1.3 0 MC0.3 0 DQ5 0 FDATA.3 0 MC1R.3 0 MC0R.3 0 TR2 0 T2H0.3 0 2 PO0.2 1 IE2 0 SBUF0.2 0 PI0.2 ST EX2 0 PD0.2 0 IT2 0 RB8 0 ESI 0 PR0.2 0 MSUB 0 MA.2 0 MB.2 0 MC2.2 0 MC1.2 0 MC0.2 0 FC2 0 FDATA.2 0 MC1R.2 0 MC0R.2 0 CPRL2 0 T2H0.2 0 1 PO0.1 1 IE1 0 SBUF0.1 0 PI0.1 ST EX1 0 PD0.1 0 IT1 0 TI 0 SMOD 0 PR0.1 0 MMAC 0 MA.1 0 MB.1 0 MC2.1 0 MC1.1 0 MC0.1 0 FC1 0 FDATA.1 0 MC1R.1 0 MC0R.1 0 SS2 0 T2H0.1 0 0 PO0.0 1 IE0 0 SBUF0.0 0 PI0.0 ST EX0 0 PD0.0 0 IT0 0 RI 0 FEDE 0 PR0.0 0 SUS 0 MA.0 0 MB.0 0 MC2.0 0 MC1.0 0 MC0.0 0 — 0 FDATA.0 0 MC1R.0 0 MC0R.0 0 G2EN 0 T2H0.0 0 MAXQ7665A–MAXQ7665D 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems _______________________________________________________________________________________ ______________________________________________________________________________________ T2CH0 (M2, 3h) T2CNA1 (M2, 4h) T2H1 (M2, 5h) T2RH1 (M2, 6h) T2CH1 (M2, 7h) T2CNB0 (M2, 8h) T2V0 (M2, 9h) T2R0 (M2, Ah) T2C0 (M2, Bh) T2CNB1 (M2, Ch) T2V1 (M2, Dh) T2R1 (M2, Eh) T2C1 (M2, Fh) T2CFG0 (M2, 10h) T2CFG1 (M2, 11b) ICDT0 (M2, 18h) ICDT1 (M2, 19h) ICDC (M2, 1Ah) ICDF (M2, 1Bh) ICDB (M2, 1Ch) ICDA M2, 1Dh) ICDD (M2, 1Eh) T2CNA2 (M3, 0h) T2H2 (M3, 1h) T2RH2 (M3, 2h) T2CH2 (M3, 3h) T2RH0 (M2, 2h) 15 — 0 — 0 — 0 — 0 — 0 — 0 — 0 T2V0.15 0 T2R0.15 0 T2C0.15 0 — 0 T2V1.15 0 T2R1.15 0 T2C1.15 0 — 0 — 0 ICDT0.15 DB ICDT1.15 DB — 0 — 0 — 0 ICDA.15 0 ICDD.15 0 — 0 — 0 — 0 — 0 14 — 0 — 0 — 0 — 0 — 0 — 0 — 0 T2V0.14 0 T2R0.14 0 T2C0.14 0 — 0 T2V1.14 0 T2R1.14 0 T2C1.14 0 — 0 — 0 ICDT0.14 DB ICDT1.14 DB — 0 — 0 — 0 ICDA.14 0 ICDD.14 0 — 0 — 0 — 0 — 0 13 — 0 — 0 — 0 — 0 — 0 — 0 — 0 T2V0.13 0 T2R0.13 0 T2C0.13 0 — 0 T2V1.13 0 T2R1.13 0 T2C1.13 0 — 0 — 0 ICDT0.13 DB ICDT1.13 DB — 0 — 0 — 0 ICDA.13 0 ICDD.13 0 — 0 — 0 — 0 — 0 12 — 0 — 0 — 0 — 0 — 0 — 0 — 0 T2V0.12 0 T2R0.12 0 T2C0.12 0 — 0 T2V1.12 0 T2R1.12 0 T2C1.12 0 — 0 — 0 ICDT0.12 DB ICDT1.12 DB — 0 — 0 — 0 ICDA.12 0 ICDD.12 0 — 0 — 0 — 0 — 0 11 — 0 — 0 — 0 — 0 — 0 — 0 — 0 T2V0.11 0 T2R0.11 0 T2C0.11 0 — 0 T2V1.11 0 T2R1.11 0 T2C1.11 0 — 0 — 0 ICDT0.11 DB ICDT1.11 DB — 0 — 0 — 0 ICDA.11 0 ICDD.11 0 — 0 — 0 — 0 — 0 10 — 0 — 0 — 0 — 0 — 0 — 0 — 0 T2V0.10 0 T2R0.10 0 T2C0.10 0 — 0 T2V1.10 0 T2R1.10 0 T2C1.10 0 — 0 — 0 ICDT0.10 DB ICDT1.10 DB — 0 — 0 — 0 ICDA.10 0 ICDD.10 0 — 0 — 0 — 0 — 0 9 — 0 — 0 — 0 — 0 — 0 — 0 — 0 T2V0.9 0 T2R0.9 0 T2C0.9 0 — 0 T2V1.9 0 T2R1.9 0 T2C1.9 0 — 0 — 0 ICDT0.9 DB ICDT1.9 DB — 0 — 0 — 0 ICDA.9 0 ICDD.9 0 — 0 — 0 — 0 — 0 REGISTERED BIT 8 7 — T2RH0.7 0 0 — T2CH0.7 0 0 — ET2 0 0 — T2H1.7 0 0 — T2RH1.7 0 0 — T2CH1.7 0 0 — ET2L 0 0 T2V0.8 T2V0.7 0 0 T2R0.8 T2R0.7 0 0 T2C0.8 T2C0.7 0 0 — ET2L 0 0 T2V1.8 T2V1.7 0 0 T2R1.8 T2R1.7 0 0 T2C1.8 T2C1.7 0 0 — — 0 0 — — 0 0 ICDT0.8 ICDT0.7 DB DB ICDT1.8 ICDT1.7 DB DB — DME 0 DW — — 0 0 — ICDB.7 0 0 ICDA.8 ICDA.7 0 0 ICDD.8 ICDD.7 0 0 — ET2 0 0 — T2H2.7 0 0 — T2RH2.7 0 0 — T2CH2.7 0 0 6 T2RH0.6 0 T2CH0.6 0 T2OE0 0 T2H1.6 0 T2RH1.6 0 T2CH1.6 0 — 0 T2V0.6 0 T2R0.6 0 T2C0.6 0 — 0 T2V1.6 0 T2R1.6 0 T2C1.6 0 T2DIV2 0 T2DIV2 0 ICDT0.6 DB ICDT1.6 DB — 0 — 0 ICDB.6 0 ICDA.6 0 ICDD.6 0 T2OE0 0 T2H2.6 0 T2RH2.6 0 T2CH2.6 0 5 T2RH0.5 0 T2CH0.5 0 T2POL0 0 T2H1.5 0 T2RH1.5 0 T2CH1.5 0 — 0 T2V0.5 0 T2R0.5 0 T2C0.5 0 — 0 T2V1.5 0 T2R1.5 0 T2C1.5 0 T2DIV1 0 T2DIV1 0 ICDT0.5 DB ICDT1.5 DB REGE DW — 0 ICDB.5 0 ICDA.5 0 ICDD.5 0 T2POL0 0 T2H2.5 0 T2RH2.5 0 T2CH2.5 0 4 T2RH0.4 0 T2CH0.4 0 TR2L 0 T2H1.4 0 T2RH1.4 0 T2CH1.4 0 — 0 T2V0.4 0 T2R0.4 0 T2C0.4 0 — 0 T2V1.4 0 T2R1.4 0 T2C1.4 0 T2DIV0 0 T2DIV0 0 ICDT0.4 DB ICDT1.4 DB — 0 — 0 ICDB.4 0 ICDA.4 0 ICDD.4 0 TR2L 0 T2H2.4 0 T2RH2.4 0 T2CH2.4 0 3 T2RH0.3 0 T2CH0.3 0 TR2 0 T2H1.3 0 T2RH1.3 0 T2CH1.3 0 TF2 0 T2V0.3 0 T2R0.3 0 T2C0.3 0 TF2 0 T2V1.3 0 T2R1.3 0 T2C1.3 0 T2MD 0 T2MD 0 ICDT0.3 DB ICDT1.3 DB CMD3 DW PSS1 0 ICDB.3 0 ICDA.3 0 ICDD.3 0 TR2 0 T2H2.3 0 T2RH2.3 0 T2CH2.3 0 2 T2RH0.2 0 T2CH0.2 0 CPRL2 0 T2H1.2 0 T2RH1.2 0 T2CH1.2 0 TF2L 0 T2V0.2 0 T2R0.2 0 T2C0.2 0 TF2L 0 T2V1.2 0 T2R1.2 0 T2C1.2 0 CCF1 0 CCF1 0 ICDT0.2 DB ICDT1.2 DB CMD2 DW PSS0 0 ICDB.2 0 ICDA.2 0 ICDD.2 0 CPRL2 0 T2H2.2 0 T2RH2.2 0 T2CH2.2 0 1 T2RH0.1 0 T2CH0.1 0 SS2 0 T2H1.1 0 T2RH1.1 0 T2CH1.1 0 TCC2 0 T2V0.1 0 T2R0.1 0 T2C0.1 0 TCC2 0 T2V1.1 0 T2R1.1 0 T2C1.1 0 CCF0 0 CCF0 0 ICDT0.1 DB ICDT1.1 DB CMD1 DW SPE 0 ICDB.1 0 ICDA.1 0 ICDD.1 0 SS2 0 T2H2.1 0 T2RH2.1 0 T2CH2.1 0 0 T2RH0.0 0 T2CH0.0 0 G2EN 0 T2H1.0 0 T2RH1.0 0 T2CH1.0 0 TC2L 0 T2V0.0 0 T2R0.0 0 T2C0.0 0 TC2L 0 T2V1.0 0 T2R1.0 0 T2C1.0 0 C/T2 0 C/T2 0 ICDT0.0 DB ICDT1.0 DB CMD0 DW TXC 0 ICDB.0 0 ICDA.0 0 ICDD.0 0 G2EN 0 T2H2.0 0 T2RH2.0 0 T2CH2.0 0 MAXQ7665A–MAXQ7665D REGISTER Table 5. Peripheral Register Bit Functions and Reset Values (continued) 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems 41 42 T2V2 (M3, 9h) T2R2 (M3, Ah) T2C2 (M3, Dh) T2CFG2 (M3, 10h) C0C (M4, 0h) C0S (M4, 1h) C0IR (M4, 2h) C0TE (M4, 3h) C0RE (M4, 4h) C0R (M4, 5h) C0DP (M4, 6h) C0DB (M4, 7h) C0RMS (M4, 8h) C0TMA (M4, 9h) C0M1C (M4, 11h) C0M2C (M4, 12h) C0M3C (M4, 13h) C0M4C (M4, 14h) C0M5C (M4, 15h) C0M6C (M4, 16h) C0M7C (M4, 17h) C0M8C (M4, 18h) C0M9C (M4, 19h) C0M10C (M4, 1Ah) C0M11C (M4, 1Bh) C0M12C (M4, 1Ch) C0M13C (M4, 1Dh) T2CNB2 (M3, 8h) REGISTER 15 — 0 T2V2.15 0 T2R2.15 0 T2C2.15 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 C0DP.15 0 C0DB.15 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 14 13 12 — — — 0 0 0 T2V2.14 T2V2.13 T2V2.12 0 0 0 T2R2.14 T2R2.13 T2R2.12 0 0 0 T2C2.14 T2C2.13 T2C2.12 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 C0DP.14 C0DP.13 C0DP.12 0 0 0 C0DB.14 C0DB.13 C0DB.12 0 0 0 C0RMS.15 C0RMS.14 C0RMS.13 0 0 0 C0TMA.15 C0TMA.14 C0TMA.13 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — 0 0 0 11 10 — — 0 0 T2V2.11 T2V2.10 0 0 T2R2.11 T2R2.10 0 0 T2C2.11 T2C2.10 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 C0DP.11 C0DP.10 0 0 C0DB.11 C0DB.10 0 0 C0RMS.12 C0RMS.11 0 0 C0TMA.12 C0TMA.11 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 — — 0 0 9 — 0 T2V2.9 0 T2R2.9 0 T2C2.9 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 C0DP.9 0 C0DB.9 0 C0RMS.10 0 C0TMA.10 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 REGISTER BIT 8 7 — ET2L 0 0 T2V2.8 T2V2.7 0 0 T2R2.8 T2R2.7 0 0 T2C2.8 T2C2.7 0 0 — — 0 0 — ERIE 0 0 — BSS 0 0 — INTIN7 0 0 — C0TE.7 0 0 — C0RE.7 0 0 — CAN0BA 0 0 C0DP.8 C0DP.7 0 0 C0DB.8 C0DB.7 0 0 C0RMS.9 C0RMS.8 0 0 C0TMA.9 C0TMA.8 0 0 — MSRDY 0 0 — MSRDY 0 0 — MSRDY 0 0 — MSRDY 0 0 — MSRDY 0 0 — MSRDY 0 0 — MSRDY 0 0 — MSRDY 0 0 — MSRDY 0 0 — MSRDY 0 0 — MSRDY 0 0 — MSRDY 0 0 — MSRDY 0 0 6 — 0 T2V2.6 0 T2R2.6 0 T2C2.6 0 T2DIV2 0 STIE 0 EC96/128 0 INTIN6 0 C0TE.6 0 C0RE.6 0 INCDEC 0 C0DP.6 0 C0DB.6 0 C0RMS.7 0 C0TMA.7 0 ETI 0 ETI 0 ETI 0 ETI 0 ETI 0 ETI 0 ETI 0 ETI 0 ETI 0 ETI 0 ETI 0 ETI 0 ETI 0 5 — 0 T2V2.5 0 T2R2.5 0 T2C2.5 0 T2DIV1 0 PDE 0 WKS 0 INTIN5 0 C0TE.5 0 C0RE.5 0 AID 0 C0DP.5 0 C0DB.5 0 C0RMS.6 0 C0TMA.6 0 ERI 0 ERI 0 ERI 0 ERI 0 ERI 0 ERI 0 ERI 0 ERI 0 ERI 0 ERI 0 ERI 0 ERI 0 ERI 0 Table 5. Peripheral Register Bit Functions and Reset Values (continued) 4 — 0 T2V2.4 0 T2R2.4 0 T2C2.4 0 T2DIV0 0 SIESTA 0 RXS 0 INTIN4 0 C0TE.4 0 C0RE.4 0 C0BPR7 0 C0DP.4 0 C0DB.4 0 C0RMS.5 0 C0TMA.5 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 3 TF2 0 T2V2.3 0 T2R2.3 0 T2C2.3 0 T2MD 0 CRST 1 TXS 0 INTIN3 0 C0TE.3 0 C0RE.3 0 C0BPR6 0 C0DP.3 0 C0DB.3 0 C0RMS.4 0 C0TMA.4 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 2 TF2L 0 T2V2.2 0 T2R2.2 0 T2C2.2 0 CCF1 0 AUTOB 0 ER2 0 INTIN2 0 C0TE.2 0 C0RE.2 0 — 0 C0DP.2 0 C0DB.2 0 C0RMS.3 0 C0TMA.3 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 1 TCC2 0 T2V2.1 0 T2R2.1 0 T2C2.1 0 CCF0 0 ERCS 0 ER1 0 INTIN1 0 C0TE.1 0 C0RE.1 0 C0BIE 0 C0DP.1 0 C0DB.1 0 C0RMS.2 0 C0TMA.2 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 0 TC2L 0 T2V2.0 0 T2R2.0 0 T2C2.0 0 C/T2 0 SWINT 1 ER0 0 INTIN0 0 C0TE.0 0 C0RE.0 0 C0IE 0 C0DP.0 0 C0DB.0 0 C0RMS.1 0 C0TMA.1 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 MAXQ7665A–MAXQ7665D 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems _______________________________________________________________________________________ 15 — 0 — 0 — 0 — 0 ADCMX4 0 — 0 — 0 — 0 — 0 TSO.15 0 — 0 VIOLVL 0 — 0 14 — 0 — 0 — 0 — 0 ADCMX3 0 — 0 — 0 — 0 — 0 TSO.14 0 — 0 DVLVL 0 — 0 13 — 0 — 0 — 0 — 0 ADCMX2 0 — 0 — 0 — 0 — 0 TSO.13 0 — 0 — 0 — 0 12 — 0 — 0 — 0 VIBE 0 ADCMX1 0 — 0 — 0 — 0 — 0 TSO.12 0 — 0 — 0 — 0 11 — 0 — 0 — 0 VDBE 0 ADCMX0 0 — 0 DACI.11 0 DACO.11 0 ADCD.11 0 TSO.11 0 — 0 XHFRY 0 HFOC1 0 10 — 0 — 0 — 0 VDPE 1 ADCDIF 0 — 0 DACI.10 0 DACO.10 0 ADCD.10 0 TSO.10 0 — 0 — 0 HFOC0 0 9 — 0 — 0 — 0 — 0 ADCBIP 0 — 0 DACI.9 0 DACO.9 0 ADCD.9 0 TSO.9 0 — 0 — 0 HFIC1 0 REGISTER BIT 8 7 — MSRDY 0 0 — MSRDY 0 0 — — 0 0 — PGG2 0 0 — — 0 0 — — 0 0 DACI.8 DACI.7 0 0 DACO.8 DACO.7 0 0 ADCD.8 ADCD.7 0 0 TSO.8 TSO.7 0 0 — — 0 0 — — 0 0 HFIC0 ADCCD2 0 0 6 ETI 0 ETI 0 — 0 PGG1 0 ADCDUL 0 DACLD2 0 DACI.6 0 DACO.6 0 ADCD.6 0 TSO.6 0 HFFIE 0 HFFINT 0 ADCCD1 0 5 ERI 0 ERI 0 VIOBI1 0 PGG0 0 — 0 DACLD1 0 DACI.5 0 DACO.5 0 ADCD.5 0 TSO.5 0 VIOBIE 0 VIOBI 0 ADCCD0 0 4 INTRQ 0 INTRQ 0 VIOBI0 0 TSE 0 ADCASD 0 DACLD0 0 DACI.4 0 DACO.4 0 ADCD.4 0 TSO.4 0 DVBIE 0 DVBI 0 — 0 ______________________________________________________________________________________ 3 EXTRQ 0 EXTRQ 0 VDBI1 0 PGAE 0 ADCBY 0 — 0 DACI.3 0 DACO.3 0 ADCD.3 0 TSO.3 0 — 0 — 0 — 0 2 MTRQ 0 MTRQ 0 VDBI0 0 — 0 ADCS2 0 — 0 DACI.2 0 DACO.2 0 ADCD.2 0 TSO.2 0 AORIE 0 ADCOV 0 EXTHF 0 1 ROW/TIH 0 ROW/TIH 0 VDBR1 S DACE 0 ADCS1 0 — 0 DACI.1 0 DACO.1 0 ADCD.1 0 TSO.1 0 ADCIE 0 ADCRY 0 RCE 1 0 DTUP 0 DTUP 0 VDBR0 S ADCE 0 ADCS0 0 — 0 DACI.0 0 DACO.0 0 ADCD.0 0 TSO.0 0 — 1 — 0 HFE 0 MAXQ7665A–MAXQ7665D The OSCC register is cleared to 0002h after a POR and is not affected by other forms of reset. Bits indicated by "DW" are only written to in debug mode. These bits are cleared after a POR. Bits indicated by "DB" have read/write access only in background or debug mode. These bits are cleared after a POR. Bits indicated by "S" are only affected by a POR and not by other forms of reset. These bits are set to 0 after a POR. Bits indicated by "ST" reflect the input signal state. Bits indicated by "—" are unused. C0M15C (M4, 1Fh) VMC (M5, 0h) APE (M5, 1h) ACNT (M5, 2h) DCNT (M5, 3h) DACI (M5, 4h) DACO (M5, 6h) ADCD (M5, 8h) TSO (M5, 9h) AIE (M5, Ah) ASR (M5, Bh) OSCC (M5, Ch) C0M14C (M4, 1Eh) REGISTER Table 5. Peripheral Register Bit Functions and Reset Values (continued) 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems 43 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems MAXQ7665A–MAXQ7665D Typical Operating Circuit AIN0 AIN2 AIN4 AIN6 AIN8 AIN10 AIN12 AIN14 2N3904 TEMPERATURE SENSOR PGA DUAL-BRIDGE SENSOR AIN1 AIN3 AIN5 AIN7 AIN9 AIN11 AIN13 AIN15 VBRIDGEA OUTA+ dr R- R+ dr MUX ~2nF R+ dr dr R- OUTA- ~2nF 12-BIT ADC P0.7/T1 P0.6/T0 P0.5/DACLOAD P0.4/ADCCNV MUX DIGITAL I/O GNDA VBRIDGEB dr R- R+ dr OUTB+ ~2nF 12-BIT DAC DACOUT ~2nF ANALOG OUTPUT R+ dr dr R- OUTB- OR VDD GNDB +12V DUAL-BRIDGE SENSOR UTX VBRIDGEA dr R- R+ dr TXD ~2nF RXD URX P0.3/TCK P0.2/TDI P0.1/TMS P0.0/TD0 GNDA VBRIDGEB dr R- R+ dr OUTB+ JTAG VCC dr R- CANTXD TXD CANRXD RXD R+ dr ~2nF GNDB REFADC 0.1µF UART (LIN 2.0) STBY MAX13050 CAN TRANSCEIVER REFDAC CAN 2.0B +12V IN OUT 10µF VDD (+5V) AVDD 22µF EN HOLD GND MAX5024 LDO 0.1µF 0.01µF SET DVDDIO 0.1µF RESET 0.01µF EXTERNAL RESET IS OPTIONAL RESET XIN MAXQ20 16-BIT RISC MICRO 32/48/64/ 128KB FLASH +3.3V DVDD 4.7µF (0.5Ω ESR MAX) 0.1µF DGND REGEN GNDIO 512 BYTES DATA RAM AGND 8MHz XOUT 44 LIN BUS RXD ~2nF OUTB- LIN MAXQ7665A–MAXQ7665D ~2nF R+ dr dr R- OUTA- TXD LIN TRANSCEIVER AGND OUTA+ _______________________________________________________________________________________ +5V CANH CAN BUS CANL GND 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems DVDDIO P0.7/T1 GNDIO 25 I.C. 29 28 27 26 I.C. 32 31 30 N.C. P0.0/TDO 33 DGND P0.1/TMS 36 35 34 P0.3/TCK P0.2/TDI P0.4/ADCCNV TOP VIEW 24 P0.6/TO P0.5/DACLOAD 37 REGEN 38 23 URX DVDDIO 39 22 UTX DVDD 40 21 CANTXD RESET 41 20 CANRXD 19 DGND XOUT 42 MAXQ7665_ATM XIN 43 18 DGND AVDD 44 17 DACOUT AIN15 45 16 AIN0 AIN14 46 15 AIN1 AIN13 47 14 AIN2 *EXPOSED PAD 13 AIN3 3 4 5 6 7 8 9 10 11 12 AIN10 AIN9 AIN8 AGND REFADC REFDAC AGND AIN7 AIN6 AIN4 2 AIN5 1 AIN11 AIN12 48 TQFN 7mm x 7mm *CONNECT EXPOSED PAD TO AGND. Chip Information PROCESS: BiCMOS and CMOS ______________________________________________________________________________________ 45 MAXQ7665A–MAXQ7665D Pin Configuration MAXQ7665A–MAXQ7665D 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems Package Information Ordering Information PART PIN-PACKAGE FLASH SIZE (KB) MAXQ7665AATM+** 48 TQFN-EP* 128 (64K x 16) MAXQ7665BATM+ 48 TQFN-EP* 64 (32K x 16) MAXQ7665CATM+** 48 TQFN-EP* 48 (24K x 16) MAXQ7665DATM+** 48 TQFN-EP* 32 (16K x 16) For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 48 TQFN-EP T4877MK+6 21-0199 +Devices are only available in lead(Pb)-free packaging. *EP = Exposed pad. **Future Product—contact factory for availability. Note: All devices are specified for operation over the -40°C to +125°C automotive temperature range. 46 _______________________________________________________________________________________ 16-Bit RISC Microcontroller-Based Smart Data-Acquisition Systems REVISION NUMBER REVISION DATE 0 3/08 Initial release 1 10/08 Restricted minimum clock speed DESCRIPTION PAGES CHANGED — 1, 2, 5, 6, 7, 9, 14, 23, 35–38, 40, 44 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 47 © 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. Boblet MAXQ7665A–MAXQ7665D Revision History