AD ADUC834BS

PRELIMINARY TECHNICAL DATA
MicroConverter ®, Dual 16-/24- Bit ADCs
with Embedded 62KB FLASH MCU
Preliminary Technical Data
ADuC834
a
FEATURES
High Resolution Sigma-Delta ADCs
Two Independent ADCs (16- and 24-Bit Resolution)
24-Bit No Missing Codes, Primary ADC
13-Bit p-p Resolution @ 20 Hz, 20 mV Range
18-Bit p-p Resolution @ 20 Hz, 2.56 V Range
Memory
62Kbytes On-Chip Flash/EE Program Memory
4 KBytes On-Chip Flash/EE Data Memory
Flash/EE, 100 Yr Retention, 100 Kcycles Endurance
In Circuit Serial Download
High Speed User Bootload (5s Download)
2304 Bytes On-Chip Data RAM
8051 Based Core
8051-Compatible Instruction Set (12.58 MHz Max)
32 kHz External Crystal, On-Chip Programmable PLL
11 Interrupt Sources, Two Priority Levels
Dual Data Pointer
Extended 11-bit Stack Pointer
On-Chip Peripherals
12-Bit Voltage Output DAC
Dual 16-Bit Σ∆ DACs/PWMs
On-Chip Temperature Sensor
Dual Excitation Current Sources
Time Interval Counter (Real Time Clock/WakeUp Cct)
UART and SPI® Serial I/O
Timer 3 for high speed UART baud rates (incl 115,200)
Watchdog Timer (WDT), Power Supply Monitor (PSM)
Power
Specified for 3 V and 5 V Operation
Normal: 3 mA @ 3 V (Core CLK = 1.5 MHz)
Power-Down: 20µA max with wake-up cct running
GENERAL DESCRIPTION
The ADuC834 is a complete smart transducer front-end, integrating two high-resolution sigma delta ADCs, an 8-bit MCU,
and program/data Flash/EE Memory on a single chip.
The two independent ADCs (Primary and Auxiliary) include a
temperature sensor and a PGA (allowing direct measurement of
low-level signals). The ADCs with on-chip digital filtering and
programmable output data rates are intended for the measurement of wide dynamic range, low frequency signals, such as those
in weigh scale, strain-gauge, pressure transducer, or temperature
measurement applications.
The device operates from a 32 kHz crystal with an on-chip PLL
generating a high-frequency clock of 12.58 MHz. This clock is,
routed through a programmable clock divider from which the
MCU core clock operating frequency is generated. The microcontroller core is an 8052 and therefore 8051 instruction set
compatible with 12 core clock periods per machine cycle.
FUNCTIONAL BLOCK DIAGRAM
A V DD
A D uC 8 34
CU R RE N T
S O UR CE
A V DD
A IN1
A IN2
BUF
MUX
PGA
P R IM A R Y
24-B IT Σ ∆ A D C
12 -BI T
DAC
BUF
IE X C1
IE X C2
DA C
1 6- BI T
DAC
Σ∆
A IN3
A IN4
1 6- BI T
DAC
A G ND
PW M0
Σ∆
A UX IL IA RY
16-B IT Σ ∆ A D C
MUX
A IN5
MUX
16 -BI T
PWM
PW M1
16 -BI T
PWM
TE M P
S EN S O R
805 1-B A S ED M CU W ITH A DD ITIO N A L
P ER IP HE RA LS
IN TE RN A L
B AN DG A P
VRE F
P RO G .
CL O C K
DIV IDE R
E X TE RN A L
VRE F
DE T E C T
OSC
&
PLL
RE FIN ›
RE FIN+
XTAL1
62 K BY TE S FLA S H/E E P R O G R A M M E M O RY
4 K B Y TE S F LA S H/E E DA TA M E M O RY
230 4 B Y TE S U S E R R A M
3 × 1 6 B IT T IM E RS
1 × RE A L TIM E CL O C K
P O W E R S U P PL Y M O N
W AT CH DO G TIM E R
4 × P A RA LLE L
P O RT S
UA R T A N D S P I
S ERIA L I/O
X TA L 2
62 Kbytes of nonvolatile Flash/EE program memory are provided
on-chip. 4 Kbytes of nonvolatile Flash/EE data memory, 256 bytes
RAM and 2 KBytes of extended RAM are also integrated on-chip.
The program memory can be configured as data memory in
datalogging applications.
The ADuC834 also incorporates additional analog functionality
with a 12-bit DAC, dual current sources, power supply monitor,
and a bandgap reference. On-chip digital peripherals include two
16-bit Σ∆ DACs/PWM, watchdog timer, real time clock (time
interval counter), four timers/counters, and two serial I/O ports
(UART and SPI).
On-chip factory firmware supports in-circuit serial download (via
UART), as well as single-pin emulation mode via the EA pin. A
functional block diagram of the ADuC834 is shown above with a
more detailed block diagram shown in figure 11 (page 18).
The part operates from a 3V or a 5V supply. When operating from
3V the power dissipation for the part is below 10mW. The
ADuC834 is housed in a 52-lead MQFP package.
APPLICATIONS
Intelligent Sensors (IEEE1451.2-Compatible)
Weigh Scales
Portable Instrumentation
Pressure Transducers
4–20 mA Transmitters
REV. PrC (12 March 2002)
MicroConverter is a registered trademark of Analog Devices, Inc.
SPI is a registered trademark of Motorola Inc.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA
ADuC834
TABLE OF CONTENTS
OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 8
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 17
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 18
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . 21
SPECIAL FUNCTION REGISTERS (SFRS) . . . . . . . . . . 22
Accumulator (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
B SFR (B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Data Pointer (DPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Program Status Word (PSW) . . . . . . . . . . . . . . . . . . . . . 23
Power Control (PCON) . . . . . . . . . . . . . . . . . . . . . . . . . 23
ADuC834 Configuration SFR (CFG834) . . . . . . . . . . . . 23
Complete SFR Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PRIMARY AND AUXILIARY ADCs . . . . . . . . . . . . . . . . 25
ADCSTAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
ADCMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
ADC0CON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
ADC1CON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
ADC0H/M/L / ADC1H/L . . . . . . . . . . . . . . . . . . . . . . . . 28
OF0H/M/L / OF1H/L . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
GN0H/M/L / GN1H/L . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
ICON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PRIMARY AND AUX ADC NOISE PERFORMANCE . . 30
PRIMARY AND AUXILIARY ADC DESCRIPTION . . . 31
Primary ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Auxiliary ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Analog Input Channels . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Primary and Auxiliary ADC Inputs . . . . . . . . . . . . . . . . . 33
Analog Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . 33
Bipolar/Unipolar Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Burnout Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Excitation Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Reference Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Sigma-Delta Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
ADC Chopping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
NONVOLATILE FLASH/EE MEMORY . . . . . . . . . . . . . 37
Flash/EE Memory Overview . . . . . . . . . . . . . . . . . . . . . . 37
Flash/EE Memory and the ADuC834 . . . . . . . . . . . . . . . 37
ADuC834 Flash/EE Memory Reliability . . . . . . . . . . . . . 37
USING THE FLASH/EE PROGRAM MEMORY . . . . . . 38
Serial/Parallel Downloading . . . . . . . . . . . . . . . . . . . . . . . 38
User Download Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Flash/EE Program Memory Security . . . . . . . . . . . . . . . . 38
USING THE FLASH/EE DATA MEMORY . . . . . . . . . . .
ECON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming the Flash/EE Data Memory . . . . . . . . . . .
FLASH/EE MEMORY TIMING . . . . . . . . . . . . . . . . . . . .
DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DACCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the DAC Converter . . . . . . . . . . . . . . . . . . . . . . . .
PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWMCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ON-CHIP PLL (PLLCON) . . . . . . . . . . . . . . . . . . . . . . . .
TIME INTERVAL COUNTER (TIMECON) . . . . . . . . . .
WATCHDOG TIMER (WDCON) . . . . . . . . . . . . . . . . . .
POWER SUPPLY MONITOR (PSMCON) . . . . . . . . . . .
SERIAL PERIPHERAL INTERFACE . . . . . . . . . . . . . . . .
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPICON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . .
DUAL DATA POINTER (DPCON) . . . . . . . . . . . . . . . . .
8051-COMPATIBLE PERIPHERALS . . . . . . . . . . . . . . . .
Parallel I/O Ports 0–3 . . . . . . . . . . . . . . . . . . . . . . . . . . .
Additional High Current Digital Output Pins . . . . . . . . .
TIMERS/COUNTERS . . . . . . . . . . . . . . . . . . . . . . . . . .
TMOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer/Counter 0/1 Modes of Operation . . . . . . . . . . .
Timer 2 Operating Modes . . . . . . . . . . . . . . . . . . . . . .
T2CON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Operating Modes . . . . . . . . . . . . . . . . . . . . . . .
Baud Rate Generation using Timer 1 and Timer 2 . . .
Baud Rate Generation using Timer 3 . . . . . . . . . . . . .
INTERRUPT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . .
HARDWARE DESIGN CONSIDERATIONS . . . . . . . . . .
External Memory Interface . . . . . . . . . . . . . . . . . . . . . . .
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Reset Operation . . . . . . . . . . . . . . . . . . . . . . .
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Grounding and Board Layout Recommendations . . . . . .
System Self-Identification . . . . . . . . . . . . . . . . . . . . . . . .
Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OTHER HARDWARE CONSIDERATIONS . . . . . . . . . .
In-Circuit Serial Download Access . . . . . . . . . . . . . . . . .
Embedded Serial Port Debugger . . . . . . . . . . . . . . . . . . .
Single-Pin Emulation Mode . . . . . . . . . . . . . . . . . . . . . .
Enhanced-Hooks Emulation Mode . . . . . . . . . . . . . . . . .
Typical System Configuration . . . . . . . . . . . . . . . . . . . . .
QUICKSTART DEVELOPMENT SYSTEM . . . . . . . . . .
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . .
–2–
39
39
40
40
41
41
41
43
43
44
46
47
49
50
51
51
51
52
53
54
54
54
55
55
56
57
58
59
60
60
61
62
63
64
66
66
67
67
67
67
68
68
68
69
69
69
69
69
69
71
72
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
REFIN(+) = 2.5 V, REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz
SPECIFICATIONS1 Crystal;
all specifications T to T unless otherwise noted.)
(AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V,
MIN
Parameter
ADC SPECIFICATIONS
Conversion Rate
Primary ADC
No Missing Codes2
Resolution
Output Noise
Integral Nonlinearity
Offset Error3
Offset Error Drift
Full-Scale Error4
Gain Error Drift5
ADC Range Matching
Power Supply Rejection (PSR)
Common-Mode DC Rejection
On AIN
On AIN
On REFIN
Common-Mode 50 Hz/60 Hz Rejection2
On AIN
ADuC834BS
Test Conditions/Comments
Unit
5.4
105
On Both Channels
Programmable in 0.732 ms Increments
Hz min
Hz max
24
13
18
See Table X and XI
in ADuC834 ADC
Description (pg 30)
±15
±3
±10
±10
±0.5
±2
113
80
20 Hz Update Rate
Range = ±20 mV, 20 Hz Update Rate
Range = ±2.56 V, 20 Hz Update Rate
Output Noise Varies with Selected
Update Rate and Gain Range
Bits min
Bits p-p typ
Bits p-p typ
1 LSB16
ppm of FSR max
µV typ
nV/°C typ
µV typ
ppm/°C typ
µV typ
dBs typ
dBs min
95
113
125
At DC, AIN = 7.8 mV, Range = ±20 mV
At DC, AIN = 1 V, Range = ±2.56 V
At DC, AIN = 1 V, Range = ±2.56 V
20 Hz Update Rate
50 Hz/60 Hz ±1 Hz, AIN = 7.8 mV,
Range = ±20 mV
50 Hz/60 Hz ±1 Hz, AIN = 1 V,
Range = ±2.56 V
50 Hz/60 Hz ±1 Hz, AIN = 1 V,
Range = ±2.56 V
dBs min
dBs typ
dBs typ
50 Hz/60 Hz ±1 Hz, 20 Hz Update Rate
50 Hz/60 Hz ±1 Hz, 20 Hz Update Rate
dBs min
dBs min
95
90
On REFIN
Normal Mode 50 Hz/60 Hz Rejection2
On AIN
On REFIN
Auxiliary ADC
No Missing Codes2
Resolution
Output Noise
Integral Nonlinearity
Offset Error3
Offset Error Drift
Full-Scale Error6
Gain Error Drift5
Power Supply Rejection (PSR)
Normal Mode 50 Hz/60 Hz Rejection2
On AIN
On REFIN
DAC PERFORMANCE
DC Specifications7
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error8
AC Specifications2, 7
Voltage Output Settling Time
Digital-to-Analog Glitch Energy
REV. PrC (12 March 2002)
ADuC834
MAX
90
60
60
16
16
See Table XII in
ADuC834 ADC
Description (pg 30)
±15
–2
1
–2.5
±0.5
80
60
60
AIN = 18 mV
AIN = 7.8 mV, Range = ±20 mV
AIN = 1 V, Range = ±2.56 V
Range = ±2.5 V, 20 Hz Update Rate
Output Noise Varies with Selected
Update Rate
dBs min
dBs min
dBs min
Bits min
Bits p-p typ
AIN = 1 V, 20 Hz Update Rate
ppm of FSR max
LSB typ
µV/°C typ
LSB typ
ppm/°C typ
dBs min
50 Hz/60 Hz ±1 Hz
50 Hz/60 Hz ±1 Hz, 20 Hz Update Rate
dBs min
dBs min
12
±3
–1
±50
±1
±1
AVDD Range
VREF Range
Bits
LSB typ
LSB max
mV max
% max
% typ
15
10
Settling Time to 1 LSB of Final Value
1 LSB Change at Major Carry
µs typ
nVs typ
Guaranteed 12-Bit Monotonic
–3–
PRELIMINARY TECHNICAL DATA
ADuC834–SPECIFICATIONS1
Parameter
INTERNAL REFERENCE
ADC Reference
Reference Voltage
Power Supply Rejection
Reference Tempco
DAC Reference
Reference Voltage
Power Supply Rejection
Reference Tempco
ADuC834BS
Test Conditions/Comments
Unit
1.25 ± 1%
45
100
Initial Tolerance @ 25°C, VDD = 5 V
V min/max
dBs typ
ppm/°C typ
2.5 ± 1%
50
±100
Initial Tolerance @ 25°C, VDD = 5 V
V min/max
dBs typ
ppm/°C typ
ANALOG INPUTS/REFERENCE INPUTS
Primary ADC
Differential Input Voltage Ranges9, 10
Bipolar Mode (ADC0CON3 = 0)
Analog Input Current2
Analog Input Current Drift
Absolute AIN Voltage Limits
Auxiliary ADC
Input Voltage Range9, 10
Average Analog Input Current
Average Analog Input Current Drift2
Absolute AIN Voltage Limits11
External Reference Inputs
REFIN(+) to REFIN(–) Range2
Average Reference Input Current
Average Reference Input Current Drift
‘NO Ext. REF’ Trigger Voltage
ADC SYSTEM CALIBRATION
Full-Scale Calibration Limit
Zero-Scale Calibration Limit
Input Span
ANALOG (DAC) OUTPUTS
Voltage Range
Resistive Load
Capacitive Load
Output Impedance
ISINK
TEMPERATURE SENSOR
Accuracy
Thermal Impedance (θJA)
±20
±40
±80
±160
±320
±640
±1.28
±2.56
±1
±5
AGND + 100 mV
AVDD – 100 mV
0 to VREF
125
±2
AGND – 30 mV
AVDD + 30 mV
1
AVDD
1
±0.1
0.3
0.65
External Reference Voltage = 2.5 V
RN2, RN1, RN0 of ADC0CON Set to
0 0 0 (Unipolar Mode 0 to 20 mV)
0 0 1 (Unipolar Mode 0 to 40 mV)
0 1 0 (Unipolar Mode 0 to 80 mV)
0 1 1 (Unipolar Mode 0 to 160 mV)
1 0 0 (Unipolar Mode 0 to 320 mV)
1 0 1 (Unipolar Mode 0 to 640 mV)
1 1 0 (Unipolar Mode 0 to 1.28 V)
1 1 1 (Unipolar Mode 0 to 2.56 V)
Unipolar Mode, for Bipolar Mode
V
See Note 11
Input Current Will Vary with Input
nA/V typ
Voltage on the Unbuffered Auxiliary ADC pA/V/°C typ
V min
V max
Both ADCs Enabled
NOXREF Bit Active if VREF < 0.3 V
NOXREF Bit Inactive if VREF > 0.65 V
+1.05 × FS
–1.05 × FS
0.8 × FS
2.1 × FS
0 to VREF
0 to AVDD
10
100
0.5
50
mV
mV
mV
mV
mV
mV
V
V
nA max
pA/°C typ
V min
V max
V min
V max
µA/V typ
nA/V/°C typ
V min
V max
V max
V min
V min
V max
DACRN = 0 in DACCON SFR
DACRN = 1 in DACCON SFR
From DAC Output to AGND
From DAC Output to AGND
±2
90
V typ
V typ
Ω typ
pF typ
Ω typ
µA typ
°C typ
°C/Ω typ
–4–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
Parameter
ADuC834BS
TRANSDUCER BURNOUT CURRENT SOURCES
AIN+ Current
–100
AIN– Current
+100
Initial Tolerance @ 25°C
Drift
±10
0.03
EXCITATION CURRENT SOURCES
Output Current
Initial Tolerance @ 25°C
Drift
Initial Current Matching @ 25°C
Drift Matching
Line Regulation (AVDD)
Load Regulation
Output Compliance
LOGIC INPUTS
All Inputs Except SCLOCK, RESET,
and XTAL1
VINL, Input Low Voltage
VINH, Input High Voltage
SCLOCK and RESET Only
(Schmitt-Triggered Inputs)2
VT+
VT–
VT+ – VT–
Input Currents
Port 0, P1.2–P1.7, EA
SCLOCK, MOSI, MISO, SS12
RESET
P1.0, P1.1, Ports 2 and 3
Input Capacitance
Unit
AIN+ is the Selected Positive Input to
the Primary ADC
AIN– is the Selected Negative Input to
the Auxiliary ADC
nA typ
nA typ
% typ
%/°C typ
–200
±10
200
±1
20
1
0.1
AVDD – 0.6
AGND
Available from Each Current Source
µA typ
% typ
ppm/°C typ
Matching Between Both Current Sources % typ
ppm/°C typ
AVDD = 5 V + 5%
µA/V typ
µA/V typ
V max
Min
0.8
0.4
2.0
DVDD = 5 V
DVDD = 3 V
V max
V max
V min
1.3/3
0.95/2.5
0.8/1.4
0.4/1.1
0.3/0.85
0.3/0.85
DVDD = 5 V
DVDD = 3 V
DVDD = 5 V
DVDD = 3 V
DVDD = 5 V
DVDD = 3 V
V
V
V
V
V
V
±10
–10 min, –40 max
±10
±10
35 min, 105 max
VIN = 0 V or VDD
VIN = 0 V, DVDD = 5 V, Internal Pull-Up
VIN = VDD, DVDD = 5 V
VIN = 0 V, DVDD = 5 V
VIN = VDD, DVDD = 5 V,
Internal Pull-Down
VIN = VDD, DVDD = 5 V
VIN = 2 V, DVDD = 5 V
µA max
µA min/µA max
µA max
µA max
µA min/µA max
±10
–180
–660
–20
–75
5
VIN = 450 mV, DVDD = 5 V
All Digital Inputs
CRYSTAL OSCILLATOR (XTAL1 AND XTAL2)
Logic Inputs, XTAL1 Only
VINL, Input Low Voltage
0.8
0.4
VINH, Input High Voltage
3.5
2.5
XTAL1 Input Capacitance
18
XTAL2 Output Capacitance
18
REV. PrC (12 March 2002)
Test Conditions/Comments
DVDD = 5 V
DVDD = 3 V
DVDD = 5 V
DVDD = 3 V
–5–
min/V
min/V
min/V
min/V
min/V
min/V
µA max
µA min
µA max
µA min
µA max
pF typ
V max
V max
V min
V min
pF typ
pF typ
max
max
max
max
max
max
PRELIMINARY TECHNICAL DATA
ADuC834–SPECIFICATIONS1
Parameter
ADuC834BS
Test Conditions/Comments
Unit
VDD = 5 V, ISOURCE = 80 µA
VDD = 3 V, ISOURCE = 20 µA
ISINK = 8 mA, SCLOCK/D0,
MOSI/D1
ISINK = 10 mA, P1.0 and P1.1
ISINK = 1.6 mA, All Other Outputs
V min
V min
V max
2
LOGIC OUTPUTS (Not Including XTAL2)
VOH, Output High Voltage
2.4
2.4
VOL, Output Low Voltage13
0.4
Floating State Leakage Current
Floating State Output Capacitance
POWER SUPPLY MONITOR (PSM)
AVDD Trip Point Selection Range
AVDD Power Supply Trip Point Accuracy
DVDD Trip Point Selection Range
DVDD Power Supply Trip Point Accuracy
WATCHDOG TIMER (WDT)
Timeout Period
MCU CORE CLOCK RATE
MCU Clock Rate2
0.4
0.4
±10
5
2.63
4.63
±3.5
2.63
4.63
±3.5
Four Trip Points Selectable in This Range V min
Programmed via TPA1–0 in PSMCON V max
% max
Four Trip Points Selectable in This Range V min
Programmed via TPD1–0 in PSMCON V max
% max
0
2000
Nine Timeout Periods in This Range
Programmed via PRE3–0 in WDCON
300
1
ms typ
ms typ
OSC_PD Bit = 0 in PLLCON SFR
1
1
1
3.4
ms
ms
ms
ms
Controlled via WDCON SFR
DVDD, 3 V Nominal Operation
DVDD, 5 V Nominal Operation
sec typ
ms typ
ms typ
14
Cycles min
Years min
DVDD and AVDD Can Be Set
Independently
POWER REQUIREMENTS
AVDD, 5 V Nominal Operation
typ
typ
typ
typ
OSC_PD Bit = 1 in PLLCON SFR
0.9
3.3
3.3
FLASH/EE MEMORY RELIABILITY CHARACTERISTICS
Endurance15
100,000
Data Retention16
100
Power Supply Voltages
AVDD, 3 V Nominal Operation
ms min
ms max
Clock Rate Generated via On-Chip PLL
Programmable via CD2–0 Bits in
kHz min
PLLCON SFR
MHz max
98.3
12.58
START-UP TIME
At Power-On
From Idle Mode
From Power-Down Mode
Oscillator Running
Wakeup with INT0 Interrupt
Wakeup with SPI Interrupt
Wakeup with TIC Interrupt
Wakeup with External RESET
Oscillator Powered Down
Wakeup with External RESET
After External RESET in Normal Mode
After WDT Reset in Normal Mode
V max
V max
µA max
pF typ
2.7
3.6
4.75
5.25
2.7
3.6
4.75
5.25
V min
V max
V min
V max
V min
V max
V min
V max
–6–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
Parameter
POWER REQUIREMENTS (continued)
Power Supply Currents Normal Mode17, 18
DVDD Current
AVDD Current
DVDD Current
AVDD Current
Power Supply Currents Idle Mode17, 18
DVDD Current
AVDD Current
DVDD Current
AVDD Current
Power Supply Currents Power-Down Mode17, 18
DVDD Current
AVDD Current
DVDD Current
Typical Additional Power Supply Currents
(AIDD and DIDD)
PSM Peripheral
Primary ADC
Auxiliary ADC
DAC
Dual Current Sources
ADuC834BS
Test Conditions/Comments
Unit
4
2.1
170
15
8
170
DVDD = 4.75 V to 5.25 V, Core CLK = 1.57 MHz
DVDD = 2.7 V to 3.6 V, Core CLK = 1.57 MHz
AVDD = 5.25 V, Core CLK = 1.57 MHz
DVDD = 4.75 V to 5.25 V, Core CLK = 12.58 MHz
DVDD = 2.7 V to 3.6 V, Core CLK = 12.58 MHz
AVDD = 5.25 V, Core CLK = 12.58 MHz
mA max
mA max
µA max
mA max
mA max
µA max
1.2
750
140
2
1
140
DVDD = 4.75 V to 5.25 V, Core CLK = 1.57 MHz
DVDD = 2.7 V to 3.6 V, Core CLK = 1.57 MHz
Measured @ AVDD = 5.25 V, Core CLK = 1.57 MHz
DVDD = 4.75 V to 5.25 V, Core CLK = 12.58 MHz
DVDD = 2.7 V to 3.6 V, Core CLK = 12.58 MHz
Measured at AVDD = 5.25 V, Core CLK = 12.58 MHz
Core CLK = 1.57 MHz or 12.58 MHz
DVDD = 4.75 V to 5.25 V, Osc. On, TIC On
DVDD = 2.7 V to 3.6 V, Osc. On, TIC On
Measured at AVDD = 5.25 V, Osc. On or Osc. Off
DVDD = 4.75 V to 5.25 V, Osc. Off
DVDD = 2.7 V to 3.6 V, Osc. Off
Core CLK = 1.57 MHz, AVDD = DVDD = 5 V
mA max
µA typ
µA typ
mA typ
mA typ
µA typ
50
20
1
20
5
50
1
500
150
400
µA max
µA max
µA max
µA max
µA typ
µA typ
mA typ
µA typ
µA typ
µA typ
NOTES
1
Temperature Range –40°C to +85°C.
2
These numbers are not production tested but are guaranteed by Design and/or Characterization data on production release.
3
System Zero-Scale Calibration can remove this error.
4
The primary ADC is factory calibrated at 25°C with AVDD = DVDD = 5 V yielding this full-scale error of 10 µV. If user power supply or temperature conditions
are significantly different than these, an Internal Full-Scale Calibration will restore this error to 10 µV. A system zero-scale and full-scale calibration will remove
this error altogether.
5
Gain Error Drift is a span drift. To calculate Full-Scale Error Drift, add the Offset Error Drift to the Gain Error Drift times the full-scale input.
6
The auxiliary ADC is factory calibrated at 25°C with AVDD = DVDD = 5 V yielding this full-scale error of –2.5 LSB. A system zero-scale and full-scale calibration
will remove this error altogether.
7
DAC linearity and AC Specifications are calculated using:
reduced code range of 48 to 4095, 0 to VREF,
reduced code range of 48 to 3995, 0 to VDD.
8
Gain Error is a measure of the span error of the DAC.
9
In general terms, the bipolar input voltage range to the primary ADC is given by RangeADC = ±(VREF 2RN)/125, where:
VREF = REFIN(+) to REFIN(–) voltage and V REF = 1.25 V when internal ADC VREF is selected.
RN = decimal equivalent of RN2, RN1, RN0,
e.g., VREF = 2.5 V and RN2, RN1, RN0 = 1, 1, 0 the RangeADC = ±1.28 V.
In unipolar mode the effective range is 0 V to 1.28 V in our example.
10
1.25 V is used as the reference voltage to the ADC when internal VREF is selected via XREF0 and XREF1 bits in ADC0CON and ADC1CON respectively.
11
In bipolar mode, the Auxiliary ADC can only be driven to a minimum of AGND – 30 mV as indicated by the Auxiliary ADC absolute AIN voltage limits. The
bipolar range is still –VREF to +VREF; however, the negative voltage is limited to –30 mV.
12
Pins configured in SPI mode, pins configured as digital inputs during this test.
13
Pins configured in High Current Output mode only.
14
Flash/EE Memory Reliability Characteristics apply to both the Flash/EE program memory and Flash/EE data memory.
15
Endurance is qualified to 100 Kcycles as per JEDEC Std. 22 method A117 and measured at –40°C, +25°C and +85°C, typical endurance at 25°C is 700
Kcycles.
16
Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of
0.6eV will derate with junction temperature as shown in Figure 27 in the Flash/EE Memory description section of this data sheet.
17
Power Supply current consumption is measured in Normal, Idle, and Power-Down Modes under the following conditions:
Normal Mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, Core Executing internal software loop.
Idle Mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, PCON.0 = 1, Core Execution suspended in idle mode.
Power-Down Mode: Reset = 0.4 V, All P0 pins and P1.2–P1.7 pins = 0.4 V, All other digital I/O pins are open circuit, Core Clk changed via CD bits in
PLLCON, PCON.1 = 1, Core Execution suspended in power-down mode, OSC turned ON or OFF via OSC_PD bit (PLLCON.7) in
PLLCON SFR.
18
DVDD power supply current will increase typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle.
Specifications subject to change without notice
REV. PrC (12 March 2002)
–7–
PRELIMINARY TECHNICAL DATA
ADuC834
(AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V; all
MIN to TMAX unless otherwise noted.)
TIMING SPECIFICATIONS1, 2, 3 specifications T
32.768 kHz External Crystal
Min
Typ
Max
Parameter
CLOCK INPUT
tCK
tCKL
tCKH
tCKR
tCKF
1/tCORE
tCORE
tCYC
(External Clock Driven XTAL1)
XTAL1 Period
XTAL1 Width Low
XTAL1 Width High
XTAL1 Rise Time
XTAL1 Fall Time
ADuC834 Core Clock Frequency4
ADuC834 Core Clock Period5
ADuC834 Machine Cycle Time6
30.52
15.16
15.16
20
20
0.098
0.95
12.58
0.636
7.6
122.45
Unit
Figure
µs
µs
µs
ns
ns
MHz
µs
µs
1
1
1
1
1
NOTES
1
AC inputs during testing are driven at DVDD – 0.5 V for a Logic 1, and 0.45 V for a Logic 0. Timing measurements are made at VIH min for a Logic 1, and VIL max
for a Logic 0 as shown in Figure 2.
2
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the
loaded VOH/V OL level occurs as shown in Figure 2.
3
CLOAD for Port0, ALE, PSEN outputs = 100 pF; CLOAD for all other outputs = 80 pF unless otherwise noted.
4
ADuC834 internal PLL locks onto a multiple (384 times) the external crystal frequency of 32.768 kHz to provide a Stable 12.583 MHz internal clock for the
system. The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR.
5
This number is measured at the default Core_Clk operating frequency of 1.57 MHz.
6
ADuC834 Machine Cycle Time is nominally defined as 12/Core_CLK.
tC K R
t C HK
t CK L
tC K F
tC K
Figure 1. XTAL1 Input
DV DD › 0.5 V
V LO A D › 0.1V
0.2DV DD + 0 .9V
TEST POINTS
0.2DV DD › 0.1V
V LO A D
V LO A D + 0.1V
0.45V
TIMING
REFERENCE
POINTS
V LO A D › 0.1V
V LO A D
V LO A D + 0.1V
Figure 2. Timing Waveform Characteristics
–8–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
Parameter
EXTERNAL PROGRAM MEMORY
ALE Pulsewidth
tLHLL
Address Valid to ALE Low
tAVLL
Address Hold after ALE Low
tLLAX
tLLIV
ALE Low to Valid Instruction In
tLLPL
ALE Low to PSEN Low
PSEN Pulsewidth
tPLPH
tPLIV
PSEN Low to Valid Instruction In
tPXIX
Input Instruction Hold after PSEN
Input Instruction Float after PSEN
tPXIZ
tAVIV
Address to Valid Instruction In
tPLAZ
PSEN Low to Address Float
tPHAX
Address Hold after PSEN High
12.58 MHz Core_Clk
Min
Max
Variable Core_Clk
Min
Max
119
39
49
2tCORE – 40
tCORE – 40
tCORE – 30
218
4tCORE – 100
49
193
tCORE – 30
3tCORE – 45
133
3tCORE – 105
0
0
54
292
25
tCORE – 25
5tCORE – 105
25
0
0
CO RE_C LK
tLH LL
A LE (O )
t A V LL
tP L P H
t LL P L
t LL IV
tP L IV
P S E N (O)
P O RT 0 (I/O)
t P X IZ
tP L A Z
tLL A X
tP XIX
P CL
(OUT)
INSTRUCTION
(IN)
t A VIV
tP H A X
P CH
P O RT 2 (O )
Figure 3. External Program Memory Read Cycle
REV. PrC (12 March 2002)
–9–
Unit
Figure
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
3
3
3
3
3
3
3
3
3
3
3
PRELIMINARY TECHNICAL DATA
ADuC834
12.58 MHz Core_Clk
Min
Max
Parameter
EXTERNAL DATA MEMORY READ CYCLE
tRLRH
RD Pulsewidth
tAVLL
Address Valid after ALE Low
tLLAX
Address Hold after ALE Low
RD Low to Valid Data In
tRLDV
tRHDX
Data and Address Hold after RD
tRHDZ
Data Float after RD
ALE Low to Valid Data In
tLLDV
tAVDV
Address to Valid Data In
tLLWL
ALE Low to RD Low
Address Valid to RD Low
tAVWL
tRLAZ
RD Low to Address Float
tWHLH
RD High to ALE High
377
39
44
Variable Core_Clk
Min
Max
6tCORE – 100
tCORE – 40
tCORE – 35
232
0
5tCORE – 165
0
89
486
550
288
188
188
0
119
39
2tCORE – 70
8tCORE – 150
9tCORE – 165
3tCORE + 50
3tCORE – 50
4tCORE – 130
0
tCORE + 40
tCORE – 40
Unit
Figure
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
4
4
4
4
4
4
4
4
4
4
4
CORE _C LK
A LE (O )
tW HL H
P S E N (O)
t LL DV
t LL W L
t R LR H
R D (O)
tA V W L
tR LD V
t A V LL
t LL A X
tR HD X
tR H DZ
t R LA Z
P O RT 0 (I/O)
A0 › A 7
(OUT)
DATA (IN)
t A V DV
P O RT 2 (O )
A1 6 › A 23
A8 › A15
Figure 4. External Data Memory Read Cycle
–10–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
Parameter
12.58 MHz Core_Clk
Min
Max
EXTERNAL DATA MEMORY WRITE CYCLE
WR Pulsewidth
tWLWH
tAVLL
Address Valid after ALE Low
tLLAX
Address Hold after ALE Low
ALE Low to WR Low
tLLWL
tAVWL
Address Valid to WR Low
tQVWX
Data Valid to WR Transition
Data Setup before WR
tQVWH
tWHQX
Data and Address Hold after WR
tWHLH
WR High to ALE High
377
39
44
188
188
29
406
29
39
288
119
Variable Core_Clk
Min
Max
6tCORE – 100
tCORE – 40
tCORE – 35
3tCORE – 50
4tCORE – 130
tCORE – 50
7tCORE – 150
tCORE – 50
tCORE – 40
3tCORE + 50
tCORE + 40
CORE _C LK
A LE (O )
t W HL H
P S E N (O)
t LL W L
tW L W H
W R (O)
tA V W L
t A V LL
tLL A X
tQ V W X
tW H Q X
tQ V W H
P O RT 0 (O )
A0 › A 7
P O RT 2 (O )
A16 › A23
DATA
A8 › A15
Figure 5. External Data Memory Write Cycle
REV. PrC (12 March 2002)
–11–
Unit
Figure
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5
5
5
5
5
5
5
5
PRELIMINARY TECHNICAL DATA
ADuC834
Parameter
12.58 MHz Core_Clk
Min
Typ
Max
UART TIMING (Shift Register Mode)
tXLXL
Serial Port Clock Cycle Time
tQVXH
Output Data Setup to Clock
tDVXH
Input Data Setup to Clock
Input Data Hold after Clock
tXHDX
tXHQX
Output Data Hold after Clock
662
292
0
42
Min
Variable Core_Clk
Typ
0.95
Max
12tCORE
10tCORE – 133
2tCORE + 133
0
2tCORE – 117
Unit
Figure
µs
ns
ns
ns
ns
6
6
6
6
6
A LE (O )
tX L X L
TX D
(OUTP UT CLO CK )
67
01
S E T RI
OR
S E T TI
tQ V X H
tX H Q X
RX D
(OUTP UT DA TA)
MSB
B IT 6
B IT 1
tD V X H
RX D
(INP UT DA TA )
MSB
tX HD X
B IT 6
B IT 1
LSB
Figure 6. UART Timing in Shift Register Mode
–12–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
Parameter
Min
SPI MASTER MODE TIMING (CPHA = 1)
tSL
SCLOCK Low Pulsewidth*
tSH
SCLOCK High Pulsewidth*
Data Output Valid after SCLOCK Edge
tDAV
Data Input Setup Time before SCLOCK Edge
tDSU
tDHD
Data Input Hold Time after SCLOCK Edge
tDF
Data Output Fall Time
Data Output Rise Time
tDR
tSR
SCLOCK Rise Time
tSF
SCLOCK Fall Time
Typ
Max
630
630
50
100
100
10
10
10
10
25
25
25
25
Unit
Figure
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
7
7
7
7
7
7
7
7
NOTE
*Characterized under the following conditions:
a. Core clock divider bits CD2, CD1, and CD0 bits in PLLCON SFR set to 0, 1, and 1 respectively, i.e., core clock frequency = 1.57 MHz and
b. SPI bit-rate selection bits SPR1 and SPR0 bits in SPICON SFR set to 0 and 0 respectively.
S CLO CK
(CP O L = 0)
tS L
tS H
tS R
S CLO CK
(CP O L = 1)
t DA V
tD F
tS F
t DR
M OS I
B IT S 6 › 1
MSB
M IS O
B IT S 6 › 1
M S B IN
t DS U
t D HD
Figure 7. SPI Master Mode Timing (CPHA = 1)
REV. PrC (12 March 2002)
–13–
LS B
LS B IN
PRELIMINARY TECHNICAL DATA
ADuC834
Parameter
Min
SPI MASTER MODE TIMING (CPHA = 0)
tSL
SCLOCK Low Pulsewidth*
tSH
SCLOCK High Pulsewidth*
Data Output Valid after SCLOCK Edge
tDAV
Data Output Setup before SCLOCK Edge
tDOSU
tDSU
Data Input Setup Time before SCLOCK Edge
tDHD
Data Input Hold Time after SCLOCK Edge
Data Output Fall Time
tDF
tDR
Data Output Rise Time
tSR
SCLOCK Rise Time
tSF
SCLOCK Fall Time
Typ
Max
630
630
50
150
100
100
10
10
10
10
25
25
25
25
Unit
Figure
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
8
8
8
8
8
8
8
8
8
NOTE
*Characterized under the following conditions:
a. Core clock divider bits CD2, CD1 and CD0 bits in PLLCON SFR set to 0, 1, and 1 respectively, i.e., core clock frequency = 1.57 MHz and
b. SPI bit-rate selection bits SPR1 and SPR0 bits in SPICON SFR set to 0 and 0 respectively.
S CLO CK
(CP O L = 0)
tS H
tS L
tS R
S CLO CK
(CP O L = 1)
tS F
t DA V
t DO S U
M OS I
M IS O
tD F
MSB
M S B IN
tD S U
tD R
B IT S 6 › 1
B IT S 6 › 1
LS B
LS B IN
tD H D
Figure 8. SPI Master Mode Timing (CPHA = 0)
–14–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
Parameter
Min
SPI SLAVE MODE TIMING (CPHA = 1)
SS to SCLOCK Edge
tSS
SCLOCK Low Pulsewidth
tSL
SCLOCK High Pulsewidth
tSH
tDAV
Data Output Valid after SCLOCK Edge
tDSU
Data Input Setup Time before SCLOCK Edge
Data Input Hold Time after SCLOCK Edge
tDHD
tDF
Data Output Fall Time
tDR
Data Output Rise Time
SCLOCK Rise Time
tSR
tSF
SCLOCK Fall Time
tSFS
SS High after SCLOCK Edge
Typ
Max
0
330
330
50
100
100
10
10
10
10
25
25
25
25
0
SS
tS F S
t SS
S CLO CK
(CP O L = 0)
tD F
tS L
tS H
tS R
tS F
S CLO CK
(CP O L = 1)
t DA V
tD F
M IS O
M OS I
B IT S 6 › 1
MSB
B IT S 6 › 1
M S B IN
tD S U
tD R
tD H D
Figure 9. SPI Slave Mode Timing (CPHA = 1)
REV. PrC (12 March 2002)
–15–
LS B
LS B IN
Unit
Figure
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9
9
9
9
9
9
9
9
9
9
9
PRELIMINARY TECHNICAL DATA
ADuC834
Parameter
Min
SPI SLAVE MODE TIMING (CPHA = 0)
tSS
SS to SCLOCK Edge
tSL
SCLOCK Low Pulsewidth
SCLOCK High Pulsewidth
tSH
Data Output Valid after SCLOCK Edge
tDAV
tDSU
Data Input Setup Time before SCLOCK Edge
tDHD
Data Input Hold Time after SCLOCK Edge
Data Output Fall Time
tDF
tDR
Data Output Rise Time
tSR
SCLOCK Rise Time
SCLOCK Fall Time
tSF
tSSR
SS to SCLOCK Edge
tDOSS
Data Output Valid after SS Edge
tSFS
SS High after SCLOCK Edge
Typ
Max
0
330
330
50
100
100
10
10
10
10
25
25
25
25
50
20
0
Unit
Figure
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
10
10
10
10
10
10
10
10
10
10
10
SS
tS F S
tS S
S CLO CK
(CP O L = 0)
tS H
tS L
tS F
tS R
S CLO CK
(CP O L = 1)
t DA V
t DO S S
tD F
MSB
M IS O
M OS I
M S B IN
tD S U
tD R
B IT S 6 › 1
B IT S 6 › 1
LS B
LS B IN
tD H D
Figure 10. SPI Slave Mode Timing (CPHA = 0)
–16–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
ABSOLUTE MAXIMUM RATINGS1
PIN CONFIGURATION
52-Lead MQFP
(TA = 25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AGND to DGND2 . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . –2 V to +5 V
Analog Input Voltage to AGND3 . . . –0.3 V to AVDD +0.3 V
Reference Input Voltage to AGND . . –0.3 V to AVDD +0.3 V
AIN/REFIN Current (Indefinite) . . . . . . . . . . . . . . . . 30 mA
Digital Input Voltage to DGND . . . . –0.3 V to DVDD +0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DVDD +0.3 V
Operating Temperature Range . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 53.2°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
AGND and DGND are shorted internally on the ADuC834.
3
Applies to P1.2 to P1.7 pins operating in analog or digital input modes.
ORDERING GUIDE
Model
Temperature
Range
Package
Description
Package
Option
ADuC834BS
–40°C to +85°C
52-Lead Plastic Quad Flatpack
S-52
QuickStart Development System
Model
Description
EVAL-ADUC834QS
Development System for the ADuC834 MicroConverter, Containing:
Evaluation Board
Serial Port Cable
Windows® Serial Downloader (WSD)
Windows Debugger/Emulator (with C source DeBug)
Windows ADuC834 Simulator (ADSIM)
Windows ADC Analysis Software Program (WASP)
8051 Assembler (Metalink)
Example Code
Documentation
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADuC834 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
Windows is a registered trademark of Microsoft Corporation.
REV. PrC (12 March 2002)
–17–
PRELIMINARY TECHNICAL DATA
ADuC834
1
2
3
4
9
10
11
28
29
30
31
36
A D u C 834
AIN
M UX
AIN2
PGA
BU F
AIN5
TEMP
S E NS O R
VR EF
RE F IN ⴚ
DE T E CT
M CU
CO R E
P 3.6 (W R )
P 3.5 (T 1)
P 3.4 (T 0)
P 3.3 (IN T 1 )
P 3.2 (IN T 0 )
P 3.0 (RX D )
P 3.1 (T X D)
P 3.7 (R D )
25
BU F
3
DA C
16-BIT
SD DAC
1
PWM0
2
PWM1
M UX
16-BIT
P WM
22
T0
23
T1
1
T2
2
T 2E X
18
IN T 0
19
IN T 1
PLL
S ING L E -P IN
E M UL AT O R
S P I S E RIAL
IN TE R F ACE
O SC
42
26
S CL O CK
/D 0
40
EA
41
17
16-BIT
CO U NT E R
T IM ER S
P O W E R S U P P LY
M O N IT O R
AL E
16
24
T IM E INT E RV A L
CO U NT E R
(W A KE UP C CT )
PSEN
15
22 23
P RO G . CL O CK
DIVIDE R
UA R T
T IM ER
TXD
35
RX D
21
RE S E T
47
DG N D
DV D D
48
DG N D
AG N D
34
DG N D
20
DV D D
6
POR
DV D D
5
AV D D
IE X C 2
UA R T
S E RIA L P O R T
19
12-BIT
V O L T AG E
O UT P UT D AC
W A T CH DO G
T IM ER
DO W N L O AD E R
DE B UG G E R
CU RR E NT
S O U RC E
M UX
IE X C 1
P 2.7 (A 1
P 2.6 (A 1
8052
2 KB ytes US E R X RA M
200 ␮A
18
256 BY T E S US E R
RA M
2 X DA TA P O INT E RS
11-BIT S T AC K P O IN TE R
200 ␮A
17
16-BIT
P WM
4 KB Y TE S D AT A
F L AS H/E E
RE F IN ⴙ
16
PWM
CO N TR O L
62 K BY T E S P RO G R AM
F L AS H/E E IN CL U DIN G
US E R DO W N L O A D M O D E
BA ND G AP
RE F E RE N CE
39
16-BIT
SD DAC
AD C C O NT R O L
AN D
CA L IBR A T IO N
AU X IL IAR Y A DC
16-BIT
⌺⌬ A DC
AIN
M UX
38
AD C
CO N TR O L
AN D
CA L IBR A T IO N
AIN3
AIN4
37
DA C
CO N TR O L
P RIM A RY A DC
24-BIT
⌺⌬ A DC
AIN1
P 2.5 (A 1
P 2.4 (A 1
P 2.3 (A1 1/A19)
P 2.2 (A 1 0 / A 1 8 )
P 2.0 (A 8
12
P 2.1 (A9/ A17)
P 1.7 (AIN 4/DA C )
P 1.6 (AIN3)
P 1.5 (AIN2)
P 1.4 (AIN1)
P 1.3 (AIN5/IE X C 2)
P 1.2 (DA C/IE XC 1)
P 1.0 (T 2)
52
P 1.1 (T 2E X )
P 0.7 (AD 7)
P 0.6 (AD 6)
51
27
14
13
32
33
X T AL 2
50
X T AL 1
49
SS
46
P 0.5 (AD 5)
P 0.4 (AD 4)
P 0.3 (AD 3)
P 0.2 (AD 2)
45
M IS O
44
M OSI
/D1
43
P 0.1 (AD 1)
P 0.0 (AD 0)
ADuC834 DETAILED BLOCK DIAGRAM
* S HA DE D A RE A S RE PRE S E NT THE NE W FE A TURE S O F THE A DUC834 O V E R THE A DUC824
Figure 11. ADuC834 Detailed Block Diagram
ADuC834 PIN BY PIN FUNCTION DESCRIPTION
Pin No.
Mnemonic
Type*
Description
1, 2
P1.0/P1.1
I/O
P1.0/T2/PWM0
I/O
P1.1/T2EX/PWM1
I/O
P1.0 and P1.1 can function as a digital inputs or digital outputs and have a
pull-up configuration as described below for Port 3. P1.0 and P1.1 have an
increased current drive sink capability of 10 mA.
P1.0 and P1.1 also have various secondary functions as described below.
P1.0 can also be used to provide a clock input to Timer 2. When Enabled, counter
2 is incremented in response to a negative transition on the T2 input pin.
If the PWM is enabled then the PWM0 output will appear at this pin.
P1.1 can also be used to provide a control input to Timer 2. When Enabled, a
negative transition on the T2EX input pin will cause a Timer 2 capture or reload
event.
If the PWM is enabled then the PWM1 output will appear at this pin.
–18–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
Pin No.
Mnemonic
Type*
Description
3-4, 9-12
P1.2-P1.7
I
P1.2/DAC/IEXC1
I/O
P1.3/AIN5/IEXC2
P1.4/AIN1
P1.5/AIN2
P1.6/AIN3
P1.7/AIN4/DAC
I/O
I
I
I
I/O
Port 1.2 to Port 1.7 have no digital output driver; they can function as a digital
input for which ‘0’ must be written to the port bit. As a digital input, these pins
must be driven high or low externally.
These pins also have the following analog functionality:
The voltage output from the DAC or one or both current sources (200 µA or 2 x
200 µA) can be configured to appear at this pin.
Auxiliary ADC Input or one or both current sources can be configured at this pin.
Primary ADC, Positive Analog Input
Primary ADC, Negative Analog Input
Auxiliary ADC Input or muxed Primary ADC, Positive Analog Input
Auxiliary ADC Input or muxed Primary ADC, Negative Analog Input. The voltage
output from the DAC can also be configured to appear at this pin.
5
6
AVDD
AGND
S
S
Analog Supply Voltage, 3 V or 5 V
Analog Ground. Ground reference pin for the analog circuitry.
7
8
REFIN(–)
REFIN(+)
I
I
Reference input, negative terminal.
Reference input, positive terminal.
13
14
SS
MISO
I
I/O
Slave Select Input for the SPI Interface. A weak pull-up is present on this pin.
Master Input/Slave Output for the SPI Interface. There is a weak pull-up on this
input pin.
15
RESET
I
Reset Input. A high level on this pin for 16 core clock cycles while the oscillator is
running resets the device. There is an internal weak pull-down and a Schmitt
trigger input stage on this pin.
16–19,
22-25
P3.0–P3.7
I/O
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P3.7/RD
I/O
P3.0–P3.7 are bidirectional port pins with internal pull-up resistors. Port 3 pins
that have 1s written to them are pulled high by the internal pull-up resistors, and
in that state can be used as inputs. As inputs, Port 3 pins being pulled externally
low will source current because of the internal pull-up resistors. When driving a
0-to-1 output transition, a strong pull-up is active for two core clock periods of
the instruction cycle.
Port 3 pins also have various secondary functions described below.
Receiver Data for UART serial Port
Transmitter Data for UART serial Port
External Interrupt 0. This pin can also be used as a gate control input to Timer0.
External Interrupt 1. This pin can also be used as a gate control input to Timer1.
Timer/Counter 0 External Input
Timer/Counter 1 External Input
External Data Memory Write Strobe. Latches the data byte from Port 0 into an
external data memory.
External Data Memory Read Strobe. Enables the data from an external data
memory to Port 0.
20, 34, 48
21, 35, 47
DVDD
DGND
S
S
Digital supply, 3 V or 5 V.
Digital ground, ground reference point for the digital circuitry.
26
SCLOCK/D0
I/O
27
MOSI/D1
I/O
Serial interface clock for the SPI interface. As an input this pin is a Schmitt
triggered input and a weak internal pull-up is present on this pin unless it is
outputting logic low.
This pin can also be controlled directly in software as a digital output pin.
Serial master output/slave input data for the SPI interface. A weak internal
pull-up is present on this pin unless it is outputting logic low.
This pin can also be controlled directly in software as a digital output pin.
REV. PrC (12 March 2002)
–19–
PRELIMINARY TECHNICAL DATA
ADuC834
Pin No.
Mnemonic
Type*
Description
28–31
36-39
P2.0–P2.7
(A8–A15)
(A16–A23)
I/O
Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s
written to them are pulled high by the internal pull-up resistors, and in that state can
be used as inputs. As inputs, Port 2 pins being pulled externally low will source current
because of the internal pull-up resistors.
Port 2 emits the high order address bytes during fetches from external program
memory and middle and high order address bytes during accesses to the 24-bit
external data memory space.
32
33
XTAL1
XTAL2
I
O
Input to the crystal oscillator inverter.
Output from the crystal oscillator inverter. (see page 68 for description)
40
EA
I/O
External Access Enable, Logic Input. When held high, this input enables the device
to fetch code from internal program memory locations 0000h to F800h. When held
low this input enables the device to fetch all instructions from external program
memory. To determine the mode of code execution, i.e., internal or external, the
EA pin is sampled at the end of an external RESET assertion or as part of a device
power cycle.
EA may also be used as an external emulation I/O pin and therefore the voltage
level at this pin must not be changed during normal mode operation as it may
cause an emulation interrupt that will halt code execution.
41
PSEN
O
Program Store Enable, Logic Output. This output is a control signal that enables
the external program memory to the bus during external fetch operations. It is
active every six oscillator periods except during external data memory accesses.
This pin remains high during internal program execution.
PSEN can also be used to enable serial download mode when pulled low through a
resistor at the end of an external RESET assertion or as part of a device power cycle.
42
ALE
O
Address Latch Enable, Logic Output. This output is used to latch the low byte (and
page byte for 24-bit data address space accesses) of the address to external memory
during external code or data memory access cycles. It is activated every six oscillator
periods except during an external data memory access. It can be disabled by setting
the PCON.4 bit in the PCON SFR.
43–46
49–52
P0.0–P0.7
(AD0–AD3)
(AD4–AD7)
I/O
P0.0–P0.7, these pins are part of Port0 which is an 8-bit open-drain bidirectional
I/O port. Port 0 pins that have 1s written to them float and in that state can be used
as high impedance inputs. An external pull-up resistor will be required on P0
outputs to force a valid logic high level externally. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program or data memory.
In this application it uses strong internal pull-ups when emitting 1s.
*I = Input, O = Output, S = Supply.
NOTES
1. In the following descriptions, SET implies a Logic 1 state and CLEARED implies a Logic 0 state unless otherwise stated.
2. In the following descriptions, SET and CLEARED also imply that the bit is set or automatically cleared by the ADuC834 hardware unless otherwise stated.
3. User software should not write 1s to reserved or unimplemented bits as they may be used in future products.
–20–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
MEMORY ORGANIZATION
The ADuC834 contains 4 different memory blocks namely:
- 62kBytes of On-Chip Flash/EE Program Memory
- 4kBytes of On-Chip Flash/EE Data Memory
- 256 Bytes of General Purpose RAM
- 2kBytes of Internal XRAM
if one is going to use more than one register bank, the stack
pointer should be initialized to an area of RAM not used for data
storage.
7FH
G ENE RA L-P URP OS E
A RE A
30H
(1) Flash/EE Program Memory
The ADuC834 provides 62kBytes of Flash/EE program
memory to run user code. The user can choose to run code
from this internal memory or run code from an external program memory.
If the user applies power or resets the device while the EA pin
is pulled low, the part will execute code from the external program space, otherwise the part defaults to code execution
from its internal 62kBytes of Flash/EE program memory. Unlike the ADuC824, where code execution can overflow from the
internal code space to external code space once the PC becomes greater than 1FFFh, the ADuC834 does not support the
rollover from F7FFh in internal code space to F800h in external code space. Instead the 2048 bytes between F800h and
FFFFh will appear as NOP instructions to user code.
This internal code space can be downloaded via the UART
serial port while the device is in-circuit.
56kBytes of the program memory can be repogrammed during
runtime hence the code space can be upgraded in the field
using a user defined protocol or it can be used as a data
memory. This will be discussed in more detail in the Flash/EE
Memory section of the datasheet.
(2) Flash/EE Data Memory
4kBytes of Flash/EE Data Memory are available to the user
and can be accessed indirectly via a group of control registers
mapped into the Special Function Register (SFR) area. Access
to the Flash/EE Data memory is discussed in detail later as part
of the Flash/EE memory section in this data sheet.
2FH
B A NK S
B IT-A DDRE S S A B LE
(BIT A DDRE S S E S )
S E LE CTE D
V IA
20H
B ITS IN P S W
1FH
11
18H
17H
10
10H
0FH
01
08H
07H
00
RE S E T V ALUE OF
S TACK P OINTE R
00H
Figure 12. Lower 128 Bytes of Internal Data Memory
The ADuC834 contains 2048 bytes of internal XRAM, 1792
bytes of which can be configured to be used as an extended 11bit stack pointer.
By default the stack will operate exactly like an 8052 in that it
will rollover from FFh to 00h in the general purpose RAM. On
the ADuC834 however it is possible (by setting CFG834.7) to
enable the 11-bit extended stack pointer. In this case the stack
will rollover from FFh in RAM to 0100h in XRAM.
The 11-bit stack pointer is visable in the SP and SPH SFRs.
The SP SFR is located at 81h as with a standard 8052. The
SPH SFR is located at B7h. The 3 LSBs of this SFR contain
the 3 extra bits necessary to extend the 8-bit stack pointer into
an 11-bit stack pointer.
(3) General Purpose RAM
07FFH
The general purpose RAM is divided into two seperate memories, namely the upper and the lower 128 bytes of RAM. The
lower 128 bytes of RAM can be accessed through direct or
indirect addressing while the upper 128 bytes of RAM can
only be accessed through indirect addressing as it shares the
same address space as the SFR space which can only be accessed through direct addressing.
The lower 128 bytes of internal data memory are mapped as
shown in Figure 12. The lowest 32 bytes are grouped into
four banks of eight registers addressed as R0 through R7. The
next 16 bytes (128 bits), locations 20Hex through 2FHex
above the register banks, form a block of directly addressable
bit locations at bit addresses 00H through 7FH. The stack can
be located anywhere in the internal memory address space, and
the stack depth can be expanded up to 2048 bytes.
Reset initializes the stack pointer to location 07 hex and increments it once before loading the stack to start from locations 08
hex which is also the first register (R0) of register bank 1. Thus,
REV. PrC (12 March 2002)
FOUR B A NK S O F EIG HT
RE G IS TE RS
R0 R7
UP P E R 1792
B Y TES O F
O N-CHIP X RA M
(DA TA +S TA CK
FOR E X S P =1,
DA TA O NLY
FOR E X S P =0)
CFG 834.7 = 0
CFG 834.7 = 1
100H
FFH
LOW E R 256
B Y TES O F
O N-CHIP X RA M
(DA TA ONLY )
256 B Y TES O F
O N-CHIP DA TA
RA M
(DA TA + S TA CK )
00H
00H
Figure 13. Extended Stack Pointer Operation
–21–
PRELIMINARY TECHNICAL DATA
ADuC834
SPECIAL FUNCTION REGISTERS (SFRs)
External Data Memory (External XRAM)
Just like a standard 8051 compatible core the ADuC834 can
access external data memory using a MOVX instruction. The
MOVX instruction automatically outputs the various control
strobes required to access the data memory.
The ADuC834 however, can access up to 16MBytes of extrenal
data memory. This is an enhancement of the 64kBytes external
data memory space available on a standard 8051 compatible
core.
The external data memory is discussed in more detail in the
ADuC834 Hardware Design Considerations section.
The SFR space is mapped into the upper 128 bytes of internal
data memory space and accessed by direct addressing only. It
provides an interface between the CPU and all on chip peripherals. A block diagram showing the programming model of the
ADuC834 via the SFR area is shown in Figure 15.
All registers except the Program Counter (PC) and the four
general-purpose register banks, reside in the SFR area. The
SFR registers include control, configuration, and data registers that provide an interface between the CPU and all on-chip
peripherals.
Internal XRAM
2kBytes of on-chip data memory exist on the ADuC834. This
memory although on-chip is also accessed via the MOVX instruction. The 2kBytes of internal XRAM are mapped into the
bottom 2kBytes of the external address space if the CFG834.0
bit is set, otherwise access to the external data memory will
occur just like a standard 8051.
4 KB Y TE
E LE CTRICA LLY
REPRO GRA MM ABLE
NO NV O LA TILE
FLA S H/E E DA TA
M EM O RY
62 K B Y TE E LECTRICA LLY
REPRO GRA MM ABLE
NO NV O LA TILE FLA S H/EE
P RO GRAM M E MO RY
8051CO M PA TIB LE
CO RE
Even with the CFG834.0 bit set access to the external XRAM
will occur once the 24 bit DPTR is greater than 0007FFH.
When accessing the internal XRAM the P0, P2 port pins as well
as the RD and WR strobes will not be output as per a standard
8051 MOVX instruction. This allows the user to use these port
pins as standard I/O.
128-B Y TE
S P ECIA L
FUNCTION
RE G IS TE R
A RE A
DUA L
S IGM A -DE LTA
A DCs
O THER ON-CHIP
P E RIP HE RALS
256 B YTE S RA M
2K X RAM
TE MP SENSOR
CURRENT S OURCE S
12-B IT DA C
S E RIA L I/O
W DT, PS M
TIC, P LL
FFFFFFH
FFFFFFH
Figure 15. Programming Model
Accumulator SFR (ACC)
E X TE RNA L
DA TA
M EM O RY
S P A CE
(24-B IT
A DDRE S S
S P A CE )
E X TE RNA L
DA TA
M EM O RY
S P A CE
(24-B IT
A DDRE S S
S P A CE )
000800H
0007F FH
000000H
000000 H
CFG 834.0=0
2 KB Y TE S
O N-CHIP
X RA M
CFG 834.0=1
Figure 14. Internal and External XRAM
ACC is the Accumulator register and is used for math operations including addition, subtraction, integer multiplication and
division, and Boolean bit manipulations. The mnemonics for
accumulator-specific instructions refer to the Accumulator as
A.
B SFR (B)
The B register is used with the ACC for multiplication and
division operations. For other instructions it can be treated
as a general-purpose scratchpad register.
Stack Pointer (SP and SPH)
The SP SFR is the stack pointer and is used to hold an internal
RAM address that is called the ‘top of the stack.’ The SP register
is incremented before data is stored during PUSH and CALL
executions. While the Stack may reside anywhere in on-chip
RAM, the SP register is initialized to 07H after a reset. This
causes the stack to begin at location 08H.
As mentioned earlier the ADuC834 offers an extended 11-bit
stack pointer. The 3 extra bits to make up the 11-bit stack
pointer are the 3 LSBs of the SPH byte located at B7h.
–22–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
Data Pointer (DPTR)
The Data Pointer is made up of three 8-bit registers, named
DPP (page byte), DPH (high byte) and DPL (low byte).
These are used to provide memory addresses for internal and
external code access and external data access. It may be manipulated as a 16-bit register (DPTR = DPH, DPL), although
INC DPTR instructions will automatically carry over to DPP,
or as three independent 8-bit registers (DPP, DPH, DPL).
The ADuC834 supports dual data pointers. Refer to the Dual
Data Pointer section later in this datasheet.
ADuC834 Configuration SFR (CFG834)
The CFG834 SFR contains the necessary bits to configure the
internal XRAM and the extended SP. By default it configures
the user into 8051 mode. i.e. extended SP is disabled, internal
XRAM is disabled.
Program Status Word (PSW)
The PSW SFR contains several bits reflecting the current status
of the CPU as detailed in Table I.
Bit
Name
Description
7
EXSP
6
5
4
3
2
1
0
------------------XRAMEN
Extended SP Enable
If this bit is set then the stack will
rollover from SPH/SP = 00FFh to
0100h.
If this bit is clear then the SPH SFR
will be disabled and the stack will
rollover from SP=FFh to SP =00h
------------------XRAM Enable Bit
If this bit is set then the internal
XRAM will be mapped into the lower
2kBytes of the external address space.
If this bit is clear then the internal
XRAM will not be accessible and the
external data memory will be mapped
into the lower 2kBytes of external data
memory. (see fig 14)
SFR Address
Power ON Default Value
Bit Addressable
SFR Address
Power ON Default Value
Bit Addressable
Table III. CFG834 SFR Bit Designations
D0H
00H
Yes
Table I. PSW SFR Bit Designations
Bit
Name
Description
7
6
5
4
3
CY
AC
F0
RS1
RS0
2
1
0
OV
F1
P
Carry Flag
Auxiliary Carry Flag
General-Purpose Flag
Register Bank Select Bits
RS1
RS0
Selected Bank
0
0
0
0
1
1
1
0
2
1
1
3
Overflow Flag
General-Purpose Flag
Parity Bit
Power Control SFR (PCON)
The PCON SFR contains bits for power-saving options and
general-purpose status flags as shown in Table II.
SFR Address
Power ON Default Value
Bit Addressable
.
87H
00H
No
Table II. PCON SFR Bit Designations
Bit
Name
Description
7
6
SMOD
SERIPD
5
INT0PD
4
3
2
1
0
ALEOFF
GF1
GF0
PD
IDL
Double UART Baud Rate
SPI Power-Down Interrupt
Enable
INT0 Power-Down Interrupt
Enable
Disable ALE Output
General-Purpose Flag Bit
General-Purpose Flag Bit
Power-Down Mode Enable
Idle Mode Enable
REV. PrC (12 March 2002)
AFhH
00H
No
–23–
PRELIMINARY TECHNICAL DATA
ADuC834
COMPLETE SFR MAP
Figure 16 below shows a full SFR memory map and the SFR
contents after RESET. NOT USED indicates unoccupied SFR
locations. Unoccupied locations in the SFR address space are
not implemented; i.e., no register exists at this location. If an
unoccupied location is read, an unspecified value is returned.
SFR locations that are reserved for future use are shaded
(RESERVED) and should not be accessed by user software.
*CALIBRATION COEFFICIENTS ARE PRECONFIGURED AT POWER-UP TO FACTORY CALIBRATED VALUES.
SFR MAP KEY:
THESE BITS ARE CONTAINED IN THIS BYTE.
BIT MNEMONIC
BIT BIT ADDRESS
IE0
89H
TCON
IT0
0 88H
0
88H
00H
DEFAULT BIT VALUE
MNEMONIC
DEFAULT VALUE
SFR ADDRESS
SFR NOTE:
SFRs WHOSE ADDRESSES END IN 0H OR 8H ARE BIT-ADDRESSABLE.
Figure 16. Special Function Register Locations and Reset Values
–24–
(12 March 2002) REV. prC
PRELIMINARY TECHNICAL DATA
ADuC834
USER INTERFACE TO THE PRIMARY AND
AUXILIARY ADCS
Both ADCs are controlled and configured via a number of
SFRs that are mentioned here and described in more detail
in the following pages.
ADCSTAT:
ADC Status Register. Holds general status of
the Primary and Auxiliary ADCs.
ADC0L/M/H:
Primary ADC 24-bit conversion result held
in these three 8-bit registers.
ADCMODE:
ADC Mode Register. Controls general modes
of operation for Primary and Auxiliary ADCs.
ADC1L/H:
Auxiliary ADC 16-bit conversion result held
in these two 8-bit registers.
ADC0CON:
Primary ADC Control Register. Controls
specific configuration of Primary ADC.
OF0L/M/H:
Primary ADC 24-bit Offset Calibration Coefficient held in these three 8-bit registers.
ADC1CON:
Auxiliary ADC Control Register. Controls
specific configuration of Auxiliary ADC.
OF1L/H:
Auxiliary ADC 16-bit Offset Calibration
Coefficient held in these two 8-bit registers.
SF:
Sinc Filter Register. Configures the decimation
factor for the Sinc3 filter and thus the Primary
and Auxiliary ADC update rates.
GN0L/M/H:
Primary ADC 24-bit Gain Calibration
Coefficient held in these three 8-bit registers.
GN1L/H:
ICON:
Current Source Control Register. Allows
user control of the various on-chip current
source options.
Auxiliary ADC 16-bit Gain Calibration Coefficient held in these two 8-bit registers.
ADCSTAT—(ADC Status Register)
This SFR reflects the status of both ADCs including data ready, calibration and various (ADC-related) error and warning conditions including reference detect and conversion overflow/underflow flags.
SFR Address
Power-On Default Value
Bit Addressable
D8H
00H
Yes
Table IV. ADCSTAT SFR Bit Designations
Bit
Name
Description
7
RDY0
6
RDY1
5
CAL
4
NOXREF
3
ERR0
2
ERR1
1
0
-----
Ready Bit for Primary ADC.
Set by hardware on completion of ADC conversion or calibration cycle.
Cleared directly by the user or indirectly by write to the mode bits to start another Primary
ADC conversion or calibration. The Primary ADC is inhibited from writing further results to its
data or calibration registers until the RDY0 bit is cleared.
Ready Bit for Auxiliary ADC.
Same definition as RDY0 referred to the Auxiliary ADC.
Calibration Status Bit.
Set by hardware on completion of calibration.
Cleared indirectly by a write to the mode bits to start another ADC conversion or calibration.
No External Reference Bit (only active if Primary or Auxiliary ADC is active).
Set to indicate that one or both of the REFIN pins is floating or the applied voltage is below
a specified threshold. When Set conversion results are clamped to all ones, if using ext.
reference.
Cleared to indicate valid VREF.
Primary ADC Error Bit.
Set by hardware to indicate that the result written to the Primary ADC data registers has
been clamped to all zeros or all ones. After a calibration this bit also flags error conditions that
caused the calibration registers not to be written.
Cleared by a write to the mode bits to initiate a conversion or calibration.
Auxiliary ADC Error Bit.
Same definition as ERR0 referred to the Auxiliary ADC.
Reserved for Future use.
Reserved for Future use.
REV. PrC (12 March 2002)
–25–
PRELIMINARY TECHNICAL DATA
ADuC834
ADCMODE (ADC Mode Register)
Used to control the operational mode of both ADCs.
SFR Address
Power-On Default Value
Bit Addressable
D1H
00H
No
Table V. ADCMODE SFR Bit Designations
Bit
Name
Description
7
6
5
----ADC0EN
4
ADC1EN
3
2
1
0
--MD2
MD1
MD0
Reserved for Future Use.
Reserved for Future Use.
Primary ADC Enable.
Set by the user to enable the Primary ADC and place it in the mode selected in MD2-MD0 below
Cleared by the user to place the Primary ADC in power-down mode.
Auxiliary ADC Enable.
Set by the user to enable the Auxiliary ADC and place it in the mode selected in MD2-MD0 below
Cleared by the user to place the Auxiliary ADC in power-down mode.
Reserved for Future Use.
Primary and Auxiliary ADC Mode bits.
These bits select the operational mode of the enabled ADC as follows:
MD2
MD1
MD0
0
0
0
ADC Power-Down Mode (Power-On Default)
0
0
1
Idle Mode
In Idle Mode the ADC filter and modulator are held in a reset state
although the modulator clocks are still provided.
0
1
0
Single Conversion Mode
In Single Conversion Mode, a single conversion is performed on the
enabled ADC. On completion of the conversion, the ADC data registers (ADC0H/M/L and/or ADC1H/L) are updated, the relevant flags
in the ADCSTAT SFR are written, and power-down is re-entered with
the MD2–MD0 accordingly being written to 000.
0
1
1
Continuous Conversion
In continuous conversion mode the ADC data registers are regularly
updated at the selected update rate (see SF register)
1
0
0
Internal Zero-Scale Calibration
Internal short automatically connected to the enabled ADC(s)
1
0
1
Internal Full-Scale Calibration
Internal or External VREF (as determined by XREF0 and XREF1 bits
in ADC0/1CON) is automatically connected to the ADC input for
this calibration.
1
1
0
System Zero-Scale Calibration
User should connect system zero-scale input to the ADC input pins
as selected by CH1/CH0 and ACH1/ACH0 bits in the ADC0/1CON
register.
1
1
1
System Full-Scale Calibration
User should connect system full-scale input to the ADC input pins as
selected by CH1/CH0 and ACH1/ACH0 bits in the ADC0/1CON
register.
NOTES
1. Any change to the MD bits will immediately reset both ADCs. A write to the MD2–0 bits with no change is also treated as a reset. (See exception to this in Note 3
below.)
2. If ADC0CON is written when ADC0EN = 1, or if ADC0EN is changed from 0 to 1, then both ADCs are also immediately reset. In other words, the Primary
ADC is given priority over the Auxiliary ADC and any change requested on the primary ADC is immediately responded to.
3. On the other hand, if ADC1CON is written or if ADC1EN is changed from 0 to 1, only the Auxiliary ADC is reset. For example, if the Primary ADC is continuously converting when the Auxiliary ADC change or enable occurs, the primary ADC continues undisturbed. Rather than allow the Auxiliary ADC to operate with a
phase difference from the primary ADC, the Auxiliary ADC will fall into step with the outputs of the primary ADC. The result is that the first conversion time
for the Auxiliary ADC will be delayed up to three outputs while the Auxiliary ADC update rate is synchronized to the Primary ADC.
4. Once ADCMODE has been written with a calibration mode, the RDY0/1 bits (ADCSTAT) are immediately reset and the calibration commences. On completion, the appropriate calibration registers are written, the relevant bits in ADCSTAT are written, and the MD2–0 bits are reset to 000 to indicate the ADC is
back in power-down mode.
5. Any calibration request of the Auxiliary ADC while the temperature sensor is selected will fail to complete. Although the RDY1 bit will be set at the end of
the calibration cycle, no update of the calibration SFRs will take place and the ERR1 bit will be set.
6. Calibrations are performed at maximum SF (see SF SFR) value guaranteeing optimum calibration operation.
–26–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
ADC0CON (Primary ADC Control Register) and ADC1CON (Auxiliary ADC Control Register)
The ADC0CON and ADC1CON SFRs are used to configure the Primary and auxiliary ADC for reference and channel selection,
unipolar or bipolar coding and in the case of the primary ADC for range (the aux ADC operates on a fixed input range of ±VREF.),
ADC0CON
Primary ADC Control SFR
ADC1CON
Auxiliary ADC Control SFR
SFR Address
D2H
SFR Address
D3H
Power-On Default Value 07H
Power-On Default Value 00H
Bit Addressable
No
Bit Addressable
No
Table VI. ADC0CON SFR Bit Designations
Bit
Name
Description
7
6
--XREF0
5
4
CH1
CH0
3
UNI0
2
1
0
RN2
RN1
RN0
Reserved for Future Use.
Primary ADC External Reference Select Bit.
Set by user to enable the Primary ADC to use the external reference via REFIN(+)/REFIN(–).
Cleared by user to enable the Primary ADC to use the internal bandgap reference (VREF = 1.25 V).
Primary ADC Channel Selection Bits.
Written by the user to select the differential input pairs used by the Primary ADC as follows:
CH1
CH0
Positive Input Negative Input
0
0
AIN1
AIN2
0
1
AIN3
AIN4
1
0
AIN2
AIN2 (Internal Short)
1
1
AIN3
AIN2
Primary ADC Unipolar Bit.
Set by user to enable unipolar coding, i.e., zero differential input will result in 000000 hex output.
Cleared by user to enable bipolar coding, zero differential input will result in 800000 hex output.
Primary ADC Range Bits.
Written by the user to select the Primary ADC input range as follows:
RN2
RN1
RN0 Selected Primary ADC Input Range (VREF = 2.5 V)
0
0
0
±20 mV
(0-20mV in unipolar mode)
0
0
1
±40 mV
(0-40mV in unipolar mode)
0
1
0
±80 mV
(0-80mV in unipolar mode)
0
1
1
±160 mV
(0-160mV in unipolar mode)
1
0
0
±320 mV
(0-320mV in unipolar mode)
1
0
1
±640 mV
(0-640mV in unipolar mode)
1
1
0
±1.28 V
(0-1.28V in unipolar mode)
1
1
1
±2.56 V
(0-2.56V in unipolar mode)
Table VII. ADC1CON SFR Bit Designations
Bit
Name
Description
7
6
--XREF1
5
4
ACH1
ACH0
3
UNI1
2
1
0
-------
Reserved for Future Use.
Auxiliary ADC External Reference Bit.
Set by user to enable the Auxiliary ADC to use the external reference via REFIN(+)/REFIN(–).
Cleared by user to enable the Auxiliary ADC to use the internal bandgap reference.
Auxiliary ADC Channel Selection Bits.
Written by the user to select the single-ended input pins used to drive the Auxiliary ADC as follows:
ACH1
ACH0
Positive Input
Negative Input
0
0
AIN3
AGND
0
1
AIN4
AGND
1
0
Temp Sensor*
AGND (Temp. Sensor routed to the ADC input)
1
1
AIN5
AGND
Auxiliary ADC Unipolar Bit.
Set by user to enable unipolar coding, i.e., zero input will result in 0000 hex output.
Cleared by user to enable bipolar coding, zero input will result in 8000 hex output.
Reserved for Future Use.
Reserved for Future Use.
Reserved for Future Use.
*NOTES
1. When the temperature sensor is selected, user code must select internal reference via XREF1 bit above and clear the UNI1 bit (ADC1CON.3) to select bipolar coding.
2. The temperature sensor is factory calibrated to yield conversion results 8000H at 0°C.
3. A +1°C change in temperature will result in a +1 LSB change in the ADC1H register ADC conversion result.
REV. PrC (12 March 2002)
–27–
PRELIMINARY TECHNICAL DATA
ADuC834
ADC0H/ADC0M/ADC0L (Primary ADC Conversion Result Registers)
These three 8-bit registers hold the 24-bit conversion result from the Primary ADC.
SFR Address
Power-On Default Value
Bit Addressable
ADC0H
ADC0M
ADC0L
00H
No
High Data Byte
Middle Data Byte
Low Data Byte
Both registers
Both registers
DBH
DAH
D9H
ADC1H/ADC1L (Auxiliary ADC Conversion Result Registers)
These two 8-bit registers hold the 16-bit conversion result from the Auxiliary ADC.
SFR Address
Power-On Default Value
Bit Addressable
ADC1H
ADC1L
00H
No
High Data Byte
Low Data Byte
Both Registers
Both Registers
DDH
DCH
OF0H/OF0M/OF0L (Primary ADC Offset Calibration Registers1)
These three 8-bit registers hold the 24-bit offset calibration coefficient for the Primary ADC. These registers are configured at
power-on with a factory default value of 800000Hex. However, these bytes will be automatically overwritten if an internal or system
zero-scale calibration is initiated by the user via MD2–0 bits in the ADCMODE register.
SFR Address
Power-On Default Value
Bit Addressable
OF0H
OF0M
OF0L
800000H
No
Primary ADC Offset Coefficient High Byte
Primary ADC Offset Coefficient Middle Byte
Primary ADC Offset Coefficient Low Byte
OF0H and OF0M Respectively
Both Registers
E3H
E2H
E1H
OF1H/OF1L (Auxiliary ADC Offset Calibration Registers1)
These two 8-bit registers hold the 16-bit offset calibration coefficient for the Auxiliary ADC. These registers are configured at poweron with a factory default value of 8000Hex. However, these bytes will be automatically overwritten if an internal or system zero-scale
calibration is initiated by the user via the MD2–0 bits in the ADCMODE register.
SFR Address
Power-On Default Value
Bit Addressable
OF1H
OF1L
8000H
No
Auxiliary ADC Offset Coefficient High Byte
Auxiliary ADC Offset Coefficient Low Byte
OF1H and OF1L Respectively
Both Registers
E5H
E4H
GN0H/GN0M/GN0L (Primary ADC Gain Calibration Registers1)
These three 8-bit registers hold the 24-bit gain calibration coefficient for the Primary ADC. These registers are configured at
power-on with a factory-calculated internal full-scale calibration coefficient. Every device will have an individual coefficient. However, these bytes will be automatically overwritten if an internal or system full-scale calibration is initiated by the user via MD2–0
bits in the ADCMODE register.
SFR Address
Power-On Default Value
Bit Addressable
GN0H
GN0M
GN0L
No
Primary ADC Gain Coefficient High Byte
Primary ADC Gain Coefficient Middle Byte
Primary ADC Gain Coefficient Low Byte
Configured at factory final test, see notes above.
Both Registers
EBH
EAH
E9H
GN1H/GN1L (Auxiliary ADC Gain Calibration Registers1)
These two 8-bit registers hold the 16-bit gain calibration coefficient for the Auxiliary ADC. These registers are configured at poweron with a factory calculated internal full-scale calibration coefficient. Every device will have an individual coefficient. However,
these bytes will be automatically overwritten if an internal or system full-scale calibration is initiated by the user via MD2–0 bits in
the ADCMODE register.
SFR Address
Power-On Default Value
Bit Addressable
GN1H
GN1L
No
Auxiliary ADC Gain Coefficient High Byte
Auxiliary ADC Gain Coefficient Low Byte
Configured at factory final test, see notes above.
Both Registers
EDH
ECH
NOTE
1
These registers can be overwritten by user software only if Mode bits MD0–2 (ADCMODE SFR) are zero.
–28–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
SF (Sinc Filter Register)
fault ADC update rate of just under 20 Hz. Both ADC inputs
are chopped to minimize offset errors, which means that the
settling time for a single conversion or the time to a first conversion result in continuous conversion mode is 2 × tADC. As
mentioned earlier, all calibration cycles will be carried out
automatically with a maximum, i.e., FFhex, SF value to
ensure optimum calibration performance. Once a calibration
cycle has completed, the value in the SF register will be that
programmed by user software.
The number in this register sets the decimation factor and
thus the output update rate for the Primary and Auxiliary
ADCs. This SFR cannot be written by user software while either
ADC is active. The update rate applies to both Primary and
Auxiliary ADCs and is calculated as follows:
f ADC =
Where:
fADC =
fMOD =
SF =
1
3
×
1
8.SF
× f MOD
ADC Output Update Rate
Modulator Clock Frequency = 32.768 kHz
Decimal Value of SF Register
Table VIII. SF SFR Bit Designations
The allowable range for SF is 0Dhex to FFhex. Examples of SF
values and corresponding conversion update rate (fADC) and
conversion time (tADC) are shown in Table VIII, the power-on
default value for the SF register is 45 hex, resulting in a de-
SF(dec)
SF(hex)
fADC(Hz)
tADC(ms)
13
69
255
0D
45
FF
105.3
19.79
5.35
9.52
50.34
186.77
ICON (Current Sources Control Register)
Used to control and configure the various excitation and burnout current source options available on-chip.
SFR Address
Power-On Default Value
Bit Addressable
D5H
00H
No
Table IX. ICON SFR Bit Designations
Bit
Name
Description
7
6
--BO
5
ADC1IC
4
ADC0IC
3
I2PIN1
2
I1PIN1
1
I2EN
0
I1EN
Reserved for Future Use.
Burnout Current Enable Bit.
Set by user to enable both transducer burnout current sources in the primary ADC signal paths.
Cleared by user to disable both transducer burnout current sources.
Auxiliary ADC Current Correction Bit.
Set by user to allow scaling of the Auxiliary ADC by an internal current source calibration word.
Primary ADC Current Correction Bit.
Set by user to allow scaling of the Primary ADC by an internal current source calibration word.
Current Source-2 Pin Select Bit.
Set by user to enable current source-2 (200 µA) to external pin 3 (P1.2/DAC/IEXC1).
Cleared by user to enable current source-2 (200 µA) to external pin 4 (P1.3/AIN5/IEXC2).
Current Source-1 Pin Select Bit.
Set by user to enable current source-1 (200 µA) to external pin 4 (P1.3/AIN5/IEXC2).
Cleared by user to enable current source-1 (200 µA) to external pin 3 (P1.2/DAC/IEXC1).
Current Source-2 Enable Bit.
Set by user to turn on excitation current source-2 (200 µA).
Cleared by user to turn off excitation current source-2 (200 µA).
Current Source-1 Enable Bit.
Set by user to turn on excitation current source-1 (200 µA).
Cleared by user to turn off excitation current source-1 (200 µA).
NOTE
1
Both current sources can be enabled to the same external pin, yielding a 400 µA current source.
REV. PrC (12 March 2002)
–29–
PRELIMINARY TECHNICAL DATA
ADuC834
PRIMARY AND AUXILIARY ADC NOISE
PERFORMANCE
Tables X, XI and XII below show the output rms noise in µV
and output peak-to-peak resolution in bits (rounded to the
nearest 0.5 LSB) for some typical output update rates on both
the Primary and Auxiliary ADCs. The numbers are typical and
are generated at a differential input voltage of 0V. The output
update rate is selected via the Sinc Filter (SF) SFR. It is important to note that the peak-to-peak resolution figures represent
the resolution for which there will be no code flicker within a
six-sigma limit.
The QuickStart Development system PC software comes complete with an ADC noise evaluation tool. This tool can be
easily used with the evalustion board to see these figures from
silicon.
␮V)
Table X. Primary ADC, Typical Output RMS Noise (␮
Typical Output RMS Noise vs. Input Range and Update Rate; Output RMS Noise in ␮V
SF
Word
Data Update
Rate (Hz)
ⴞ20 mV
ⴞ40 mV
ⴞ80 mV
Input Range
ⴞ160 mV
ⴞ320 mV
ⴞ640 mV
±1.28 V
±2.56 V
13
69
255
105.3
19.79
5.35
1.50
0.60
0.35
1.50
0.65
0.35
1.60
0.65
0.37
1.75
0.65
0.37
3.50
0.65
0.37
4.50
0.95
0.51
6.70
1.40
0.82
11.75
2.30
1.25
Table XI. Primary ADC, Peak-to-Peak Resolution (Bits)
Peak-to-Peak Resolution vs. Input Range and Update Rate; Peak-to-Peak Resolution in Bits
SF
Word
Data Update
Rate (Hz)
ⴞ20 mV
ⴞ40 mV
ⴞ80 mV
Input Range
ⴞ160 mV
ⴞ320 mV
ⴞ640 mV
ⴞ1.28 V
ⴞ2.56 V
13
69
255
105.3
19.79
5.35
12
13
14
13
14
15
14
15
16
15
16
17
15
17
18
15.5
17.5
18.5
16
18
18.8
16
18.5
19.2
Table XII. Auxiliary ADC
Typical Output RMS Noise vs. Update Rate1
Output RMS Noise in ␮V
SF
Peak-to-Peak Resolution vs. Update Rate1
Peak-to-Peak Resolution in Bits
Data Update
Rate (Hz)
Input Range
Word
2.5 V
SF
Word
Data Update
Rate (Hz)
Input Range
2.5 V
13
69
255
105.3
19.79
5.35
10.75
2.00
1.15
13
69
255
105.3
19.79
5.35
162
16
16
NOTE
1
ADC converting in bipolar mode.
NOTES
1
ADC converting in bipolar mode.
2
In unipolar mode peak-to-peak resolution at 105 Hz is 15 bits.
–30–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
PRIMARY AND AUXILIARY ADC CIRCUIT DESCRIPTION
Overview
The ADuC834 incorporates two independent sigma-delta ADCs
(Primary and Auxiliary) with on-chip digital filtering intended
for the measurement of wide dynamic range, low frequency
signals such as those in weigh-scale, strain-gauge, pressure transducer or temperature measurement applications.
Primary ADC
This ADC is intended to convert the primary sensor input. The
input is buffered and can be programmed for one of 8 input
ranges from ±20 mV to ±2.56 V being driven from one of three
differential input channel options AIN1/2, AIN3/4, or AIN3/2.
The input channel is internally buffered allowing the part to
handle significant source impedances on the analog input,
allowing R/C filtering (for noise rejection or RFI reduction) to
be placed on the analog inputs if required. On-chip burnout
currents can also be turned on. These currents can be used to
check that a transducer on the selected channel is still operational
before attempting to take measurements.
The ADC employs a sigma-delta conversion technique to realize up to 24 bits of no missing codes performance. The
sigma-delta modulator converts the sampled input signal into a
digital pulse train whose duty cycle contains the digital information. A Sinc3 programmable low-pass filter is then employed
to decimate the modulator output data stream to give a valid
data conversion result at programmable output rates from
5.35 Hz (186.77 ms) to 105.03 Hz (9.52 ms). A Chopping
scheme is also employed to minimize ADC offset errors. A
block diagram of the Primary ADC is shown in Figure 17.
D IF FE R E N T I A L
RE FE RE N C E
P R O G R A M M A B LE G A IN
A M P LI F IE R
A N A L O G IN P U T C H O P P IN G
BU RNO U T C U R RE N TS
TW O 1 00 nA B U RN O U T
CUR RE NT S A L LO W TH E
US E R TO E A S ILY DE TE CT
IF A TR A N S D UC E R H A S
B UR NE D O UT O R G O N E
O P E N -C IR CU IT
TH E IN P U TS A R E
A L TE R N A T E L Y R E V E R S E D
TH R O U G H TH E
C O N V E R S IO N C Y C LE .
C H O P P IN G Y IE L D S
E X C E LL E N T A D C O F F S E T
A N D O F FS E T D R IF T
PE RFO R M A NCE
S EE P A G E 36
TH E P R O G R A M M A B LE
G A IN A M P L IF IE R A LL O W S
E IG H T U N IP O LA R A N D
E IG H T B IP O L A R IN P U T
R A N G E S FR O M 20 m V T O
2.5 6V (E X T V R E F = + 2. 5V )
S EE P A G E 33
TH E E X TE R N A L R E FE R E N C E
IN P U T T O TH E A D uC 8 34 I S
D IFF E R E N T IA L A N D
FA C ILI TA TE S R A TI O M E TR IC
O P E R A TI O N . TH E E X TE R N A L
R E F E R E N C E V O L TA G E IS S E L E C TE D V I A TH E X R E F0 B IT
IN A D C 0 C O N .
R E FE R E N C E D E T E C T
C IR C U IT R Y TE S TS FO R O P E N O R
S H O R T E D R E F E R E N C E S IN P U TS
S EE P A G E 34
S IG M A -D E L TA A D C
O U TP U T A V E R A G E
TH E S IG M A -D E LT A
A R C H IT E C TU R E E N S U R E S
24 B IT S N O M IS S IN G
C O D E S . T H E E N TIR E S IG M A D E LT A A D C IS
C H O P PE D TO R E M O V E
D R IF T E R R O R
S EE P A G E 35
A S P A R T O F T H E C H O P P IN G
IM P L E M E N TA TI O N , E A C H
D A TA W O R D O U TP U T
FR O M TH E FI LT E R I S
S U M M E D A N D A V E R A G E D W ITH
ITS P R E D E C E S SO R
TO N U L L A D C C H A N N E L
O FF S E T E R R O R S
S EE P A G E 35
S EE P A G E 29 A ND 3 4
R E F IN ( -) R E F IN (+)
A V DD
DIG TAL O UTPUT
R E S U LT W R IT TE N
TO A D C 0H /M /L S FR s
S IG M A -D E LT A A /D C O N V E R T E R
A IN1
B U F FE R
A IN2
MUX
PGA
SIGM A DE LTA
M O D U LA T O R
P R O G R A M M A B LE
D IG IT A L
FI L T E R
O U TP UT
AV E RA G E
O U TP UT
S C A LI N G
A IN3
CH O P
A IN4
CH O P
AG N D
O U TP U T S C A L IN G
A N A L O G M U L T IP L E X E R
A D I FF E R E N TI A L M U LT IP LE X E R
A LL O W S S E LE C TI O N O F T H R E E
FU L LY D IF FE R E N T IA L P A IR O P T IO N S A N D
A D D IT IO N A L IN TE R N A L S H O R T O P TI O N
(A I N 2 ›A IN 2).T H E M U L TI P L E X E R IS
C O N T R O LL E D V IA T H E C H A N N E L
S EL E C TI O N B IT S IN A D C 0 C O N
S EE P A G E S 2 7 A N D 3 3
B U F FE R A M P L IF IE R
TH E B U FF E R A M P L IF IE R
P R E S E N T S A H IG H
IM P E D A N C E IN P U T S TA G E
FO R T H E A N A LO G IN P U T S ,
A LL O W IN G S IG N I FI C A N T
E X TE R N A L S O U R C E
IM P E D A N C E S
S EE P A G E 33
P R O G R A M M A B LE
D IG I T A L FI L TE R
S IG M A -D E L TA
M O D U LA T O R
TH E M O D U L A T O R P R O V ID E S
A H I G H -F R E Q U E N C Y 1-B I T
D A TA S TR E A M (T H E O U T P U T O F
W H I C H IS A LS O C H O P P E D ) TO
TH E D IG IT A L F IL TE R ,
TH E D U T Y C Y C L E O F W H I C H
R E P R E S E N TS T H E S A M P LE D
A N A LO G IN P U T V O L TA G E
S EE P A G E 34
TH E S IN C 3 F ILT E R R E M O V E S
Q U A N T IZ A T IO N N O IS E IN T R O D U C E D
B Y T H E M O D U L A T O R . TH E U P D A TE
R A TE A N D B A N D W ID TH O F T H IS
FI LT E R A R E P R O G R A M M A B L E
V IA T H E S F S F R
Figure 17. Primary ADC Block Diagram
REV. PrC (12 March 2002)
–31–
S EE P A G E 35
TH E O U P U T W O R D F R O M TH E
D IG IT A L F IL TE R IS S C A L E D B Y
TH E C A LI B R A TI O N
C O E FF IC IE N T S B E FO R E
B E I N G P R O V ID E D A S
TH E C O N V E R S IO N R E S U L T
S EE P A G E 36
PRELIMINARY TECHNICAL DATA
ADuC834
Auxiliary ADC
The Auxiliary ADC is intended to convert supplementary inputs
such as those from a cold junction diode or thermistor. This ADC is
not buffered and has a fixed input range of 0 V to 2.5 V (assuming an external 2.5 V reference). The single-ended inputs can be
driven from AIN3, AIN4 or AIN5 pins or directly from the on-chip
temperature sensor voltage. A block diagram of the Auxiliary ADC
is shown in Figure 18.
DIFFERENTIAL REFERENCE
ANALOG INPUT CHOPPING
THE INPUTS ARE ALTERNATELY
REVERSED THROUGH THE
CONVERSION CYCLE. CHOPPING
YIELDS EXCELLENT ADC
OFFSET AND OFFSET DRIFT
PERFORMANCE
THE EXTERNAL REFERENCE INPUT
TO THE ADuC834 IS DIFFERENTIAL AND
FACILITATES RATIOMETRIC
OPERATION. THE EXTERNAL
REFERENCE VOLTAGE IS SELECTED
VIA THE XREF1 BIT IN ADC1CON.
REFERENCE DETECT
CIRCUITRY TESTS FOR OPEN OR
SHORTED REFERENCES INPUTS
SEE PAGE 35
SIGMA-DELTA ADC
OUTPUT AVERAGE
THE SIGMA-DELTA
ARCHITECTURE ENSURES
16 BITS NO MISSING
CODES. THE ENTIRE
SIGMA-DELTA ADC IS
CHOPPED TO REMOVE DRIFT
ERRORS
SEE PAGE 35
AS PART OF THE CHOPPING
IMPLEMENTATION EACH
DATA WORD OUTPUT
FROM THE FILTER IS
SUMMED AND AVERAGED
WITH ITS PREDECESSOR
TO NULL ADC CHANNEL
OFFSET ERRORS
SEE PAGE 35
SEE PAGE 36
R E F IN (› )
R E F IN (+)
S IG M A -D E LT A A /D C O N V E R T E R
A IN 3
S IG M A DE LTA
M O D U LA T O R
A IN 4
MU
X
M
UX
P R O G R A M M A B LE
D I G IT A L
FI L T E R
O U TP UT
AV E RA G E
O U TP UT
S C A LI N G
D I G TA L O U TP U T
R E S U L T W R IT T E N
TO A D C 1 H /L S FR s
A IN 5
O N -C H IP
TE M P E R A T U R E
SE NS O R
CH O P
CH O
P
OUTPUT SCALING
ANALOG MULTIPLEXER
A DIFFERENTIAL MULTIPLEXER
ALLOWS SELECTION OF THREE
EXTERNAL SINGLE ENDED INPUTS OR
THE ON-CHIP TEMP. SENSOR.
THE MULTIPLEXER IS CONTROLLED
VIA THE CHANNEL SELECTION
BITS IN ADC1CON
SEE PAGE 28 AND 33
PROGRAMMABLE DIGITAL
FILTER
SIGMA DELTA
MODULATOR
THE MODULATOR PROVIDES A
HIGH FREQUENCY 1-BIT DATA
STREAM (THE OUTPUT OF WHICH
IS ALSO CHOPPED) TO THE
DIGITAL FILTER,
THE DUTY CYCLE OF WHICH
REPRESENTS THE SAMPLED
ANALOG INPUT VOLTAGE
SEE PAGE 34
THE SINC3 FILTER REMOVES
QUANTIZATION NOISE INTRODUCED
BY THE MODULATOR. THE UPDATE RATE
AND BANDWIDTH OF THIS
FILTER ARE PROGRAMMABLE
VIA THE SF SFR
SEE PAGE 35
THE OUPUT WORD FROM THE
DIGITAL FILTER IS SCALED BY
THE CALIBRATION
COEFFICIENTS BEFORE
BEING PROVIDED AS
THE CONVERSION RESULT
SEE PAGE 36
Figure 18. Auxiliary ADC Block Diagram
–32–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
The auxiliary ADC does not incorporate a PGA and is configured for a fixed single input range of 0 to VREF.
19.372
Primary and Auxiliary ADC Inputs
19.371
A DC INP UT V O LTA GE › mV
The output of the primary ADC multiplexer feeds into a
high impedance input stage of the buffer amplifier. As a
result, the primary ADC inputs can handle significant source
impedances and are tailored for direct connection to external
resistive-type sensors like strain gauges or Resistance Temperature Detectors (RTDs).
The auxiliary ADC, however, is unbuffered resulting in higher
analog input current on the auxiliary ADC. It should be noted
that this unbuffered input path provides a dynamic load to the
driving source. Therefore, resistor/capacitor combinations on
the input pins can cause dc gain errors depending on the output
impedance of the source that is driving the ADC inputs.
The absolute input voltage range on the auxiliary ADC is restricted to between AGND – 30 mV to AVDD + 30 mV. The
slightly negative absolute input voltage limit does allow the
possibility of monitoring small signal bipolar signals using the
single-ended auxiliary ADC front end.
Programmable Gain Amplifier
The output from the buffer on the primary ADC is applied to
the input of the on-chip programmable gain amplifier (PGA).
The PGA can be programmed through eight different unipolar
input ranges and bipolar ranges. The PGA gain range is programmed via the range bits in the ADC0CON SFR. With the
external reference select bit set in the ADC0CON SFR and an
external 2.5V reference, the unipolar ranges are 0 mV to
+20 mV, 0 mV to 40 mV, 0 mV to 80 mV, 0 mV to 160 mV,
0 mV to 320 mV, 0 mV to 640 mV and 0 V to 1.28 V and 0
to 2.56 V while the bipolar ranges are ±20 mV, ±40 mV,
±80 mV, ±160 mV, ±320 mV, ±640 mV, ±1.28 V and
±2.56 V. These are the nominal ranges that should appear at the
input to the on-chip PGA. An ADC range matching specification of 0.5 LSB (typ) across all ranges means that calibration
REV. PrC (12 March 2002)
19.369
19.368
19.367
19.366
19.365
19.364
300
400
500
600
700
800
ⴞ2.56V
200
ⴞ1.28V
100
ⴞ640V
A DC RA NG E
ⴞ320mV
SAMPLE CO UNT 0
Analog Input Ranges
The absolute input voltage range on the primary ADC is restricted to between AGND + 100 mV to AVDD –100 mV. Care
must be taken in setting up the common-mode voltage and
input voltage range so that these limits are not exceeded, otherwise there will be a degradation in linearity performance.
19.370
ⴞ160mV
Two input multiplexers switch the selected input channel to
the on-chip buffer amplifier in the case of the primary ADC
and directly to the sigma-delta modulator input in the case
of the auxiliary ADC. When the analog input channel is
switched, the settling time of the part must elapse before a new
valid word is available from the ADC.
Typical matching across ranges is shown in Figure 19 below.
Here, the primary ADC is configured in bipolar mode with an
external 2.5 V reference, while just greater than 19 mV is
forced on its inputs. The ADC continuously converts the DC
input voltage at an update rate of 5.35 Hz, i.e., SF = FFhex. In
total, 800 conversion results are gathered. The first 100 results are gathered with the primary ADC operating in the
±20 mV range. The ADC range is then switched to ±40 mV and
100 more conversion results are gathered, and so on until the
last group of 100 samples are gathered with the ADC configured
in the ±2.56 V range. From Figure 19, The variation in the
sample mean through each range, i.e., the range matching, is
seen to be of the order of 2 µV.
ⴞ80m V
The auxiliary ADC has three external input pins (labelled
AIN3 to AIN5) as well as an internal connection to the internal
on-chip temperature sensor. All inputs to the auxiliary ADC
are single-ended inputs referenced to the AGND on the part.
Channel selection bits in the ADC1CON SFR detailed previously in Table VII allow selection of one of four inputs.
need only be carried out at a single gain range and does not
have to be repeated when the PGA gain range is changed.
ⴞ40m V
The primary ADC has four associated analog input pins (labelled AIN1 to AIN4) which can be configured as two fully
differential input channels. Channel selection bits in the
ADC0CON SFR detailed in Table VI allow three combinations of differential pair selection as well as an additional shorted
input option (AIN2–AIN2).
ⴞ20m V
Analog Input Channels
Figure 19. Primary ADC Range Matching
Bipolar/Unipolar Inputs
The analog inputs on the ADuC834 can accept either unipolar or bipolar input voltage ranges. Bipolar input ranges
do not imply that the part can handle negative voltages with
respect to system AGND.
Unipolar and bipolar signals on the AIN(+) input on the primary ADC are referenced to the voltage on the respective AIN(–)
input. For example, if AIN(–) is 2.5 V and the primary ADC is
configured for an analog input range of 0 mV to +20 mV,
the input voltage range on the AIN(+) input is 2.5 V to
2.52 V. If AIN(–) is 2.5 V and the ADuC834 is configured for an
analog input range of 1.28 V, the analog input range on the
AIN(+) input is 1.22 V to 3.78 V (i.e., 2.5 V ± 1.28 V).
As mentioned earlier, the auxiliary ADC input is a singleended input with respect to the system AGND. In this context a
bipolar signal on the auxiliary ADC can only span 30 mV
negative with respect to AGND before violating the voltage
input limits for this ADC.
Bipolar or unipolar options are chosen by programming the
Primary and Auxiliary Unipolar enable bits in the ADC0CON
and ADC1CON SFRs respectively. This programs the relevant
ADC for either unipolar or bipolar operation. Programming for
either unipolar or bipolar operation does not change any of the
–33–
PRELIMINARY TECHNICAL DATA
ADuC834
input signal conditioning; it simply changes the data output coding and the points on the transfer function where calibrations
occur. When an ADC is configured for unipolar operation,
the output coding is natural (straight) binary with a zero
differential input voltage resulting in a code of 000 . . . 000, a
midscale voltage resulting in a code of 100 . . . 000, and a fullscale input voltage resulting in a code of 111 . . . 111. When an
ADC is configured for bipolar operation, the coding is offset
binary with a negative full-scale voltage resulting in a code of
000 . . . 000, a zero differential voltage resulting in a code of
100 . . . 000, and a positive full-scale voltage resulting in a code
of 111 . . . 111.
Reference Input
The ADuC834’s reference inputs, REFIN(+) and REFIN(–),
provide a differential reference input capability. The common-mode range for these differential inputs is from AGND to
AVDD. The nominal reference voltage, VREF (REFIN(+) –
REFIN(–)), for specified operation is 2.5 V with the primary and auxiliary reference enable bits set in the
respective ADC0CON and/or ADC1CON SFRs.
The part is also functional (although not specified for performance) when the XREF0 or XREF1 bits are ‘0,’ which
enables the on-chip internal bandgap reference. In this mode,
the ADCs will see the internal reference of 1.25 V, therefore
halving all input ranges. As a result of using the internal
reference voltage, a noticeable degradation in peak-to-peak
resolution will result. Therefore, for best performance, operation with an external reference is strongly recommended.
In applications where the excitation (voltage or current) for the
transducer on the analog input also drives the reference voltage
for the part, the effect of the low-frequency noise in the excitation source will be removed as the application is ratiometric. If
the ADuC834 is not used in a ratiometric application, a low
noise reference should be used. Recommended reference voltage
sources for the ADuC834 include the AD780, REF43, and
REF192.
flow in the external transducer circuit, and a measurement of
the input voltage on the analog input channel can be taken. If
the resultant voltage measured is full-scale, this indicates that
the transducer has gone open-circuit. If the voltage measured is
0 V, it indicates that the transducer has short circuited. For
normal operation, these burnout currents are turned off by
writing a 0 to the BO bit in the ICON SFR. The current
sources work over the normal absolute input voltage range specifications.
Excitation Currents
The ADuC834 also contains two identical, 200 µA constant
current sources. Both source current from AVDD to Pin
#3 (IEXC1) or Pin #4 (IEXC2) These current sources are
controlled via bits in the ICON SFR shown in Table IX. They
can be configured to source 200 µA individually to both pins
or a combination of both currents, i.e., 400 µA to either of
the selected pins. These current sources can be used to excite
external resistive bridge or RTD sensors.
Reference Detect
The ADuC834 includes on-chip circuitry to detect if the part has
a valid reference for conversions or calibrations. If the
voltage between the external REFIN(+) and REFIN(–) pins
goes below 0.3 V or either the REFIN(+) or REFIN(–) inputs is
open circuit, the ADuC834 detects that it no longer has a
valid reference. In this case, the NOXREF bit of the
ADCSTAT SFR is set to a 1. If the ADuC834 is performing
normal conversions and the NOXREF bit becomes active, the
conversion results revert to all 1s. Therefore, it is not necessary
to continuously monitor the status of the NOXREF bit when
performing conversions. It is only necessary to verify its status if
the conversion result read from the ADC Data Register is all 1s.
If the ADuC834 is performing either an offset or gain calibration and the NOXREF bit becomes active, the updating of the
respective calibration registers is inhibited to avoid loading
incorrect coefficients to these registers, and the appropriate
ERR0 or ERR1 bits in the ADCSTAT SFR are set. If the
user is concerned about verifying that a valid reference is in
place every time a calibration is performed, the status of the
ERR0 or ERR1 bit should be checked at the end of the calibration cycle.
It should also be noted that the reference inputs provide a
high impedance, dynamic load. Because the input impedance
of each reference input is dynamic, resistor/capacitor combinations on these inputs can cause dc gain errors depending
on the output impedance of the source that is driving the
reference inputs. Reference voltage sources, like those recommended above (e.g., AD780) will typically have low output
impedances and therefore decoupling capacitors on the
REFIN(+) input would be recommended. Deriving the reference input voltage across an external resistor, as shown in
Figure 60, will mean that the reference input sees a significant external source impedance. External decoupling on the
REFIN(+) and REFIN(-) pins would not be recommended
in this type of circuit configuration.
Sigma-Delta Modulator
A sigma-delta ADC generally consists of two main blocks,
an analog modulator and a digital filter. In the case of the
ADuC834 ADCs, the analog modulators consist of a difference amplifier, an integrator block, a comparator, and a
feedback DAC as illustrated in Figure 20.
A NA LOG
INPUT
DIFFE RE NCE
AMP
CO M P ARA TO R
INTE G RA TOR
Burnout Currents
The primary ADC on the ADuC834 contains two 100 nA
constant current generators, one sourcing current from
AVDD to AIN(+), and one sinking from AIN(–) to AGND.
The currents are switched to the selected analog input pair. Both
currents are either on or off, depending on the Burnout Current Enable (BO) bit in the ICON SFR (see Table IX). These
currents can be used to verify that an external transducer is still
operational before attempting to take measurements on that
channel. Once the burnout currents are turned on, they will
HIGHFRE Q UE NCY
B ITS TRE AM
TO DIGITA L
FILTE R
DA C
Figure 20. Sigma-Delta Modulator Simplified Block Diagram
In operation, the analog signal sample is fed to the difference amplifier along with the output of the feedback DAC. The
difference between these two signals is integrated and fed
to the comparator. The output of the comparator provides the
input to the feedback DAC so the system functions as a negative
feedback loop that tries to minimize the difference signal. The
–34–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
The response of the filter, however, will change with SF word
as can be seen in Figure 22, which shows >90 dB NMR at
50 Hz and >70 dB NMR at 60 Hz when SF = 255 dec.
0
›10
›20
›30
›40
Digital Filter
The output of the sigma-delta modulator feeds directly into the
digital filter. The digital filter then band-limits the response to
a frequency significantly lower than one-half of the modulator frequency. In this manner, the 1-bit output of the
comparator is translated into a band-limited, low noise
output from the ADuC834 ADCs.
The ADuC834 filter is a low-pass, Sinc3 or (sinx/x)3 filter
whose primary function is to remove the quantization noise
introduced at the modulator. The cutoff frequency and decimated output data rate of the filter are programmable via the
SF (Sinc Filter) SFR as described in Table VIII.
›50
G AIN › dB
digital data that represents the analog input voltage is contained in the duty cycle of the pulse train appearing at the
output of the comparator. This duty cycle data can be recovered as a data word using a subsequent digital filter stage.
The sampling frequency of the modulator loop is many
times higher than the bandwidth of the input signal. The
integrator in the modulator shapes the quantization noise
(which results from the analog-to-digital conversion) so that
the noise is pushed toward one-half of the modulator frequency.
›60
›70
›80
›90
›10 0
›11 0
›12 0
0
10
20
30
40
50
60
70
80
90
110
FRE Q UE NCY › Hz
Figure 22. Filter Response, SF = 255 dec
Figures 23 and 24 show the NMR for 50 Hz and 60 Hz across
the full range of SF word, i.e., SF = 13 dec to SF = 255 dec.
Figure 21 shows the frequency response of the ADC
channel at the default SF word of 69 dec or 45 hex, yielding
an overall output update rate of just under 20 Hz.
0
›10
›20
It should be noted that this frequency response allows frequency components higher than the ADC Nyquist frequency
to pass through the ADC, in some cases without significant
attenuation. These components may, therefore, be aliased and
appear in-band after the sampling process.
›30
G A IN › dB
›40
It should also be noted that rejection of mains-related frequency components, i.e., 50 Hz and 60 Hz, is seen to be at
level of >65 dB at 50 Hz and >100 dB at 60 Hz. This confirms the data sheet specifications for 50 Hz/60 Hz Normal
Mode Rejection (NMR) at a 20 Hz update rate.
›50
›60
›70
›80
›90
›10 0
›11 0
›12 0
10
30
50
70
90
0
130
150
170 190
210
230 250
S F › Decim al
›10
Figure 23. 50 Hz Normal Mode Rejection vs. SF
›20
›30
0
›40
›10
›50
›20
›60
›30
›70
›40
›80
›50
G AIN › dB
G AIN › dB
110
›90
›10 0
›11 0
›60
›70
›80
›12 0
0
10
20
30
40
50
60
70
80
90
100
›90
110
FRE QUE NCY › Hz
›100
›110
Figure 21. Filter Response, SF = 69 dec
›120
10
30
50
70
90
110
130
150
170
190
210
230
250
S F › Decim al
Figure 24. 60 Hz Normal Mode Rejection vs. SF
REV. PrC (12 March 2002)
–35–
PRELIMINARY TECHNICAL DATA
ADuC834
ADC Chopping
Both ADCs on the ADuC834 implement a chopping scheme
whereby the ADC repeatability reverses its inputs. The decimated digital output words from the Sinc3 filters therefore have a
positive offset and negative offset term included.
As a result, a final summing stage is included in each ADC so that
each output word from the filter is summed and averaged with the
previous filter output to produce a new valid output result to
be written to the ADC data SFRs. In this way, while the
ADC throughput or update rate is as discussed earlier and
illustrated in Table VIII, the full settling time through the ADC
(or the time to a first conversion result), will actually be given
by 2 × tADC.
The chopping scheme incorporated in the ADuC834 ADC results in excellent dc offset and offset drift specifications and
is extremely beneficial in applications where drift, noise rejection, and optimum EMI rejection are important factors.
Calibration
The ADuC834 provides four calibration modes that can be
programmed via the mode bits in the ADCMODE SFR detailed in Table V. In fact, every ADuC834 has already been
factory calibrated. The resultant Offset and Gain calibration
coefficients for both the primary and auxiliary ADCs are
stored on-chip in manufacturing-specific Flash/EE memory
locations. At power-on, these factory calibration coefficients
are automatically downloaded to the calibration registers in
the ADuC834 SFR space. Each ADC (primary and auxiliary)
has dedicated calibration SFRs, these have been described earlier
as part of the general ADC SFR description. However, the
factory calibration values in the ADC calibration SFRs will be
overwritten if any one of the four calibration options are initiated
and that ADC is enabled via the ADC enable bits in
ADCMODE.
Even though an internal offset calibration mode is described
below, it should be recognized that both ADCs are chopped. This
chopping scheme inherently minimizes offset and means that
an internal offset calibration should never be required. Also, because factory 5 V/25°C gain calibration coefficients are
automatically present at power-on, an internal full-scale cali-
bration will only be required if the part is being operated at 3 V or
at temperatures significantly different from 25°C.
The ADuC834 offers “internal” or “system” calibration facilities. For full calibration to occur on the selected ADC, the
calibration logic must record the modulator output for two
different input conditions. These are “zero-scale” and “fullscale” points. These points are derived by performing a
conversion on the different input voltages provided to the
input of the modulator during calibration. The result of the
“zero-scale” calibration conversion is stored in the Offset
Calibration Registers for the appropriate ADC. The result of
the “full-scale” calibration conversion is stored in the Gain
Calibration Registers for the appropriate ADC. With these
readings, the calibration logic can calculate the offset and the
gain slope for the input-to-output transfer function of the
converter.
During an “internal” zero-scale or full-scale calibration, the respective “zero” input and “full-scale” input are automatically
connected to the ADC input pins internally to the device. A
“system” calibration, however, expects the system zero-scale and
system full-scale voltages to be applied to the external ADC
pins before the calibration mode is initiated. In this way external
ADC errors are taken into account and minimized as a result of
system calibration. It should also be noted that to optimize
calibration accuracy, all ADuC834 ADC calibrations are carried out automatically at the slowest update rate.
Internally in the ADuC834, the coefficients are normalized before
being used to scale the words coming out of the digital filter. The
offset calibration coefficient is subtracted from the result prior to
the multiplication by the gain coefficient. All ADuC834 ADC
specifications will only apply after a zero-scale and full-scale
calibration at the operating point (supply voltage/temperature)
of interest.
From an operational point of view, a calibration should be treated
like another ADC conversion. A zero-scale calibration (if required) should always be carried out before a full-scale calibration.
System software should monitor the relevant ADC RDY0/1
bit in the ADCSTAT SFR to determine end of calibration
via a polling sequence or interrupt driven routine.
–36–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
NONVOLATILE FLASH/EE MEMORY
Flash/EE Memory Overview
The ADuC834 incorporates Flash/EE memory technology onchip to provide the user with nonvolatile, in-circuit
reprogrammable, code and data memory space.
Flash/EE memory is a relatively recent type of nonvolatile
memory technology and is based on a single transistor cell
architecture.
This technology is basically an outgrowth of EPROM technology
and was developed through the late 1980s. Flash/EE memory
takes the flexible in-circuit reprogrammable features of
EEPROM and combines them with the space efficient/density
features of EPROM (see Figure 25).
Because Flash/EE technology is based on a single transistor cell
architecture, a Flash memory array, like EPROM, can be
implemented to achieve the space efficiencies or memory
densities required by a given design.
Like EEPROM, Flash memory can be programmed in-system
at a byte level, although it must first be erased; the erase being
performed in page blocks. Thus, Flash memory is often and
more correctly referred to as Flash/EE memory.
E P RO M
T E CHN O L O G Y
E E P RO M
T E CHN O L O G Y
S P AC E E F F ICIENT /
DE N S ITY
IN-C IRCU I T
RE P R O G RAM M ABL E
F LA S H/E E M EM O RY
T E CHN O L O G Y
Figure 25. Flash/EE Memory Development
Endurance quantifies the ability of the Flash/EE memory to
be cycled through many Program, Read, and Erase cycles. In
real terms, a single endurance cycle is composed of four independent, sequential events. These events are defined as:
a. initial page erase sequence
b. read/verify sequence
c. byte program sequence
d. second read/verify sequence
In reliability qualification, every byte in both the program
and data Flash/EE memory is cycled from 00 hex to FFhex
until a first fail is recorded signifying the endurance limit of the
on-chip Flash/EE memory.
As indicated in the specification pages of this data sheet,
the ADuC834 Flash/EE Memory Endurance qualification has
been carried out in accordance with JEDEC Specification
A117 over the industrial temperature range of –40°C, +25°C,
and +85°C. The results allow the specification of a minimum
endurance figure over supply and temperature of 100,000 cycles,
with an endurance figure of 700,000 cycles being typical of
operation at 25°C.
Retention quantifies the ability of the Flash/EE memory to
retain its programmed data over time. Again, the ADuC834
has been qualified in accordance with the formal JEDEC Retention Lifetime Specification (A117) at a specific junction
temperature (TJ = 55°C). As part of this qualification procedure, the Flash/EE memory is cycled to its specified endurance
limit described above, before data retention is characterized.
This means that the Flash/EE memory is guaranteed to retain
its data for its full specified retention lifetime every time the
Flash/EE memory is reprogrammed. It should also be noted
that retention lifetime, based on an activation energy of
0.6 eV, will derate with TJ as shown in Figure 26.
Overall, Flash/EE memory represents a step closer to the ideal
memory device that includes nonvolatility, in-circuit programmability, high density and low cost. Incorporated in the
ADuC834, Flash/EE memory technology allows the user to
update program code space in-circuit, without the need to
replace one-time programmable (OTP) devices at remote
operating nodes.
300
250
200
A DI S P EC IF IC A TIO N
100 Y E AR S M IN .
A T T J = 55 ⴗC
RE T E N T
150
Flash/EE Memory and the ADuC834
The ADuC834 provides two arrays of Flash/EE memory for user
applications. 62kBytes of Flash/EE Program space are provided on-chip to facilitate code execution without any external
discrete ROM device requirements. The program memory can
be programmed in-circuit, using the serial download mode
provided, using conventional third party memory programmers
or via a user defined protocol who can configure it as data if
required.
A 4kByte Flash/EE Data Memory space is also provided on-chip.
This may be used as a general-purpose nonvolatile scratchpad
area. User access to this area is via a group of six SFRs. This space
can be programmed at a byte level, although it must first be
erased in 4-byte pages.
100
50
0
40
50
60
70
80
90
100
110
T J JU NC TIO N TE M P E RA TURE › ⴗC
Figure 26. Flash/EE Memory Data Retention
ADuC834 Flash/EE Memory Reliability
The Flash/EE Program and Data Memory arrays on the
ADuC834 are fully qualified for two key Flash/EE memory
characteristics, namely Flash/EE Memory Cycling
Endurance and Flash/EE Memory Data Retention.
REV. PrC (12 March 2002)
A single Flash/EE
Memory
Endurance Cycle
–37–
PRELIMINARY TECHNICAL DATA
ADuC834
USING THE FLASH/EE PROGRAM MEMORY
(3) User Download Mode (ULOAD)
The 62kByte Flash/EE Program Memory array is mapped
into the lower 62kBytes of the 64 Kbytes program space
addressable by the ADuC834, and is used to hold user code
in typical applications.
As shown in figure 28 the 62kBytes of user program memory
is split into two seperate blocks. The upper 6kBytes of the
program memory (E000h to F7FFh) is only programmable
via serial download or parallel programming. The lower
56kBytes (0000h to DFFFh) is also programmable by a
third method, user download (ULOAD) mode.
The program memory Flash/EE memory arrays can be programmed in three ways, namely:
Programming the flash/EE program memory via is described in more detail in the description of ECON and
also in technote uC0XX.
(1) Serial Downloading (In-Circuit Programming)
The ADuC834 facilitates code download via the standard
UART serial port. The ADuC834 will enter serial download
mode after a reset or power cycle if the PSEN pin is pulled low
through an external 1kΩ resistor. Once in serial download
mode, the user can download code to the full 62kBytes of flash/
EE program memory while the device is in circuit in its target
application hardware.
A PC serial download executable is provided as part of the
ADuC834 QuickStart development system. The Serial Download protocol is detailed in a MicroConverter Applications
Note uC004.
KE R NE L P RO G RA M
THE K E RNE L P RO G RA M CA N DOW NLOA D CODE TO THE FULL 62 K B Y TE S O F
FLASH/EE PROG RA M M E MO RY .
FF F F H
2 K BYTE
F8 00 H
F7 F F H
US E R BO O T L O A DE R S P A CE .
THE USE R B OO TLO ADE R CA N B E P ROG RA M ME D VIA THE KE RNE L PROGRA M
O R P A RA LLE L P RO GRAM M ING B UT IS
RE A DONLY TO US E R CODE
6 K BYTE
E 0 00 H
DF F F H
62 K B Y TES
O F US E R
CO DE
US E R DO W NL O AD S P AC E
E ITHE R THE KE RNE L P ROG RA M O R
US E R CO DE (IN ULO A D M O DE ) CA N
W RITE TO THIS S P A CE .
56 K B Y TE
(2) Parallel Programming
The parallel programming mode is fully compatible with conventional third party Flash or EEPROM device programmers. A
block diagram of the external pin configuration required to support parallel programming is shown in Figure 27. In this mode,
Ports 0, 1, and 2 operate as the external data and address bus
interface, ALE operates as the Write Enable strobe, and Port 3 is
used as a general configuration port that configures the device for
various program and erase operations during parallel programming.
Table XIII. Flash/EE Memory Parallel Programming Modes
Port 3 Pins
Programming
0.7 0.6 0.5 0.4 0.3 0.2 0.1 Mode
X
X
X X
X X
X X
X X
X X
X X
X X
All other
X
X
X
X
X
X
X
X
codes
X
0
0
0
X
1
0
1
0
X
X
0
0
0
0
0
1
1
0
1
1
1
1
0
0
1
0
0
1
1
0
1
Erase Flash/EE Program,
Data, and Security Modes
Read Device Signature/ID
Program Code Byte
Program Data Byte
Read Code Byte
Read Data Byte
Program Security Modes
Read/Verify Security Modes
Redundant
5V
VDD
P0
G ND
P RO GRA M
DA TA
(D0 ›D7)
ADuC83 4
PRO GRA M M O DE
(SE E TA B LE X III)
CO M MA ND
E NA B LE
NE G A TIV E
E DG E
E NTRY
S E QUE NCE
G ND
VDD
P3
P 3.0
P1
P2
P 3.6
PSEN
A LE
P RO GRA M
A DDRE S S
(A0›A 13 )
(P2.0 = A 0)
(P1.7 = A 13)
W RITE ENA BLE
S TRO BE
RE S E T
Figure 27. Flash/EE Memory Parallel Programming
00 00 H
Figure 28. Flash/EE Program Memory Map
Flash/EE Program Memory Security
The ADuC834 facilitates three modes of Flash/EE program
memory security. These modes can be independently activated,
restricting access to the internal code space. These security
modes can be enabled as part of serial download protocol as
described in technote uC004 or via parallel programming. The
security modes available on the ADuC834 are described as
follows:
Lock Mode
This mode locks the code memory, disabling parallel programming of the program memory. However, reading the memory in
parallel mode and reading the memory via a MOVC command
from extrenal memory is still allowed.
This mode is deactivated by initiating a ‘code-erase’ command
in serial download or parallel programming modes.
Secure Mode
This mode locks the code memory, disabling parallel programming
of the program memory. Reading/Verifying the memory in
parallel mode and reading the internal memory via a MOVC
command from external memory is also disabled.
This mode is deactivated by initiating a “code-erase” command
in serial download or parallel programming modes.
Serial Safe Mode
This mode disables serial download capability on the device. If
Serial Safe mode is activated and an attempt is made to reset the
part into serial download mode, i.e., RESET asserted and
de-asserted with PSEN low, the part will interpret the serial download reset as a normal reset only. It will therefore not enter serial
download mode but only execute a normal reset sequence.
Serial Safe mode can only be disabled by initiating a codeerase command in parallel programming mode.
–38–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
USING THE FLASH/EE DATA MEMORY
Byte 1
Byte 2
Byte 3
Byte 4
3FEh
Byte 1
Byte 2
Byte 3
Byte 4
03h
Byte 1
Byte 2
Byte 3
Byte 4
02h
Byte 1
Byte 2
Byte 3
Byte 4
01h
Byte 1
Byte 2
Byte 3
Byte 4
00h
Byte 1
Byte 2
Byte 3
Byte 4
PAGE ADDRESS
(EADRH/
The 4kBytes of Flash/EE data memory is configured as 1024
pages, each of 4 bytes. As with the other ADuC834 peripherals,
the interface to this memory space is via a group of registers
mapped in the SFR space. A group of four data registers
(EDATA1–4) are used to hold the 4 bytes of data at each
page. The page is addressed via the two registers EADRH and
EADRL. Finally, ECON is an 8-bit control register that may be
written with one of nine Flash/EE memory access commands to
trigger various read, write, erase, and verify functions.
3FFh
A block diagram of the SFR interface to the flash/EE data
memory array is shown in figure 29.
ECON—Flash/EE Memory Control SFR
Programming of either the flash/EE data memory or the flash/
EE program memory is done through the flash/EE memory
control SFR (ECON). This SFR allows the user to read, write,
erase or verify the 4 KBytes of flash/EE data memory or the 54
KBytes of flash/EE program memory
Figure 29. Flash/EE Data Memory Control and Configuration
Table XIV. Flash/EE Memory Parallel Programming Modes
ECON VALUE
COMMAND DESCRIPTION
(NORMAL MODE) (power on default)
COMMAND DESCRIPTION
(ULOAD MODE)
01H
READ
Results in 4 bytes in the flash/EE data memory,
addressed by the page address EADRH/L, being read
into EDATA 1 to 4.
Not Implemented. Use the MOVC instruction
02H
WRITE
Results in 4 bytes in EDATA1-4 being written to the
flash/EE data memory, at the page address EADRH/L
(0≤EADRH/L<0400h)
Note: The 4 bytes in the page being addressed must
be pre-erased.
Results in bytes 0-255 of internal XRAM being written
to the 256 bytes of flash/EE program memory at the
page address EADRH. (0≤EADRH<E0H)
Note: The 256 bytes in the page being addressed must
be pre-erased.
03H
Reserved Command
Reserved Command
04H
VERIFY
Verifies if the data in EDATA1-4 is contained in the
page address given by EADRH/L. A subsequent read
of the ECON SFR will result in a 0 being read if the
verification is valid, or a nonzero value being read to
indicate an invalid verification.
Not Implemented. Use the MOVC and MOVX
Instructions to verify the WRITE in software
05H
Results in the Erase of the 4 byte page of flash/EE data Results in the 64 Byte page of flash/EE program
ERASE PAGE memory addressed by the page address EADRH/L
memory, addressed by the byte address EADRH/L
being erased. EADRL can equal any of 64 locations
within the page. A new page starts whenever EADRL is
equal to 00h, 40h, 80h or C0h
06H
ERASE ALL
Results in the erase of entire 4kBytes of flash/EE
data memory.
Results in the Erase of the entire 56kBytesof ULOAD
flash/EE program memory.
81H
READBYTE
Results in the byte in the flash/EE data memory,
addressed by the byte address EADRH/L, being read
into EDATA1. (0≤EADRH/L≤0FFFh.)
Results in the byte in the flash/EE program memory,
addressed by the byte address EADRH/L, being read
into EDATA1. (0≤EADRH/L≤F7FFh.)
81H
WRITEBYTE
Results in the byte in EDATA1 being written into
flash/EE data memory, at the byte address EADRH/L.
Results in the byte in EDATA1 being written into
flash/EE prog memory, at the byte address EADRH/L.
0FH
EXULOAD
Leaves the ECON instructions operate on the
flash/EE data memory.
Enters NORMAL mode allowing subsequent ECON
instructions operate on the flash/EE program memory.
F0H
ULOAD
Enters ULOAD mode allowing subsequent ECON
instructions operate on the flash/EE data memory.
Leaves the ECON instructions operate on the flash/EE
program memory.
REV. PrC (12 March 2002)
–39–
PRELIMINARY TECHNICAL DATA
ADuC834
Example: Programming the flash/EE data memory
Flash/EE Memory Timing
A user wishes to write F3H into the second byte on Page 03H of
the Flash/EE Data Memory space while preserving the other three
bytes already in this page.
Typical program and erase times for the ADuC834 are as follows:
NORMAL MODE (operating on flash/EE data memory)
A typical access to the Flash/EE Data array will involve setting
up the page address of the page to be accessed in the EADRH/
L SFRs, configuring the EDATA1–4 SFRs with data to be programmed to the array (the EDATA SFRs will not be written for
read accesses) and finally, writing the ECON command word
which initiates one of the nine modes shown in Table XIV.
Step 1: Set up the page address:
The two address registers EADRH and EADRL hold the high
byte address and the low byte address of the page to be addressed.
To set the address up in assembly language would appear as
follows.
MOV EADRH,#0
MOV EADRL,#03H
READPAGE (4 bytes)
WRITEPAGE (4 bytes)
VERIFYPAGE (4 bytes)
ERASEPAGE (4 bytes)
ERASEALL (4kBytes)
READBYTE (1 byte)
WRITEBYTE (1 byte)
ULOAD MODE (operating on flash/EE program memory)
; Set Page Address Pointer
WRITEPAGE (256 bytes)
ERASEPAGE (64 bytes)
ERASEALL (56kBytes)
READBYTE (1 byte)
Step 2: Set up the EDATA registers:
We must now write the 4 values to be written into the page
into the 4 SFRs EDATA1-4. Unfortunately we do not know 3
of them. Hence we must read the current page and overwrite
the second byte.
WRITEBYTE (1 byte)
MOV ECON,#1
; Read Page into EDATA1-4
MOV EDATA2,#0F3H ; Overwrite byte 2
Step 3:Program Page:
A byte in the Flash/EE array can only be programmed if it has
previously been erased. To be more specific, a byte can only be
programmed if it already holds the value FFH. Because of the
Flash/EE architecture, this erasure must happen at a page level;
therefore, a minimum of four bytes (1 page) will be erased
when an erase command is initiated. Once the page is erased
we can program the 4 bytes in page and then perform a verification of the data.
MOV
MOV
MOV
MOV
JNZ
ECON,#5
ECON,#2
ECON,#4
A, ECON
ERROR
;
;
;
;
– instruction time +
3 machine cycles
– 380µs
– instruction time +
3 machine cycles
– 2ms
– 2ms
– instruction time +
1 machine cycle
– 200µs
ERASE Page
WRITE Page
VERIFY Page
Check if ECON=0 (OK!)
– 15ms
– 2 ms
– 2 ms
– instruction time +
1 machine cycle
– 200µs
It should be noted that a given mode of operation is initiated as
soon as the command word is written to the ECON SFR. The
core microcontroller operation on the ADuC834 is idled until
the requested Program/Read or Erase mode is completed.
In practice, this means that even though the Flash/EE
memory mode of operation is typically initiated with a twomachine cycle MOV instruction (to write to the ECON SFR),
the next instruction will not be executed until the Flash/EE
operation is complete. This means that the core will not respond
to Interrupt requests until the Flash/EE operation is complete, although the core peripheral functions like Counter/
Timers will continue to count and time as configured throughout this period.
Note:
As with all Flash/EE memory architectures, the array can be
programmed in-system at a byte level, although it must be
erased first; the erasure being performed in page blocks (4byte pages in this case).
Although the 4kBytes of Flash/EE data memory is shipped
from the factory pre-erased, i.e., Byte locations set to FFH, it is
nonetheless good programming practice to include an erase-all
routine as part of any configuration/setup code running on the
ADuC834. An “ERASE-ALL” command consists of writing
“06H” to the ECON SFR, which initiates an erase of the
4kByte Flash/EE array. This command coded in 8051 assembly
would appear as:
MOV ECON,#06H
; Erase all Command
; 2 ms Duration
–40–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
DAC
The ADuC834 incorporates a 12-bit, voltage output DAC onchip. It has a rail-to-rail voltage output buffer capable of driving
10 kΩ/100 pF. It has two selectable ranges, 0 V to VREF (the
internal bandgap 2.5 V reference) and 0 V to AVDD. It can
operate in 12-bit or 8-bit mode. The DAC has a control register, DACCON, and two data registers, DACH/L. The DAC
output can be programmed to appear at Pin 3 or Pin 12. It
should be noted that in 12-bit mode, the DAC voltage output
will be updated as soon as the DACL data SFR has been written; therefore, the DAC data registers should be updated as
DACH first followed by DACL.5The 12-bit DAC data should
be written into DACH/L right-justified such that DACL contains the lower eight bits, and the lower nibble of DACH
contains the upper four bits.
Table XV. DACCON SFR Bit Designations
Bit
Name
Description
7
6
5
4
------DACPIN
3
DAC8
2
DACRN
1
DACCLR
0
DACEN
Reserved for Future Use.
Reserved for Future Use.
Reserved for Future Use.
DAC Output Pin Select.
Set by the user to direct the DAC output to Pin 12 (P1.7/AIN4/DAC).
Cleared by user to direct the DAC output to Pin 3 (P1.2/DAC/IEXC1).
DAC 8-bit Mode Bit.
Set by user to enable 8-bit DAC operation. In this mode the 8-bits in DACL SFR are routed to
the 8 MSBs of the DAC and the 4 LSBs of the DAC are set to zero.
Cleared by user to operate the DAC in its normal 12-bit mode of operation.
DAC Output Range Bit.
Set by user to configure DAC range of 0 – AVDD.
Cleared by user to configure DAC range of 0 – 2.5V (VREF).
DAC Clear Bit.
Set to ‘1’ by user to enable normal DAC operation.
Cleared to ‘0’ by user to reset DAC data registers DACl/H to zero.
DAC Enable Bit.
Set to ‘1’ by user to enable normal DAC operation.
Cleared to ‘0’ by user to power-down the DAC.
DACH/L
DAC Data Registers
Function
SFR Address
DAC Data Registers, written by
DACL (DAC Data Low Byte)
DACH (DAC Data High Byte)
00H
No
Power-On Default Value
Bit Addressable
Using the D/A Converter
The on-chip D/A converter architecture consists of a resistor
string DAC followed by an output buffer amplifier, the functional equivalent of which is illustrated in Figure 30.
AVD D
V R EF
A DuC 834
R
OUTPUT
B U F FE R
R
2 0 DA C 0
R
H IGH Z
D IS A B L E
(F RO M MC U)
R
R
Figure 30. Resistor String DAC Functional Equivalent
REV. PrC (12 March 2002)
user to update the DAC output.
–>FBH
–>FCH
–>Both Registers
–>Both Registers
Features of this architecture include inherent guaranteed monotonicity and excellent differential linearity. As illustrated in
Figure 30, the reference source for each DAC is user selectable
in software. It can be either AVDD or VREF. In 0-to-AVDD mode,
the DAC output transfer function spans from 0V to the voltage at the AVDD pin. In 0-to-VREF mode, the DAC output
transfer function spans from 0V to the internal VREF (2.5V).
The DAC output buffer amplifier features a true rail-to-rail
output stage implementation. This means that, unloaded, each
output is capable of swinging to within less than 100mV of both
AVDD and ground. Moreover, the DAC’s linearity specification
(when driving a 10KΩ resistive load to ground) is guaranteed
through the full transfer function except codes 0 to 48, and, in 0to-AVDD mode only, codes 3945 to 4095.
Linearity degradation near ground and VDD is caused by saturation of the output amplifier, and a general representation of its
effects (neglecting offset & gain error) is illustrated in Figure
31. The dotted line in Figure 31 indicates the ideal transfer
function, and the solid line represents what the transfer function might look like with endpoint non-linearities due to
saturation of the output amplifier.
–41–
PRELIMINARY TECHNICAL DATA
ADuC834
Note that Figure 31 represents a transfer function in 0-to-VDD
mode only. In 0-to-VREF mode (with VREF < VDD) the lower
non-linearity would be similar, but the upper portion of the
transfer function would follow the “ideal” line right to the end,
showing no signs of endpoint linearity errors.
3
output voltage [V]
DAC loaded with 0FFF hex
VDD
V D D - 5 0m V
V DD - 1 00 m V
2
1
DAC loaded with 0000 hex
0
0
5
10
15
source/sink current [mA]
10 0m V
Figure 33. Source & Sink Current Capability
with VREF = VDD = 3V
50m V
0V
FF F H ex
00 0 Hex
For larger loads the current drive capability may not be sufficient. In order to increase the Source & Sink current capability
of the DACs an external buffer should be added, as shown in
figure 34.
Figure 31. Endpoint Non-linearities due to Amplifier
Saturation.
The endpoint non-linearities conceptually illustrated in Figure
31 get worse as a function of output loading. Most of the
ADuC834’s datasheet specifications assume a 10KΩ resistive
load to ground at the DAC output. As the output is forced to
source or sink more current, the nonlinear regions at the top
or bottom (respectively) of Figure 31 become larger. With
larger current demands, this can significantly limit output
voltage swing. Figure 32 & Figure 33 illustrate this behavior.
It should be noted that the upper trace in each of these figures
is only valid for an output range selection of 0-to-AVDD. In 0to-VREF mode, DAC loading will not cause high-side voltage
drops as long as the reference voltage remains below the upper
trace in the corresponding figure. For example, if AVDD=3V &
VREF=2.5V, the high-side voltage will not be affected by loads
less than 5mA. But somewhere around 7mA the upper curve
in Figure 33 drops below 2.5V (VREF) indicating that at these
higher currents the output will not be capable of reaching
VREF.
5
20
A D u C 8 34
+
21
Figure 34. Buffering the DAC outputs
The DAC output buffer also features a high-impedance disable
function. In the chip’s default power-on state, both DACs are
disabled, and their outputs are in a high-impedance state (or
“tri-state”) where they remain inactive until enabled in software.
This means that if a zero output is desired during power-up or
power-down transient conditions, then a pull-down resistor
must be added to each DAC output. Assuming this resistor is
in place, the DAC outputs will remain at ground potential
whenever the DAC is disabled.
D A C lo ad ed w ith 0F F F h ex
o u tp u t v o lta g e [V ]
+
4
3
2
1
D A C lo a d e d w ith 0 00 0 he x
0
0
5
10
15
s o u rce /s in k c u rren t [m A ]
Figure 32. Source and Sink Current Capability
with VREF = VDD = 5V
–42–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
PULSE WIDTH MODULATOR BLOCK (PWM)
CL K SE L 0
The PWM is one of the new features of the ADuC834 over the
ADuC824. The PWM can be configured as a Σ∆ DAC with up
to 16-bits of resolution or as a PWM with variable resolution.
The PWM is widely programmable in terms input clock, clock
dividers and PWM mode to produce a highly flexible PWM. A
block diagram of the PWM is shown in figure X, with each of
the modes explained overleaf.
CL K SE L 1
CL K DIV 0
CL K DIV 1
12.583M Hz
T0
CL O C K
S E LE C T
32.768kH z
P RO G
DIV ID E R
32.768kHz /15
16 B IT PW M C O U NT E R
The PWM uses 5 extra SFRs; the control SFR, PWMCON,
and 4 data SFRs PWM0H, PWM0L, PWM1H and PWM1L.
P 1.0
PWMCON (as described below) controls the different modes
as well as the clock frequency.
CO M PA RE
P 1.1
PWM0H/L and PWM1H/L are the data regaisters that determine the outputs at P1.0 and P1.1.
M D2
M D1
M D0
M ODE
P W M 0H /L
P W M 1H /L
Figure 35. PWM Block Diagram
PWMCON
SFR Address
Power-On Default Value
Bit Addressable
PWM Control SFR
AEh
00h
No
Table XVI. PWMCON SFR Bit Designations
Bit
Name
Description
7
-
Reserved for future use
6
5
4
MD2
MD1
MD0
PWM Mode Bits
The MD2/1/0 bits choose
MD2
MD1
MD0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
3
2
CDIV1
CDIV0
PWM Clock Divider
Scale the clock source for the PWM counter as shown below.
CDIV1 CDIV0 Description
0
0
PWM Counter = Selected Clock /1
0
1
PWM Counter = Selected Clock /4
1
0
PWM Counter = Selected Clock /16
1
1
PWM Counter = Selected Clock /64
1
0
CSEL1
CSEL0
PWM Clock Divider
Select the clock source for the PWM as shown below.
CSEL1 CSEL0 Description
0
0
PWM Clock = fXTAL/15
0
1
PWM Clock = fXTAL
1
0
PWM Clock = External Interrupt on P3.4/T0
1
1
PWM Clock = fVCO(12.58MHz)
REV. PrC (12 March 2002)
the PWM mode as follows
Mode
Mode 0: PWM Disabled
Mode 1: Single variable resolution PWM
Mode 2: Twin 8-bit PWM
Mode 3: Twin 16-bit PWM
Mode 4: Dual NRZ 16-bit Σ∆ DAC
Mode 5: Dual 8-bit PWM
Mode 6: Dual RZ 16-bit Σ∆ DAC
Reserved for future use
–43–
PRELIMINARY TECHNICAL DATA
ADuC834
PWM MODES OF OPERATION
P W M 1L
P W M CO UN TE R
MODE 0: PWM disblabled
P W M 0H
P W M 0L
The PWM is disabled allowing P1.0 and P1.1 be used as normal.
P W M 1H
0
P 1.0
MODE 1: Single Variable resolution PWM
P 1.1
In this mode both the pulse length and the cycle time (period) are programmable in user code allowing the resolution
of the PWM to be variable.
Figure 37. PWM Mode 2
PWM1H/L sets the period of the output waveform. Setting
PWM1H/L to 65536 gives a 16-bit PWM with a maximum
output rate of 192Hz (12.583MHz/65536). Setting
PWM1H/L to 4096 gives a 12-bit PWM with a maximum
output rate of 3072Hz (12.583MHz/4096).Reducing
PWM1H/L reduces the resolution but increases the maximum output rate of the PWM.
MODE 3: Twin 16-bit PWM
In this mode the pulse is programmable but the cycle time
(period) is fixed. The PWM counter is fixed to count from 0
to 65536 giving a fixed 16-bit resolution. This means that
the maximum output of the PWM is 192Hz.
PWM0H/L sets the width of the output waveform as shown
in the diagram below.
As shown below while the PWM counter is less than
PWM0H/L then the output of PWM0 (P1.0) is high. Once
the PWM counter equals PWM0H/L then PWM0 (P1.0)
goes low and remains low until the PWM counter is rolls
over.
P W M 1H /L
P W M CO UN TE R
Similarly while the PWM counter is less than PWM1H/L
then the output of PWM1 (P1.1) is high. Once the PWM
counter equals PWM1H/L then PWM1 (P1.1) goes low and
remains low until the PWM counter is rolls over.
P W M 0H /L
0
In this mode PWMs must be synchronised. i.e. Both PWM0
(P1.0) and PWM1 (P1.1) go high at the same time.
P 1.0
Figure 36. ADuC834 PWM in Mode 1
655 36
MODE 2: Twin 8-bit PWM
P W M C O U NT E R
P W M 1H/L
In this mode both the pulse and cycle time (period) are programmable however the maximum resolution of the PWM
output is 8-bits.
P W M 0H/L
0
PWM1L sets the period for both PWM outputs. Typically this
will be set to 255 (FFh) to give an 8-bit PWM although it is
possible to reduce this as necessary. A value of 100 is loaded
here to give a percentage PWM (i.e. the PWM is accurate to
1%).
P 1.0
P 1.1
Figure 38. PWM Mode 3
The ouputs of the PWM at P1.0 and P1.1 are shown in the
diagram below. As can be seen the output of PWM0 (P1.0)
goes low when the PWM counter equals PWM0L. The output
of PWM1 (P1.1) goes high when the PWM counter equals
PWM1H and goes low again when the PWM counter equals
PWM0H. Often PWM1H will be set to 0 so that both outputs
start simultaneously.
–44–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
MODE 4: Dual NRZ 16-bit Σ∆ DAC
P W M 1L
P W M C O U NT E RS
Mode 4 provides a high speed PWM output similar to that of a
Σ∆ DAC. Typically this mode will be used with the 12.58MHz
clock.
P W M 1H
P W M 0L
P W M 0H
In this mode P1.0 and P1.1 are updated every PWM clock
(80ns in the case of 12.58MHz). Over any 65536 cycles (16 bit
PWM) PWM0 (P1.0) is high for PWM0H/L cycles and low for
65536 - PWM0H/L. Similarly PWM1 (P1.1) is high for
PWM1H/L cycles during this same time.
0
P 1.0
P 1.1
For lower resolution, higher speed DAC outputs write 0’s to
the LSBs that are not required. If for example only 12 bit performance is required then write 0’s to the 4LSBs. This means
that 12 bit accuracy in the PWM output can occur at 3kHz.
Similary writing 0’s to the 8LSBs gives 8 bit accuracy at 49kHz.
e.g. if PWM0H was set to 4010H (slightly above one quater of
FS) then typically P1.0 will be low for three clocks and high for
one clock (each clock is 80ns appox). Over every 65536 clocks
the PWM will compromise for the fact that the output should
be slightly above one quater of fullscale by leaving the output
high for two clocks in four every so often.
Figure 40. PWM Mode 5
MODE 6: Dual RZ 16-bit Σ∆ DAC
Mode 6 provides the exact same functionality as mode 4
except that in this mode the PWM output is ANDed with
the PWM clock. i.e. every output 1 is only high for half a
clock and low for the other half clock. This return to zero
(RZ) mode reduces any errors due to mismatch between rise
time and fall time of the PWM outputs and is recommended
over mode 4 for accurate PWM outputs.
The disadvantage of this mode is that the dynamic range of
the PWM output is halved from 0->DVDD to 0->DVDD/2.
PWM0H/L
e.g. if PWM0H was set to 4010H (slightly above one quater
of FS) then typically P1.0 will be low for three full clocks (3
x 80ns), high for half a clock (40ns) and then low again for
half a clock (40ns) before repeating itself. Over every 65536
clocks the PWM will compromise for the fact that the output should be slightly above one quater of fullscale by
leaving the output high for two half clocks in four every so
often.
CA RR Y O UT A T P 1.0
0
16 B IT
0,
, ‰, …, 0
1
1
0
1
0 0
1
0
0 0
1
1
+
80u s
16 B IT
16 B IT
L A TC H
12.583MHz
16 B IT
16 B IT
PWM0H/L
0,
, ‰, …, 0
…
0
CA RRY O UT AT P 1.0
CA RR Y O UT A T P 1.1
0
1
1
1
0
1
0
0
1
0
0 0
1
16 B IT
16 B IT
0,
, ‰, …, 0
+
80u s
PWM1H/L
80u s
16 B IT
16 B IT
Figure 39. PWM Mode 4
12.583MHz
L A TC H
16 B IT
16 B IT
MODE 5: Dual 8-bit PWM
0
0,
In this mode both the pulse and cycle time (period) are independently programmable by using the high and low bytes of the
PWM counters independently. The output resolution and
period are set by the PWM1L and PWM1H registers for the
P1.0 and P1.1 outputs respectively. PWM0L and PWM0H will
set the width of the high pulse for the P1.0 and P1.1 outputs
respectively. Both channels have same clock source and clock
divider.
REV. PrC (12 March 2002)
–45–
, ‰, …, 0
…
CA RRY O UT AT P 1.1
16 B IT
80u s
PWM1H/L
Figure 41. PWM Mode 6
PRELIMINARY TECHNICAL DATA
ADuC834
ON-CHIP PLL
The ADuC834 is intended for use with a 32.768 kHz watch
crystal. A PLL locks onto a multiple (384) of this to provide a
stable 12.582912 MHz clock for the system. The core can
operate at this frequency or at binary submultiples of it to
allow power saving in cases where maximum core performance is not required. The default core clock is the PLL
PLLCON
PLL Control Register
SFR Address
Power-On Default Value
Bit Addressable
D7H
03H
No
clock divided by 8 or 1.572864 MHz. The ADC clocks are also
derived from the PLL clock, with the modulator rate being the
same as the crystal oscillator frequency. The above choice of
frequencies ensures that the modulators and the core will be
synchronous, regardless of the core clock rate. The PLL control register is PLLCON.
Table XVII. PLLCON SFR Bit Designations
Bit
Name
Description
7
OSC_PD
6
LOCK
5
4
3
--LTEA
FINT
2
1
0
CD2
CD1
CD0
Oscillator Power-down Bit.
Set by user to halt the 32 kHz oscillator in power-down mode.
Cleared by user to enable the 32 kHz oscillator in power-down mode.
This feature allows the TIC to continue counting even in power-down mode.
PLL Lock Bit.
This is a read only bit.
Set automatically at power-on to indicate the PLL loop is correctly tracking the crystal clock. If the
external crystal becomes subsequently disconnected the PLL will rail and the core will halt.
Cleared automatically at power-on to indicate the PLL is not correctly tracking the crystal clock.
This may be due to the absence of a crystal clock or an external crystal at power-on. In this mode,
the PLL output can be 12.58 MHz ± 20%.
Reserved for future use; should be written with ‘0.’
Reading this bit returns the state of the external EA pin latched at reset or power-on.
Fast Interrupt Response Bit.
Set by user enabling the response to any interrupt to be executed at the fastest core clock frequency,
regardless of the configuration of the CD2–0 bits (see below). After user code has returned from an
interrupt, the core resumes code execution at the core clock selected by the CD2–0 bits.
Cleared by user to disable the fast interrupt response feature.
CPU (Core Clock) Divider Bits.
This number determines the frequency at which the microcontroller core will operate.
CD2
CD1
CD0
Core Clock Frequency (MHz)
0
0
0
12.582912
0
0
1
6.291456
0
1
0
3.145728
0
1
1
1.572864 (Default Core Clock Frequency)
1
0
0
0.786432
1
0
1
0.393216
1
1
0
0.196608
1
1
1
0.098304
–46–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
TIME INTERVAL COUNTER (TIC)
A time interval counter is provided on-chip for:
- counting longer intervals than the standard
8051-compatible timers are capable of
- periodically the part up from power down
- implementing a Real Time Clock
The TIC is capable of timeout intervals ranging from 1/128th
second to 255 hours. Furthermore, this counter is clocked by
the crystal oscillator rather than the PLL and thus has the
ability to remain active in power-down mode and time long
power-down intervals. This has obvious applications for remote
battery-powered sensors where regular widely spaced readings
are required.
to the TIC interrupt service vector address at 0053 hex. The
TIC-related SFRs are described in Table XVIII. Note also that
the timebase SFRs can be written initially with the current
time, the TIC can then be controlled and accessed by user software. In effect, this facilitates the implementation of a real-time
clock. A block diagram of the TIC is shown in Figure 42.
TCE N
32.768kHz E XTE RNA L CRY S TA L
ITS 0, 1
8-B IT
P RE S CA LE R
HUNDRE DTHS CO UNT E R
HTHSE C
If the TIC is being used as a real time clock (TCEN is set) then
the TCEN bit itself and the HTHSEC, SEC, MIN and HOUR
registers do not get reset after a hardware or watchdog timer
reset. This is to prevent the need to recalibrate the real time
clock after a reset. However, these registers will get reset to 00h
after a power cycle (independent of TCEN) or after any reset if
TCEN is clear.
S E CO ND C O UNTE R
SEC
INTE RVA L
TIM EBA S E
S E LE CTIO N
M UX
TIE N
M INUTE COUNTE R
M IN
Six SFRs are associated with the time interval counter, TIMECON
being its control register. Depending on the configuration of the
IT0 and IT1 bits in TIMECON, the selected time counter register
overflow will clock the interval counter. When this counter is
equal to the time interval value loaded in the INTVAL SFR,
the TII bit (TIMECON.2) is set and generates an interrupt if
enabled (See IEIP2 SFR description under Interrupt System
later in this data sheet.) If the ADuC834 is in power-down
mode, again with TIC interrupt enabled, the TII bit will wake
up the device and resume code execution by vectoring directly
HO UR C O UNTE R
HO U R
INTE RVA L TIME O UT
TIM E INTE RV A L COUNTE R INTERRUP T
8-B IT
INTE RVA L CO UNTER
E QUA L?
INTV A L S FR
Figure 42. TIC, Simplified Block Diagram
Table XVIII. TIMECON SFR Bit Designations
Bit
Name
Description
7
6
5
4
----ITS1
ITS0
3
STI
2
TII
1
TIEN
0
TCEN
Reserved for Future Use.
Reserved for Future Use. For future product code compatibility this bit should be written as a ‘1.’
Interval Timebase Selection Bits.
Written by user to determine the interval counter update rate.
ITS1
ITS0
Interval Timebase
0
0
1/128 Second
0
1
Seconds
1
0
Minutes
1
1
Hours
Single Time Interval Bit.
Set by user to generate a single interval timeout. If set, a timeout will clear the TIEN bit.
Cleared by user to allow the interval counter to be automatically reloaded and start counting again at
each interval timeout.
TIC Interrupt Bit.
Set when the 8-bit Interval Counter matches the value in the INTVAL SFR.
Cleared by user software.
Time Interval Enable Bit.
Set by user to enable the 8-bit time interval counter.
Cleared by user to disable and clear the contents of the interval counter.
Time Clock Enable Bit.
Set by user to enable the time clock to the time interval counters.
Cleared by user to disable the clock to the time interval counters and clear the time interval SFRs.
The time registers (HTHSEC, SEC, MIN and HOUR) can be written while TCEN is low.
REV. PrC (12 March 2002)
–47–
PRELIMINARY TECHNICAL DATA
ADuC834
INTVAL
User Time Interval Select Register
Function
User code writes the required time interval to this register. When the 8-bit interval counter is equal
to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) bit is set and
generates an interrupt if enabled. (See IEIP2 SFR description under Interrupt System later in this
data sheet.)
A6H
00H
No
0 to 255 decimal
SFR Address
Power-On Default Value
Bit Addressable
Valid Value
HTHSEC
Hundredths Seconds Time Register
Function
This register is incremented in (1/128) second intervals once TCEN in TIMECON is active. The
HTHSEC SFR counts from 0 to 127 before rolling over to increment the SEC time register.
A2H
00H
No
0 to 127 decimal
SFR Address
Power-On Default Value
Bit Addressable
Valid Value
SEC
Seconds Time Register
Function
This register is incremented in 1-second intervals once TCEN in TIMECON is active. The SEC
SFR counts from 0 to 59 before rolling over to increment the MIN time register.
A3H
00H
No
0 to 59 decimal
SFR Address
Power-On Default Value
Bit Addressable
Valid Value
MIN
Minutes Time Register
Function
This register is incremented in 1-minute intervals once TCEN in TIMECON is active. The MIN
counts from 0 to 59 before rolling over to increment the HOUR time register.
A4H
00H
No
0 to 59 decimal
SFR Address
Power-On Default Value
Bit Addressable
Valid Value
HOUR
Hours Time Register
Function
This register is incremented in 1-hour intervals once TCEN in TIMECON is active. The HOUR
SFR counts from 0 to 23 before rolling over to 0.
A5H
00H
No
0 to 23 decimal
SFR Address
Power-On Default Value
Bit Addressable
Valid Value
–48–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
WATCHDOG TIMER
The purpose of the watchdog timer is to generate a device reset or
interrupt within a reasonable amount of time if the ADuC834
enters an erroneous state, possibly due to a programming
error, electrical noise, or RFI. The Watchdog function can be
disabled by clearing the WDE (Watchdog Enable) bit in the
Watchdog Control (WDCON) SFR. When enabled; the watchdog
circuit will generate a system reset or interrupt (WDS) if the user
program fails to set the watchdog (WDE) bit within a predeter-
mined amount of time (see PRE3–0 bits in WDCON). The
watchdog timer itself is a 16-bit counter that is clocked at
32.768 kHz. The watchdog time-out interval can be adjusted
via the PRE3–0 bits in WDCON. Full Control and Status of
the watchdog timer function can be controlled via the watchdog timer control SFR (WDCON). The WDCON SFR can
only be written by user software if the double write sequence
described in WDWR below is initiated on every write access to
the WDCON SFR.
WDCON
Watchdog Timer Control Register
SFR Address
Power-On Default Value
Bit Addressable
C0H
10H
Yes
Table XIX. WDCON SFR Bit Designations
Bit
Name
Description
7
6
5
4
PRE3
PRE2
PRE1
PRE0
3
WDIR
2
WDS
1
WDE
0
WDWR
Watchdog Timer Prescale Bits.
The Watchdog timeout period is given by the equation: tWD = (2PRE × (29/fPLL))
(0 ≤ PRE ≤ 7; fPLL = 32.768 kHz)
PRE3 PRE2
PRE1
PRE0
Timout Period (ms) Action
0
0
0
0
15.6
Reset or Interrupt
0
0
0
1
31.2
Reset or Interrupt
0
0
1
0
62.5
Reset or Interrupt
0
0
1
1
125
Reset or Interrupt
0
1
0
0
250
Reset or Interrupt
0
1
0
1
500
Reset or Interrupt
0
1
1
0
1000
Reset or Interrupt
0
1
1
1
2000
Reset or Interrupt
1
0
0
0
0.0
Immediate Reset
PRE3–0 > 1001
Reserved
Watchdog Interrupt Response Enable Bit.
If this bit is set by the user, the watchdog will generate an interrupt response instead of a
system reset when the watchdog timeout period has expired. This interrupt is not disabled by
the CLR EA instruction and it is also a fixed, high-priority interrupt. If the watchdog is not
being used to monitor the system, it can alternatively be used as a timer. The prescaler is used to
set the timeout period in which an interrupt will be generated. (See also Note 1, Table XXXIX
in the Interrupt System section.)
Watchdog Status Bit.
Set by the Watchdog Controller to indicate that a watchdog timeout has occurred.
Cleared by writing a ‘0’ or by an external hardware reset. It is not cleared by a watchdog reset.
Watchdog Enable Bit.
Set by user to enable the watchdog and clear its counters. If a ‘1’ is not written to this bit
within the watchdog timeout period, the watchdog will generate a reset or interrupt, depending on
WDIR. Cleared under the following conditions, User writes ‘0,’ Watchdog Reset (WDIR = ‘0’);
Hardware Reset; PSM Interrupt.
Watchdog Write Enable Bit.
To write data into the WDCON SFR involves a double instruction sequence. The WDWR bit
must be set and the very next instruction must be a write instruction to the WDCON SFR.
e.g.,
CLR
EA
; disable interrupts while writing
; to WDT
SETB
WDWR
; allow write to WDCON
MOV
WDCON, #72h
; enable WDT for 2.0s timeout
SETB
EA
; enable interrupts again (if rqd)
REV. PrC (12 March 2002)
–49–
PRELIMINARY TECHNICAL DATA
ADuC834
POWER SUPPLY MONITOR
As its name suggests, the Power Supply Monitor, once enabled, monitors both supplies (AVDD or DVDD) on the
ADuC834. It will indicate when any of the supply pins drop
below one of four user-selectable voltage trip points from
2.63 V to 4.63 V. For correct operation of the Power Supply
Monitor function, AVDD must be equal to or greater than
2.7 V. Monitor function is controlled via the PSMCON SFR.
If enabled via the IEIP2 SFR, the monitor will interrupt the
core using the PSMI bit in the PSMCON SFR. This bit will
not be cleared until the failing power supply has returned
above the trip point for at least 250 ms. This monitor function
allows the user to save working registers to avoid possible data
loss due to the low supply condition, and also ensures that
normal code execution will not resume until a safe supply
level has been well established. The supply monitor is also
protected against spurious glitches triggering the interrupt
circuit.
PSMCON
Power Supply Monitor Control Register
SFR Address
Power-On Default Value
Bit Addressable
DFH
DEH
No
Table XX. PSMCON SFR Bit Designations
Bit
Name
Description
7
CMPD
6
CMPA
5
PSMI
4
3
TPD1
TPD0
2
1
TPA1
TPA0
0
PSMEN
DVDD Comparator Bit
This is a read-only bit and directly reflects the state of the DVDD comparator.
Read ‘1’ indicates the DVDD supply is above its selected trip point.
Read ‘0’ indicates the DVDD supply is below its selected trip point.
AVDD Comparator Bit.
This is a read-only bit and directly reflects the state of the AVDD comparator.
Read ‘1’ indicates the AVDD supply is above its selected trip point.
Read ‘0’ indicates the AVDD supply is below its selected trip point.
Power Supply Monitor Interrupt Bit.
This bit will be set high by the MicroConverter if either CMPA or CMPD are low, indicating
low analog or digital supply. The PSMI bit can be used to interrupt the processor. Once CMPD
and/or CMPA return (and remain) high, a 250 ms counter is started. When this counter times
out, the PSMI interrupt is cleared. PSMI can also be written by the user. However, if either comparator output is low, it is not possible for the user to clear PSMI.
DVDD Trip Point Selection Bits.
These bits select the DVDD trip-point voltage as follows:
TPD1
TPD0
Selected DVDD Trip Point (V)
0
0
4.63
0
1
3.08
1
0
2.93
1
1
2.63
AVDD Trip Point Selection Bits.
These bits select the AVDD trip-point voltage as follows:
TPA1
TPA0
Selected AVDD Trip Point (V)
0
0
4.63
0
1
3.08
1
0
2.93
1
1
2.63
Power Supply Monitor Enable Bit.
Set to ‘1’ by the user to enable the Power Supply Monitor Circuit.
Cleared to ‘0’ by the user to disable the Power Supply Monitor Circuit.
–50–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
SERIAL PERIPHERAL INTERFACE
The ADuC834 integrates a complete hardware Serial Peripheral Interface (SPI) interface on-chip. SPI is an industry standard
synchronous serial interface that allows eight bits of data to
be synchronously transmitted and received simultaneously, i.e.,
full duplex. It should be noted that the SPI pins SCLOCK and
MOSI are multiplexed with the digital output pins D0 and D1.
This pins are controlled via the DCON SFR only if SPE is clear.
SPI can be configured for Master or Slave operation and typically
consists of four pins, namely:
MISO (Master In, Slave Out Data I/O Pin), Pin#14
The MISO (master in slave out) pin is configured as an input
line in master mode and an output line in slave mode. The
MISO line on the master (data in) should be connected to the
MISO line in the slave device (data out). The data is transferred as byte wide (8-bit) serial data, MSB first.
MOSI (Master Out, Slave In Pin), Pin#27
The MOSI (master out slave in) pin is configured as an output line
in master mode and an input line in slave mode. The MOSI
line on the master (data out) should be connected to the MOSI
line in the slave device (data in). The data is transferred as byte
wide (8-bit) serial data, MSB first.
SCLOCK (Serial Clock I/O Pin), Pin#26
SS (Slave Select Input Pin), Pin#13
The master clock (SCLOCK) is used to synchronize the
data being transmitted and received through the MOSI and
MISO data lines. A single data bit is transmitted and received in each SCLOCK period. Therefore, a byte is
transmitted/received after eight SCLOCK periods. The
SCLOCK pin is configured as an output in master mode and
as an input in slave mode. In master mode the bit-rate, polarity
and phase of the clock are controlled by the CPOL, CPHA,
SPR0 and SPR1 bits in the SPICON SFR (see Table XXI
below). In slave mode the SPICON register will have to be
configured with the phase and polarity (CPHA and CPOL)
as the master as for both master and slave mode the data is
transmitted on one edge of the SCLOCK signal and sampled
on the other.
The Slave Select (SS) input pin is only used when the
ADuC834 is configured in SPI slave mode. This line is active
low. Data is only received or transmitted in slave mode when
the SS pin is low, allowing the ADuC834 to be used in single
master, multislave SPI configurations. If CPHA = 1 then the SS
input may be permanently pulled low. With CPHA = 0 then
the SS input must be driven low before the first bit in a byte
wide transmission or reception and return high again after the
last bit in that byte wide transmission or reception. In SPI
Slave Mode, the logic level on the external SS pin (Pin# 13),
can be read via the SPR0 bit in the SPICON SFR.
The following SFR registers are used to control the SPI interface.
Table XXI. SPICON SFR Bit Designations
Bit
Name
Description
7
ISPI
6
WCOL
5
SPE
4
SPIM
3
CPOL
2
CPHA
1
0
SPR1
SPR0
SPI Interrupt Bit.
Set by MicroConverter at the end of each SPI transfer.
Cleared directly by user code or indirectly by reading the SPIDAT SFR
Write Collision Error Bit.
Set by MicroConverter if SPIDAT is written to while an SPI transfer is in progress.
Cleared by user code.
SPI Interface Enable Bit.
Set by user to enable the SPI interface.
Cleared by user to allow the DCON SFR control the digital output pins D0 and D1
SPI Master/Slave Mode Select Bit.
Set by user to enable Master Mode operation (SCLOCK is an output).
Cleared by user to enable Slave Mode operation (SCLOCK is an input).
Clock Polarity Select Bit.
Set by user if SCLOCK idles high.
Cleared by user if SCLOCK idles low.
Clock Phase Select Bit.
Set by user if leading SCLOCK edge is to transmit data.
Cleared by user if trailing SCLOCK edge is to transmit data.
SPI Bit-Rate Select Bits.
These bits select the SCLOCK rate (bit-rate) in Master Mode as follows:
SPR1
SPR0
Selected Bit Rate
0
0
fCORE/2
0
1
fCORE/4
1
0
fCORE/8
1
1
fcore/16
In SPI Slave Mode, i.e., SPIM = 0, the logic level on the external SS pin (Pin# 13), can be read
via the SPR0 bit.
NOTE
The CPOL and CPHA bits should both contain the same values for master and slave devices.
REV. PrC (12 March 2002)
–51–
PRELIMINARY TECHNICAL DATA
ADuC834
SPIDAT
SPI Data Register
Function
The SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user
code to read data just received by the SPI interface.
F7H
00H
No
SFR Address
Power-On Default Value
Bit Addressable
Using the SPI Interface
Depending on the configuration of the bits in the SPICON
SFR shown in Table XXI, the ADuC834 SPI interface will
transmit or receive data in a number of possible modes. Figure
43 shows all possible ADuC834 SPI configurations and the timing relationships and synchronization between the signals
involved. Also shown in this figure is the SPI interrupt bit
(ISPI) and how it is triggered at the end of each byte-wide communication.
S CLOCK
(CP OL = 1)
S CLOCK
(CP OL = 0)
SS
S A M P LE INP UT
DA TA OUTP UT
?
MSB
B IT 6
B IT 5
B IT 4
B IT 3
B IT 2
B IT 1
LS B
(CP HA = 1)
SPI Interface—Master Mode
In master mode, the SCLOCK pin is always an output and generates a burst of eight clocks whenever user code writes to the
SPIDAT register. The SCLOCK bit rate is determined by
SPR0 and SPR1 in SPICON. It should also be noted that the
SS pin is not used in master mode. If the ADuC834 needs to
assert the SS pin on an external slave device, a Port digital output
pin should be used.
In master mode a byte transmission or reception is initiated
by a write to SPIDAT. Eight clock periods are generated via the
SCLOCK pin and the SPIDAT byte being transmitted via MOSI.
With each SCLOCK period a data bit is also sampled via MISO.
After eight clocks, the transmitted byte will have been completely
transmitted and the input byte will be waiting in the input shift
register. The ISPI flag will be set automatically and an interrupt
will occur if enabled. The value in the shift register will be
latched into SPIDAT.
SPI Interface—Slave Mode
IS P I FLAG
S A M P LE INP UT
DA TA OUTP UT
MSB
B IT 6
B IT 5 B IT 4
B IT 3
B IT 2
B IT 1
LS B
(CP HA = 0)
IS P I FLAG
Figure 43. ADuC834, SPI Timing, All Modes
?
In slave mode the SCLOCK is an input. The SS pin must
also be driven low externally during the byte communication.
Transmission is also initiated by a write to SPIDAT. In slave
mode, a data bit is transmitted via MISO and a data bit is received
via MOSI through each input SCLOCK period. After eight
clocks, the transmitted byte will have been completely transmitted
and the input byte will be waiting in the input shift register. The
ISPI flag will be set automatically and an interrupt will occur
if enabled. The value in the shift register will be latched into
SPIDAT only when the transmission/reception of a byte has
been completed. The end of transmission occurs after the
eighth clock has been received, if CPHA = 1 or when SS returns high if CPHA = 0.
–52–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
DUAL DATA POINTER
The ADuC834 incorporates two data pointers. The second
data pointer is a shadow data pointer and is selected via the
data pointer control SFR (DPCON). DPCON also includes
some nice features such as automatic hardware post increment
and post decrement as well as automatic data pointer toggle.
DPCON is described below.
DPCON
SFR Address
Power-On Default Value
Bit Addressable
Data Pointer Control SFR
A7h
00h
No
Table XXII. DPCON SFR Bit Designations
Bit
Name
Description
7
-
Reserved for future use
6
DPT
Data Pointer automatic toggle enable
Cleared by user to disable auto swapping of the DPTR.
Set in user software to enable automatic toggling of the DPTR after each each MOVX or MOVC
instruction.
5
4
DP1m1
DP1m0
Shadow Data Pointer Mode
These two bits enable extra modes of the shadow data pointer operation allowing for more compact
and more efficient code size and execution.
m1
m0
Behaviour of the Shadow Data Pointer
0
0
8052 Behaviour
0
1
DPTR is post incremented after a MOVX or a MOVC instruction
1
0
DPTR is post decremented after a MOVX or MOVC instruction
1
1
DPTR LSB is toggled after a MOVX or MOVC instruction
(This instruction can be useful for moving 8 bit blocks to/from 16-bit devices)
3
2
DP0m1
DP0m0
Main Data Pointer Mode
These two bits enable extra modes of the main data pointer operation allowing for more compact and
more efficient code size and execution.
m1
m0
Behaviour of the Main Data Pointer
0
0
8052 Behaviour
0
1
DPTR is post incremented after a MOVX or a MOVC instruction
1
0
DPTR is post decremented after a MOVX or MOVC instruction
1
1
DPTR LSB is toggled after a MOVX or MOVC instruction
(This instruction can be useful for moving 8 bit blocks to/from 16-bit devices)
1
-
Not implemented to allow the INC DPCON instruction toggle the data pointer
0
DPSEL
Data Pointer select
Cleared by user to select the main data pointer. This means that the contents of this 24 bit register
is placed into the 3 SFRs DPL, DPH and DPP.
Set by the user to select the shadow data pointer. This means that the contents of a separate 24 bit
register appears in the 3 SFRs DPL, DPH and DPP.
Note 1: This is the only place where the main and shadow data
pointers are distinguished. Everywhere else in this datasheet
wherever the DPTR is mentioned, operation on the active
DPTR is implied.
Note 2: Only MOVC/MOVX @DPTR instructions are relevant
above. MOVC/MOVX [email protected] instructions will not cause the
DPTR to automatically post increment/decrement etc.
To illustrate the operation of DPCON, the following code will
copy 256 bytes of code memory at address D000h into XRAM
starting from address 0000h.
The following piece of code uses 16 bytes and 2054 cycles. To
perform this on a standard 8051 requires approximately 33
bytes and 7172 cycles (depending on how its implemented).
REV. PrC (12 March 2002)
MOV DPTR,#0
MOV DPCON,#55h
;
;
;
;
;
MOV DPTR,#0D000h ;
MOVELOOP:
CLR A
MOVC A,@A+DPTR
;
;
;
MOVX @DPTR,A
;
;
;
MOV A, DPL
JNZ MOVELOOP
–53–
Main DPTR = 0
Select shadow DPTR
DPTR1 increment mode,
DPTR0 increment mode
DPTR auto toggling ON
Shadow DPTR = D000h
Get data
Post Inc DPTR
Swap to Main DPTR (Data)
Put ACC in XRAM
Increment main DPTR
Swap Shadow DPTR (Code)
PRELIMINARY TECHNICAL DATA
ADuC834
high order address bytes during fetches from external program memory and middle and high order address bytes during
accesses to the 16-bit external data memory space.
8051-COMPATIBLE ON-CHIP PERIPHERALS
This section gives a brief overview of the various secondary peripheral circuits are also available to the user on-chip. These
remaining functions are fully 8051-compatible and are controlled
via standard 8051 SFR bit definitions.
Parallel I/O Ports 0–3
The ADuC834 uses four input/output ports to exchange data
with external devices. In addition to performing general-purpose I/O, some ports are capable of external memory operations;
others are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is
enabled, that pin may not be used as a general purpose I/O pin.
Port 0 is an 8-bit open drain bidirectional I/O port that is directly controlled via the Port 0 SFR (SFR address = 80 hex).
Port 0 pins that have 1s written to them via the Port 0 SFR will
be configured as open drain and will therefore float. In that
state, Port 0 pins can be used as high impedance inputs. An
external pull-up resistor will be required on Port 0 outputs to
force a valid logic high level externally. Port 0 is also the multiplexed low-order address and data bus during accesses to external
program or data memory. In this application it uses strong internal
pull-ups when emitting 1s.
Port 1 is also an 8-bit port directly controlled via the P1 SFR
(SFR address = 90 hex). The Port 1 pins are divided into two
distinct pin groupings.
P1.0 and P1.1 pins on Port 1 are bidirectional digital I/O pins with
internal pull-ups. If P1.0 and P1.1 have 1s written to them via the
P1 SFR, these pins are pulled high by the internal pull-up resistors. In this state they can also be used as inputs; as input pins
being externally pulled low, they will source current because of
the internal pull-ups. With 0s written to them, both these pins
will drive a logic low output voltage (VOL) and will be capable of
sinking 10 mA compared to the standard 1.6 mA sink capability on the other port pins. These pins also have various
secondary functions described in Table XXIII.
Port 3 is a bidirectional port with internal pull-ups directly
controlled via the P2 SFR (SFR address = B0 hex). Port 3
pins that have 1s written to them are pulled high by the internal
pull-ups and in that state they can be used as inputs. As inputs,
Port 3 pins being pulled externally low will source current because
of the internal pull-ups. Port 3 pins also have various secondary
functions described in Table XXIV.
Table XXIV. Port 3, Alternate Pin Functions
Pin
Alternate Function
P3.0
RXD (UART Input Pin)
(or Serial Data I/O in Mode 0)
TXD (UART Output Pin)
(or Serial Clock Output in Mode 0)
INT0 (External Interrupt 0)
INT1 (External Interrupt 1)
T0 (Timer/Counter 0 External Input)
T1 (Timer/Counter 1 External Input)
WR (External Data Memory Write Strobe)
RD (External Data Memory Read Strobe)
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
The alternate functions of P1.0, P1.1, and Port 3 pins can only be
activated if the corresponding bit latch in the P1 and P3 SFRs
contains a 1. Otherwise, the port pin is stuck at 0. In the case
of the PWM outputs at P1.0 and P1.1, the PWM outputs will
overwrite anything written to P1.0 or P1.1.
Additional Digital Ouput Pins
Pins P1.0 and P1.1 can be used to provide high current (10mA
sink) general purpose I/O. In addition to P1.0 and P1.1, two more
high current (8mA sink) outputs are provided at D0 and D1. If
the SPE bit (in SPICON) is clear, the two extra high current
digital ouputs, D0 and D1, are controlled via the DCON SFR as
follows:
Table XXV. DCON SFR description
Table XXIII. Port 1, Alternate Pin Functions
Pin
Alternate Function
P1.0
T2 (Timer/Counter 2 External Input)
PWM0 (PWM0 output at this pin)
T2EX (Timer/Counter 2 Capture/Reload Trigger)
PWM1 (PWM1 output at this pin)
P1.1
Bit
The remaining Port 1 pins (P1.2–P1.7) can only be configured
as Analog Input (ADC), Analog Output (DAC) or Digital Input
pins. By (power-on) default these pins are configured as Analog
Inputs, i.e., ‘1’ written in the corresponding Port 1 register bit.
To configure any of these pins as digital inputs, the user should
write a ‘0’ to these port bits to configure the corresponding pin
as a high impedance digital input.
Port 2 is a bidirectional port with internal pull-up resistors directly
controlled via the P2 SFR (SFR address = A0 hex). Port 2 pins
that have 1s written to them are pulled high by the internal pullup resistors and, in that state, they can be used as inputs. As
inputs, Port 2 pins being pulled externally low will source current
because of the internal pull-up resistors. Port 2 emits the
–54–
Name
Description
7
D1
6
D1EN
5
D0
4
3
---D0EN
2
1
0
----------
Data written to this bit will be
outputted on the D1 pin if
D1EN is set.
Set to enable the D1 bit as
an ouput.
Data written to this bit will be
outputted on the DC0 pin if
D0EN is set.
---Set to enable the D0 bit as
an ouput.
----------
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
TIMERS/COUNTERS
The ADuC834 has three 16-bit Timer/Counters: Timer 0,
Timer 1, and Timer 2. The Timer/Counter hardware has been
included on-chip to relieve the processor core of the overhead inherent in implementing timer/counter functionality
in software. Each Timer/Counter consists of two 8-bit registers
THx and TLx (x = 0, 1 and 2). All three can be configured to
operate either as timers or event counters.
In ‘Timer’ function, the TLx register is incremented every machine cycle. Thus one can think of it as counting machine cycles.
Since a machine cycle consists of 12 core clock periods, the
maximum count rate is 1/12 of the core clock frequency.
In ‘Counter’ function, the TLx register is incremented by a 1-to0 transition at its corresponding external input pin, T0, T1, or
T2. In this function, the external input is sampled during
S5P2 of every machine cycle. When the samples show a high in
one cycle and a low in the next cycle, the count is
incremented. The new count value appears in the register during
S3P1 of the cycle following the one in which the transition was
detected. Since it takes two machine cycles (16 core clock periods)
to recognize a 1-to-0 transition, the maximum count rate is 1/16
of the core clock frequency. There are no restrictions on the
duty cycle of the external input signal, but to ensure that a
given level is sampled at least once before it changes, it must be
held for a minimum of one full machine cycle. Remember that
the core clock frequency is programmed via the CD0–2 selection bits in the PLLCON SFR.
User configuration and control of the timers is achieved via
three main SFRs. TMOD and TCON control the configuration of timers 0 and 1 while T2CON configures timer 2.
TMOD
Timer/Counter 0 and 1 Mode Register
SFR Address
Power-On Default Value
Bit Addressable
89H
00H
No
Table XXVI. TMOD SFR Bit Designations
Bit
Name
Description
7
Gate
6
C/T
5
4
M1
M0
3
Gate
2
C/T
1
0
M1
M0
Timer 1 Gating Control.
Set by software to enable timer/counter 1 only while INT1 pin is high and TR1 control bit is set.
Cleared by software to enable timer 1 whenever TR1 control bit is set.
Timer 1 Timer or Counter Select Bit.
Set by software to select counter operation (input from T1 pin).
Cleared by software to select timer operation (input from internal system clock).
Timer 1 Mode Select Bit 1 (Used with M0 Bit).
Timer 1 Mode Select Bit 0.
M1
M0
0
0
TH1 operates as an 8-bit timer/counter. TL1 serves as 5-bit prescaler.
0
1
16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler.
1
0
8-Bit Auto-Reload Timer/Counter. TH1 holds a value which is to be
reloaded into TL1 each time it overflows.
1
1
Timer/Counter 1 Stopped.
Timer 0 Gating Control.
Set by software to enable timer/counter 0 only while INT0 pin is high and TR0 control bit is set.
Cleared by software to enable Timer 0 whenever TR0 control bit is set.
Timer 0 Timer or Counter Select Bit.
Set by software to select counter operation (input from T0 pin).
Cleared by software to select timer operation (input from internal system clock).
Timer 0 Mode Select Bit 1.
Timer 0 Mode Select Bit 0.
M1
M0
0
0
TH0 operates as an 8-bit timer/counter. TL0 serves as 5-bit prescaler.
0
1
16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no prescaler
1
0
8-Bit Auto-Reload Timer/Counter. TH0 holds a value which is to be
reloaded into TL0 each time it overflows.
1
1
TL0 is an 8-bit timer/counter controlled by the standard timer 0 control
bits. TH0 is an 8-bit timer only, controlled by Timer 1 control bits.
REV. PrC (12 March 2002)
–55–
PRELIMINARY TECHNICAL DATA
ADuC834
TCON:
Timer/Counter 0 and 1 Control Register
SFR Address
Power-On Default Value
Bit Addressable
88H
00H
Yes
Table XXVII. TCON SFR Bit Designations
Bit
Name
Description
7
TF1
6
TR1
5
TF0
4
TR0
3
IE11
2
IT11
1
IE01
0
IT01
Timer 1 Overflow Flag.
Set by hardware on a timer/counter 1 overflow.
Cleared by hardware when the Program Counter (PC) vectors to the interrupt service routine.
Timer 1 Run Control Bit.
Set by user to turn on timer/counter 1.
Cleared by user to turn off timer/counter 1.
Timer 0 Overflow Flag.
Set by hardware on a timer/counter 0 overflow.
Cleared by hardware when the PC vectors to the interrupt service routine.
Timer 0 Run Control Bit.
Set by user to turn on timer/counter 0.
Cleared by user to turn off timer/counter 0.
External Interrupt 1 (INT1) Flag.
Set by hardware by a falling edge or zero level being applied to external interrupt pin INT1, depending on bit IT1 state.
Cleared by hardware when the when the PC vectors to the interrupt service routine only if the interrupt was transition-activated. If level-activated, the external requesting source controls the
request flag, rather than the on-chip hardware.
External Interrupt 1 (IE1) Trigger Type.
Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition).
Cleared by software to specify level-sensitive detection (i.e., zero level).
External Interrupt 0 (INT0) Flag.
Set by hardware by a falling edge or zero level being applied to external interrupt pin INT0, depending on bit IT0 state.
Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was
transition-activated. If level-activated, the external requesting source controls the request flag,
rather than the on-chip hardware.
External Interrupt 0 (IE0) Trigger Type.
Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition).
Cleared by software to specify level-sensitive detection (i.e., zero level).
NOTE
1
These bits are not used in the control of timer/counter 0 and 1, but are used instead in the control and monitoring of the external INT0 and INT1 interrupt
pins.
Timer/Counter 0 and 1 Data Registers
Both timer 0 and timer 1 consists of two 8-bit registers. These can be used as independent registers or combined to be a single 16bit register depending on the timer mode configuration.
TH0 and TL0
Timer 0 high byte and low byte.
SFR Address = 8Chex, 8Ahex respectively.
TH1 and TL1
Timer 1 high byte and low byte.
SFR Address = 8Dhex, 8Bhex respectively.
–56–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
TIMER/COUNTER 0 AND 1 OPERATING MODES
Mode 2 (8-Bit Timer/Counter with Auto Reload)
The following paragraphs describe the operating modes for
timer/counters 0 and 1. Unless otherwise noted, it should be
assumed that these modes of operation are the same for timer 0 as
for timer 1.
Mode 2 configures the timer register as an 8-bit counter (TL0)
with automatic reload, as shown in Figure 46. Overflow from TL0
not only sets TF0, but also reloads TL0 with the contents of TH0,
which is preset by software. The reload leaves TH0 unchanged.
Mode 0 (13-Bit Timer/Counter)
Mode 0 configures an 8-bit timer/counter with a divide-by-32 prescaler. Figure 44 shows mode 0 operation.
CORE
CLK*
CORE
CLK*
ⴜ 12
C/T = 0
TL0
(8 BITS)
ⴜ 12
INTERRUPT
TF0
C/T = 1
P3.4/T0
C/T = 0
TL0
(5 BITS)
TH0
(8 BITS)
INTERRUPT
CONTROL
TF0
TR0
C/T = 1
P3.4/T0
RELOAD
TH0
(8 BITS)
GATE
CONTROL
P3.2/INT0
TR0
*THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 46
Figure 46. Timer/Counter 0, Mode 2
GATE
P3.2/INT0
*THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 46
Mode 3 (Two 8-Bit Timer/Counters)
Figure 44. Timer/Counter 0, Mode 0
In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the timer
overflow flag TF0. The overflow flag, TF0, can then be used to
request an interrupt. The counted input is enabled to the timer
when TR0 = 1 and either Gate = 0 or INT0 = 1. Setting Gate = 1
allows the timer to be controlled by external input INT0, to
facilitate pulsewidth measurements. TR0 is a control bit in the
special function register TCON; Gate is in TMOD. The 13-bit
register consists of all eight bits of TH0 and the lower five bits of
TL0. The upper three bits of TL0 are indeterminate and should
be ignored. Setting the run flag (TR0) does not clear the registers.
Mode 3 has different effects on timer 0 and timer 1. Timer 1 in
Mode 3 simply holds its count. The effect is the same as setting
TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two
separate counters. This configuration is shown in Figure 47. TL0
uses the timer 0 control bits: C/T, Gate, TR0, INT0, and TF0.
TH0 is locked into a timer function (counting machine cycles)
and takes over the use of TR1 and TF1 from timer 1. Thus, TH0
now controls the “timer 1” interrupt. Mode 3 is provided for
applications requiring an extra 8-bit timer or counter.
When timer 0 is in Mode 3, timer 1 can be turned on and off by
switching it out of, and into, its own Mode 3, or can still be used by
the serial interface as a Baud Rate Generator. In fact, it can be used,
in any application not requiring an interrupt from timer 1 itself.
Mode 1 (16-Bit Timer/Counter)
CORE
CLK*
Mode 1 is the same as Mode 0, except that the timer register
is running with all 16 bits. Mode 1 is shown in Figure 45.
CORE
CLK/12
ⴜ 12
C/T = 0
INTERRUPT
TL0
(8 BITS)
TF0
TH0
(8 BITS)
TF1
C/T = 1
CORE
CLK*
ⴜ 12
P3.4/T0
TR0
C/T = 0
TL0
TH0
(8 BITS) (8 BITS)
CONTROL
INTERRUPT
TF0
GATE
C/T = 1
P3.2/INT0
P3.4/T0
CONTROL
TR0
CORE
CLK/12
TR1
GATE
INTERRUPT
CONTROL
*THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 46
P3.2/INT0
*THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 46
Figure 47. Timer/Counter 0, Mode 3
Figure 45. Timer/Counter 0, Mode 1
REV. PrC (12 March 2002)
–57–
PRELIMINARY TECHNICAL DATA
ADuC834
TIMER/COUNTER 2 OPERATING MODES
16-Bit Capture Mode
In the ‘Capture’ mode, there are again two options, which are
selected by bit EXEN2 in T2CON. If EXEN2 = 0, then Timer 2
is a 16-bit timer or counter which, upon overflowing, sets bit TF2,
the Timer 2 overflow bit, which can be used to generate an interrupt. If EXEN2 = 1, then Timer 2 still performs the above, but
a l-to-0 transition on external input T2EX causes the current value
in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the
transition at T2EX causes bit EXF2 in T2CON to be set, and
EXF2, like TF2, can generate an interrupt. The Capture Mode
is illustrated in Figure 49.
The following paragraphs describe the operating modes for
timer/counter 2. The operating modes are selected by bits in the
T2CON SFR as shown in Table XXIX.
Table XXVIII. Timer 2 Operating modes
RCLK (or) TCLK
CAP2
TR2
MODE
0
0
1
X
0
1
X
X
1
1
1
0
16-Bit Autoreload
16-Bit Capture
Baud Rate
OFF
The baud rate generator mode is selected by RCLK = 1 and/or
TCLK = 1.
16-Bit Autoreload Mode
In ‘Autoreload’ mode, there are two options, which are selected
by bit EXEN2 in T2CON. If EXEN2 = 0, then when Timer 2
rolls over it not only sets TF2 but also causes the Timer 2 registers
to be reloaded with the 16-bit value in registers RCAP2L and
RCAP2H, which are preset by software. If EXEN2 = 1, then
Timer 2 still performs the above, but with the added feature that
a 1-to-0 transition at external input T2EX will also trigger the
16-bit reload and set EXF2. The autoreload mode is illustrated
in Figure 48 below.
CO RE
CLK *
12
In either case if Timer 2 is being used to generate the baud rate,
the TF2 interrupt flag will not occur. Hence Timer 2 interrupts
will not occur so they do not have to be disabled. In this mode
the EXF2 flag, however, can still cause interrupts and this can
be used as a third external interrupt.
Baud rate generation will be described as part of the UART
serial port operation in the following pages.
C/T 2 = 0
TL2
(8-B ITS )
TH2
(8-B ITS )
RCA P 2L
RCA P 2H
C/T 2 = 1
T2
P IN
CO NTR O L
TR2
RE LO A D
TRA NS ITION
DE TE CTO R
TF2
TIM E R
INTE RRUP T
T2E X
P IN
E X F2
CO NTR O L
E X E N2
* THE CORE CLO CK IS THE OUTP UT OF THE P LL A S DE S CRIB E D ON P A GE 46
Figure 48. Timer/Counter 2, 16-Bit Autoreload Mode
CO RE
CLK *
12
C/T 2 = 0
TL2
(8-B ITS )
TH2
(8-B ITS )
TF2
C/T 2 = 1
T2
P IN
CO NTR O L
TR2
TIM E R
INTE RRUP T
CA P TURE
TRA NS ITION
DE TE CTO R
RCA P 2L
RCA P 2H
T2E X
P IN
E X F2
CO NTR O L
E X E N2
* THE CORE CLO CK IS THE OUTP UT OF THE P LL A S DE S CRIB E D ON P A GE 46
Figure 49. Timer/Counter 2, 16-Bit Capture Mode
–58–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
T2CON
Timer/Counter 2 Control Register
SFR Address
Power-On Default Value
Bit Addressable
C8H
00H
Yes
Table XXIX. T2CON SFR Bit Designations
Bit
Name
Description
7
TF2
6
EXF2
5
RCLK
4
TCLK
3
EXEN2
2
TR2
1
CNT2
0
CAP2
Timer 2 Overflow Flag.
Set by hardware on a timer 2 overflow. TF2 will not be set when either RCLK or TCLK = 1.
Cleared by user software.
Timer 2 External Flag.
Set by hardware when either a capture or reload is caused by a negative transition on T2EX and
EXEN2 = 1.
Cleared by user user software.
Receive Clock Enable Bit.
Set by user to enable the serial port to use timer 2 overflow pulses for its receive clock in serial port
Modes 1 and 3.
Cleared by user to enable timer 1 overflow to be used for the receive clock.
Transmit Clock Enable Bit.
Set by user to enable the serial port to use timer 2 overflow pulses for its transmit clock in serial
port Modes 1 and 3.
Cleared by user to enable timer 1 overflow to be used for the transmit clock.
Timer 2 External Enable Flag.
Set by user to enable a capture or reload to occur as a result of a negative transition on T2EX if
Timer 2 is not being used to clock the serial port.
Cleared by user for Timer 2 to ignore events at T2EX.
Timer 2 Start/Stop Control Bit.
Set by user to start timer 2.
Cleared by user to stop timer 2.
Timer 2 timer or counter function select bit.
Set by user to select counter function (input from external T2 pin).
Cleared by user to select timer function (input from on-chip core clock).
Timer 2 Capture/Reload Select Bit.
Set by user to enable captures on negative transitions at T2EX if EXEN2 = 1.
Cleared by user to enable auto-reloads with Timer 2 overflows or negative transitions at T2EX
when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is
forced to autoreload on Timer 2 overflow.
Timer/Counter 2 Data Registers
Timer/Counter 2 also has two pairs of 8-bit data registers associated with it. These are used as both timer data registers and timer
capture/reload registers.
TH2 and TL2
Timer 2, data high byte and low byte.
SFR Address = CDhex, CChex respectively.
RCAP2H and RCAP2L
Timer 2, Capture/Reload byte and low byte.
SFR Address = CBhex, CAhex respectively.
REV. PrC (12 March 2002)
–59–
PRELIMINARY TECHNICAL DATA
ADuC834
UART SERIAL INTERFACE
The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can
commence reception of a second byte before a previously received byte has been read from the receive register. However, if
the first byte still has not been read by the time reception of the
second byte is complete, the first byte will be lost. The physical
interface to the serial data network is via Pins RXD(P3.0) and
TXD(P3.1) while the SFR interface to the UART is comprised of the following registers.
SBUF
The serial port receive and transmit registers are both accessed
through the SBUF SFR (SFR address = 99 hex). Writing to
SBUF loads the transmit register and reading SBUF accesses a
physically separate receive register.
SCON
UART Serial Port Control Register
SFR Address
Power-On Default Value
Bit Addressable
98H
00H
Yes
Table XXX. SCON SFR Bit Designations
Bit
Name
Description
7
6
SM0
SM1
5
SM2
4
REN
3
TB8
2
RB8
1
TI
0
RI
UART Serial Mode Select Bits.
These bits select the Serial Port operating mode as follows:
SM0
SM1
Selected Operating Mode
0
0
Mode 0: Shift Register, fixed baud rate (Core_Clk/2)
0
1
Mode 1: 8-bit UART, variable baud rate
1
0
Mode 2: 9-bit UART, fixed baud rate (Core_Clk/64) or (Core_Clk/32)
1
1
Mode 3: 9-bit UART, variable baud rate
Multiprocessor Communication Enable Bit.
Enables multiprocessor communication in Modes 2 and 3. In Mode 0, SM2 should be cleared.
In Mode 1, if SM2 is set, RI will not be activated if a valid stop bit was not received. If SM2 is
cleared, RI will be set as soon as the byte of data has been received. In Modes 2 or 3, if SM2 is
set, RI will not be activated if the received ninth data bit in RB8 is 0. If SM2 is cleared, RI will
be set as soon as the byte of data has been received.
Serial Port Receive Enable Bit.
Set by user software to enable serial port reception.
Cleared by user software to disable serial port reception.
Serial Port Transmit (Bit 9).
The data loaded into TB8 will be the ninth data bit that will be transmitted in Modes 2 and 3.
Serial port Receiver Bit 9.
The ninth data bit received in Modes 2 and 3 is latched into RB8. For Mode 1 the stop bit is
latched into RB8.
Serial Port Transmit Interrupt Flag.
Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in
Modes 1, 2, and 3.
TI must be cleared by user software.
Serial Port Receive Interrupt Flag.
Set by hardware at the end of the eighth bit in mode 0, or halfway through the stop bit in
Modes 1, 2, and 3.
RI must be cleared by software.
–60–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
UART OPERATING MODES
Mode 2: 9-Bit UART with Fixed Baud Rate
Mode 0: 8-Bit Shift Register Mode
Mode 2 is selected by setting SM0 and clearing SM1. In this
mode the UART operates in 9-bit mode with a fixed baud rate.
The baud rate is fixed at Core_Clk/64 by default, although
by setting the SMOD bit in PCON, the frequency can be
doubled to Core_Clk/32. Eleven bits are transmitted or received, a
start bit(0), eight data bits, a programmable ninth bit and a stop
bit(1). The ninth bit is most often used as a parity bit, although it
can be used for anything, including a ninth data bit if required.
Mode 0 is selected by clearing both the SM0 and SM1 bits in
the SFR SCON. Serial data enters and exits through RXD. TXD
outputs the shift clock. Eight data bits are transmitted or received. Transmission is initiated by any instruction that writes to
SBUF. The data is shifted out of the RXD line. The eight bits are
transmitted with the least-significant bit (LSB) first, as shown in
Figure 50.
M A CH IN E
CY C LE 1
M A CH IN E
CY C LE 2
S1 S2 S3 S4 S5 S6 S1 S2
M A CH IN E
CY C LE 7
S3 S4
M A CH IN E
CY C LE 8
S4 S5 S6
S1 S2 S3 S4 S5 S6
CO RE
CL K
ALE
RX D
(D A T A O U T)
DA T A B IT 0
DA TA B IT 1
DA T A B IT 6
DA T A B IT 7
TX D
(SH IF T CL O C K )
Figure 50. UART Serial Port Transmission, Mode 0.
Reception is initiated when the receive enable bit (REN) is 1
and the receive interrupt bit (RI) is 0. When RI is cleared the
data is clocked into the RXD line and the clock pulses are
output from the TXD line.
Mode 1: 8-Bit UART, Variable Baud Rate
Mode 1 is selected by clearing SM0 and setting SM1. Each data
byte (LSB first) is preceded by a start bit(0) and followed by a stop
bit(1). Therefore 10 bits are transmitted on TXD or received on
RXD. The baud rate is set by the Timer 1 or Timer 2 overflow
rate, or a combination of the two (one for transmission and the
other for reception).
Transmission is initiated by writing to SBUF. The ‘write to
SBUF’ signal also loads a 1 (stop bit) into the ninth bit position
of the transmit shift register. The data is output bit by bit
until the stop bit appears on TXD and the transmit interrupt
flag (TI) is automatically set as shown in Figure 51.
START
BIT
TXD
STOP BIT
D0
D1
D2
D3
D4
D5
D6
D7
TI
(SCON.1)
SET INTERRUPT
i.e. READY FOR MORE DATA
Figure 51. UART Serial Port Transmission, Mode 0.
Reception is initiated when a 1-to-0 transition is detected on
RXD. Assuming a valid start bit was detected, character reception
continues. The start bit is skipped and the eight data bits are
clocked into the serial port shift register. When all eight bits have
been clocked in, the following events occur:
- The eight bits in the receive shift register are latched into SBUF
- The ninth bit (Stop bit) is clocked into RB8 in SCON
- The Receiver interrupt flag (RI) is set
if, and only if, the following conditions are met at the time the
final shift pulse is generated:
- RI = 0, and
- Either SM2 = 0, or SM2 = 1 and the received stop bit = 1.
If either of these conditions is not met, the received frame is
irretrievably lost, and RI is not set.
REV. PrC (12 March 2002)
To transmit, the eight data bits must be written into SBUF.
The ninth bit must be written to TB8 in SCON. When transmission is initiated the eight data bits (from SBUF) are loaded
onto the transmit shift register (LSB first). The contents of TB8
are loaded into the ninth bit position of the transmit shift register.
The transmission will start at the next valid baud rate clock.
The TI flag is set as soon as the stop bit appears on TXD.
Reception for Mode 2 is similar to that of Mode 1. The eight
data bytes are input at RXD (LSB first) and loaded onto the
receive shift register. When all eight bits have been clocked in,
the following events occur:
- The eight bits in the receive shift register are latched into SBUF
- The ninth data bit is latched into RB8 in SCON
- The Receiver interrupt flag (RI) is set
if, and only if, the following conditions are met at the time the
final shift pulse is generated:
- RI = 0, and
- Either SM2 = 0, or SM2 = 1 and the received stop bit = 1.
If either of these conditions is not met, the received frame is
irretrievably lost, and RI is not set.
Mode 3: 9-Bit UART with Variable Baud Rate
Mode 3 is selected by setting both SM0 and SM1. In this mode
the 8051 UART serial port operates in 9-bit mode with a variable
baud rate determined by either Timer 1 or Timer 2. The operation of the 9-bit UART is the same as for Mode 2 but the baud
rate can be varied as for Mode 1.
In all four modes, transmission is initiated by any instruction that
uses SBUF as a destination register. Reception is initiated in Mode 0
by the condition RI = 0 and REN = 1. Reception is initiated in
the other modes by the incoming start bit if REN = 1.
UART Serial Port Baud Rate Generation
Mode 0 Baud Rate Generation
The baud rate in Mode 0 is fixed:
Mode 0 Baud Rate = (Core Clock Frequency1/12)
NOTE
1
In these descriptions Core Clock Frequency refers to the core clock frequency
selected via the CD0–2 bits in the PLLCON SFR.
Mode 2 Baud Rate Generation
The baud rate in Mode 2 depends on the value of the SMOD bit
in the PCON SFR. If SMOD = 0, the baud rate is 1/64 of the core
clock. If SMOD = 1, the baud rate is 1/32 of the core clock:
Mode 2 Baud Rate = (2SMOD/64) ∞ (Core Clock Frequency)
Mode 1 and 3 Baud Rate Generation
Traditionally the baud rates in Modes 1 and 3 are determined by
the overflow rate in Timer 1 or Timer 2, or both (one for
transmit and the other for receive).
On the ADuC834 however the baud rate can also be generated
via a seperate baud rate generator to achieve higher baud rates
and allow all three be used for other functions.
–61–
PRELIMINARY TECHNICAL DATA
ADuC834
BAUD RATE GENERATION USING TIMER 1 AND TIMER 2
Timer 2 Generated Baud Rates
Timer 1 Generated Baud Rates
Baud rates can also be generated using Timer 2. Using Timer 2
is similar to using Timer 1 in that the timer must overflow 16 times
before a bit is transmitted/received. Because Timer 2 has a 16-bit
autoreload mode a wider range of baud rates is possible using
Timer 2.
When Timer 1 is used as the baud rate generator, the baud
rates in Modes 1 and 3 are determined by the Timer 1 overflow
rate and the value of SMOD as follows:
Modes 1 and 3 Baud Rate =
(2SMOD/32) × (Timer 1 Overflow Rate)
Modes 1 and 3 Baud Rate = (1/16) × (Timer 2 Overflow Rate)
The Timer 1 interrupt should be disabled in this application.
The Timer itself can be configured for either timer or counter
operation, and in any of its three running modes. In the most
typical application, it is configured for timer operation, in the
autoreload mode (high nibble of TMOD = 0100Binary). In that
case, the baud rate is given by the formula:
Therefore, when Timer 2 is used to generate baud rates, the timer
increments every two clock cycles and not every core machine
cycle as before. Hence, it increments six times faster than Timer
1, and therefore baud rates six times faster are possible. Because
Timer 2 has 16-bit autoreload capability, very low baud rates
are still possible.
Modes 1 and 3 Baud Rate =
(2SMOD/32) × (Core Clock/(12 × [256-TH1]))
Timer 2 is selected as the baud rate generator by setting the TCLK
and/or RCLK in T2CON. The baud rates for transmit and receive
can be simultaneously different. Setting RCLK and/or TCLK puts
Timer 2 into its baud rate generator mode as shown in Figure 52.
A very low baud rate can also be achieved with Timer 1 by leaving
the Timer 1 interrupt enabled, and configuring the timer to run
as a 16-bit timer (high nibble of TMOD = 0100Binary), and
using the Timer 1 interrupt to do a 16-bit software reload. Table
XXXI below, shows some commonly-used baud rates and
how they might be calculated from a core clock frequency of
1.5728 MHz and 12.58 MHz using timer 1. Generally speaking, a 5% error is tolerable using asynchronous (start/stop)
communications.
In this case, the baud rate is given by the formula:
Modes 1 and 3 Baud Rate
= (Core Clk)/(32 × [65536 – (RCAP2H, RCAP2L)])
Table XXXII shows some commonly used baud rates and how they
might be calculated from a core clock frequency of 1.5728 MHz
and 12.5829 MHz using timer 2.
Table XXXII. Commonly used Baud Rates, Timer 2
Table XXXI. Commonly-Used Baud Rates, Timer 1
Ideal
Baud
Core
CLK
SMOD
Value
TH1-Reload
Value
Actual
Baud
%
Error
9600
1600
1200
1200
12.58
12.58
12.58
1.57
1
1
1
1
–7 (F9h)
–27 (E5h)
–55 (C9h)
–7 (F9h)
9362
1627
1192
1170
2.5
1.1
0.7
2.5
Ideal
Baud
Core
CLK
RCAP2H
Value
RCAP2L
Value
Actual
Baud
%
Error
19200
9600
1600
1200
9600
1600
1200
12.58
12.58
12.58
12.58
1.57
1.57
1.57
–1
–1
–1
–2
–1
–1
–1
–20 (ECh)
–41 (D7h)
–164 (5Ch)
–72 (B8h)
–5 (FBh)
–20 (ECh)
–41 (D7h)
19661
9591
2398
1199
9830
1658
1199
2.4
0.1
0.1
0.1
2.4
2.4
0.1
(FFh)
(FFh)
(FFh)
(FEh)
(FFh)
(FFh)
(FFh)
TIM E R 1
O V ERFLO W
2
NO TE : O S C. FRE Q . IS DIV IDE D B Y 2, NO T 12.
0
CO RE
CLK *
2
S M OD
C/T 2 = 0
TL2
(8-B ITS )
T2
P IN
1
CO NTR O L
TH2
(8-B ITS )
TIM E R 2
O V ERFLO W
1
0
RCLK
C/T 2 = 1
16
1
TR2
RX
CLO CK
0
TCLK
RE LO A D
16
RCA P 2L
TX
CLO CK
RCA P 2H
NO TE A V A ILA BILITY OF A DDITIO NA L
E X TE RNA L INTE RRUP T
EXF
2
T2E X
P IN
TIM E R 2
INTE RRUP T
CO NTR O L
TRA NS ITION
DE TE CTO R
E X E N2
* THE CORE CLO CK IS THE O UTP UT OF THE P LL A S DE S CRIB E D ON P A GE 46
Figure 52. Timer 2, UART Baud Rates
–62–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
BAUD RATE GENERATION USING TIMER 3
The T3FD register writes to the fractional divider. This register
can be calculated using the following equation:
The ADuC824 and the ADuC816 can only achieve PC baud
rates up to 57,600baud. They cannot achieve a baud rate of
115,200. To address this problem the ADuC834 has added a
fourth timer specifically for generating high accuracy baudrates.
Timer 3 can be used instead of timer1 or timer2 for generating
the baudrate, allowing a much wider range of baud rates to be
accurately obtained. This also frees up the other three timers
allowing them to be used for different applications.
As shown in figure 53 timer 3 uses a programmable fractional
divider to divide the core clock down into a wide range of
clocks. These are then passed through a seven stage binary
divider. Two SFRs (T3CON and T3FD) are required to use
the Timer 3 baud rate generator.
T3FD = (2 x fVCO) / (Baud Rate x 2CD x 2DIV) - 64
where DIV is the 3 LSBs of the T3CON SFR.
NOTE: The value of DIV should be chosen to ensure that:
0 ≤ T3FD < 64
or
64 ≤ (2 x fVCO) / (Baud Rate x 2CD x 2DIV) < 128
e.g. to get a baud rate of 115200 while operating from the
maximum core frequency (CD=0) we get:
T3FD = 218.45/2DIV - 64
therefore choose DIV = 1
T3CON is the baud rate control SFR, allowing timer 3 to be
used to set up the UART baud rate, and setting up the binary
divider (DIV). T3FD is the fractional divider ratio required to
achieve the required baudrate.
FRA CTIO NA L
DIVIDE R
TIM ER 1/TIM ER 2
RX CLO CK (FIG 52)
2 DIV
1
0
1
0
= 109.22 -64 = 45.22 => 2Dh
DIV2-0
= 1 (=>T3CON = 81h )
The actual baudrate can then be calculated using the following
formula:
TIM ER 1/TIM ER 2
TX CLOCK (FIG 52)
CO RE
CLK *
T3FD
Baud Rate = (2 x fVCO) / ((T3FD + 64) x 2CD x 2DIV)
(1 + T3FD/64)
RX CLO CK
Table XXXIV. Commonly used Baud Rates using Timer 3
32
T3 RX /TX
CLO CK
T3E N
TX CLOCK
Ideal
Baud
CD
DIV
T3CON
T3FD
Error
230400 0
0
80h
2Dh
0.2%
115200 0
115200 1
1
0
81h
80h
2Dh
2Dh
0.2%
0.2%
57600
57600
57600
0
1
2
2
1
0
82h
81h
80h
2Dh
2Dh
2Dh
0.2%
0.2%
0.2%
38400
38400
38400
38400
0
1
2
3
3
2
1
0
83h
82h
81h
80h
12h
12h
12h
12h
0.1%
0.1%
0.1%
0.1%
19200
19200
19200
19200
19200
0
1
2
3
4
4
3
2
1
0
84h
83h
82h
81h
80h
12h
12h
12h
12h
12h
0.1%
0.1%
0.1%
0.1%
0.1%
9600
9600
9600
9600
9600
9600
0
1
2
3
4
5
5
4
3
2
1
0
85h
84h
83h
82h
81h
80h
12h
12h
12h
12h
12h
12h
0.1%
0.1%
0.1%
0.1%
0.1%
0.1%
* THE CORE CLOCK IS THE OUTPUT OF THE P LL A S DE S CRIB E D O N PA G E 46.
Figure 53. Timer 3, UART Baud Rates
Table XXXIII. T3CON SFR Bit Designations
Bit
Name
Description
7
T3EN
Set to enable Timer 3 to generate
the baud rate. When set
PCON.7, T2CON.4 and
T2CON.5 are ignored.
Cleared to let the baud rate be
generated as per a standard
8052.
Binary Divider Factor
DIV2 DIV1 DIV0 Bin Divider
0
0
0
1
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
6
5
4
3
2
1
0
DIV2
DIV1
DIV0
REV. PrC (12 March 2002)
–63–
PRELIMINARY TECHNICAL DATA
ADuC834
INTERRUPT SYSTEM
The ADuC834 provides a total of eleven interrupt sources with two priority levels. The control and configuration of the interrupt
system is carried out through three Interrupt-related SFRs. These are the IE (Interrupt Enable) register, the IP (Interrupt Priority
Register) and the IEIP2 (secondary interrupt enable/priority SFR) registers. There bit definifitions are given in the tables below.
IE:
Interrupt Enable Register
SFR Address
Power-On Default Value
Bit Addressable
A8H
00H
Yes
Bit
Name
Description
7
6
5
4
3
2
1
0
EA
EADC
ET2
ES
ET1
EX1
ET0
EX0
Written by User to Enable ‘1’ or Disable ‘0’ All Interrupt Sources
Written by User to Enable ‘1’ or Disable ‘0’ ADC Interrupt
Written by User to Enable ‘1’ or Disable ‘0’ Timer 2 Interrupt
Written by User to Enable ‘1’ or Disable ‘0’ UART Serial Port Interrupt
Written by User to Enable ‘1’ or Disable ‘0’ Timer 1 Interrupt
Written by User to Enable ‘1’ or Disable ‘0’ External Interrupt 1
Written by User to Enable ‘1’ or Disable ‘0’ Timer 0 Interrupt
Written by User to Enable ‘1’ or Disable ‘0’ External Interrupt 0
Table XXXV. IE SFR Bit Designations
IP:
Interrupt Priority Register
SFR Address
Power-On Default Value
Bit Addressable
B8H
00H
Yes
Bit
Name
Description
7
6
5
4
3
2
1
0
--PADC
PT2
PS
PT1
PX1
PT0
PX0
Reserved for Future Use.
Written by User to Select ADC Interrupt Priority (‘1’ = High; ‘0’ = Low)
Written by User to Select Timer 2 Interrupt Priority (‘1’ = High; ‘0’ = Low)
Written by User to Select UART Serial Port Interrupt Priority (‘1’ = High; ‘0’ = Low)
Written by User to Select Timer 1 Interrupt Priority (‘1’ = High; ‘0’ = Low)
Written by User to Select External Interrupt 1 Priority (‘1’ = High; ‘0’ = Low)
Written by User to Select Timer 0 Interrupt Priority (‘1’ = High; ‘0’ = Low)
Written by User to Select External Interrupt 0 Priority (‘1’ = High; ‘0’ = Low)
Table XXXVI. IP SFR Bit Designations
IEIP2:
Secondary Interrupt Enable and Priority Register
SFR Address
Power-On Default Value
Bit Addressable
A9H
A0H
No
Bit
Name
Description
7
6
5
4
3
2
1
0
--PTI
PPSM
PSI
--ETI
EPSM
ESI
Reserved for Future Use.
Written by User to Select TIC Interrupt Priority (‘1’ = High; ‘0’ = Low).
Written by User to Select Power Supply Monitor Interrupt Priority (‘1’ = High; ‘0’ = Low).
Written by User to Select SPI Serial Port Interrupt Priority (‘1’ = High; ‘0’ = Low).
Reserved, This Bit Must Be ‘0.’
Written by User to Enable ‘1’ or Disable ‘0’ TIC Interrupt.
Written by User to Enable ‘1’ or Disable ‘0’ Power Supply Monitor Interrupt.
Written by User to Enable ‘1’ or Disable ‘0’ SPI Serial Port Interrupt.
Table XXXVII. IEIP2 SFR Bit Designations
–64–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
Interrupt Priority
Interrupt Vectors
The Interrupt Enable registers are written by the user to enable
individual interrupt sources, while the Interrupt Priority registers
allow the user to select one of two priority levels for each interrupt. An interrupt of a high priority may interrupt the service
routine of a low priority interrupt, and if two interrupts of different priority occur at the same time, the higher level interrupt
will be serviced first. An interrupt cannot be interrupted by
another interrupt of the same priority level. If two interrupts of
the same priority level occur simultaneously, a polling sequence is used to determine which interrupt is serviced first.
The polling sequence is shown in Table XXXVIII.
When an interrupt occurs the program counter is pushed onto
the stack and the corresponding interrupt vector address is loaded
into the program counter. The interrupt vector addresses are
shown in Table XXXIX.
Table XXXVIII. Priority within an Interrupt Level
Source
Priority
Description
PSMI
WDS
IE0
RDY0/RDY1
TF0
IE1
TF1
ISPI
RI + TI
TF2 + EXF2
TII
1 (Highest)
2
3
4
5
6
7
8
9
10
11 (Lowest)
Power Supply Monitor Interrupt
Watchdog Interrupt
External Interrupt 0
ADC Interrupt
Timer/Counter 0 Interrupt
External Interrupt 1
Timer/Counter 1 Interrupt
SPI Interrupt
Serial Interrupt
Timer/Counter 2 Interrupt
Time Interval Counter Interrupt
REV. PrC (12 March 2002)
Table XXXiX. Interrupt Vector Addresses
Source
Vector Address
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
RDY0/RDY1 (ADC)
ISPI
PSMI
TII
WDS (WDIR = 1)1
0003 Hex
000B Hex
0013 Hex
001B Hex
0023 Hex
002B Hex
0033 Hex
003B Hex
0043 Hex
0053 Hex
005B Hex
Notes
1
The watchdog can be configured to generate an interrupt instead of a reset
when it times out. This is used for logging errors or to examine the internal
status of the microcontroller core to understand, from a software debug
point of view, why a watchdog timeout occurred. The watchdog interrupt is
slightly different from the normal interrupts in that its priority level is always
set to 1 and it is not possible to disable the interrupt via the global disable
bit (EA) in the IE SFR. This is done to ensure that the interrupt will always
be responded to if a watchdog timeout occurs. The watchdog will only
produce an interrupt if the watchdog timeout is greater than zero.
–65–
.
PRELIMINARY TECHNICAL DATA
ADuC834
ADUC834 HARDWARE DESIGN CONSIDERATIONS
Though both external program memory and external data
memory are accessed by some of the same pins, the two are
completely independent of each other from a software point
of view. For example, the chip can read/write external data
memory while executing from external program memory.
This section outlines some of the key hardware design considerations that must be addressed when integrating the
ADuC834 into any hardware system.
External Memory Interface
In addition to its internal program and data memories, the
ADuC834 can access up to 64 Kbytes of external program
memory (ROM/PROM/etc.) and up to 16 Mbytes of external
data memory (SRAM).
Figure 55 shows a hardware configuration for accessing up
to 64 Kbytes of external RAM. This interface is standard to any
8051 compatible MCU.
ADuC83 4
S RA M
D0›D7
(DA TA)
P0
To select from which code space (internal or external program memory) to begin executing instructions, tie the EA
(external access) pin high or low, respectively. When EA is high
(pulled up to VDD), user program execution will start at address 0 of the internal 62 Kbytes Flash/EE code space. When EA
is low (tied to ground) user program execution will start at address 0 of the external code space. When executing from internal
code space accesses to the program space above F7FF hex (62K)
will be read as NOP instructions.
LATCH
A 0›A 7
A LE
Note that a second very important function of the EA pin is
described in the Single Pin Emulation Mode section of this
data sheet.
P2
A 8›A 15
RD
OE
WR
WE
Figure 55. External Data Memory Interface (64 K Address
Space)
External program memory (if used) must be connected to
the ADuC834 as illustrated in Figure 54. Note that 16 I/O
lines (Ports 0 and 2) are dedicated to bus functions during
external program memory fetches. Port 0 (P0) serves as a
multiplexed address/data bus. It emits the low byte of the
program counter (PCL) as an address, and then goes into a
float state awaiting the arrival of the code byte from the program
memory. During the time that the low byte of the program
counter is valid on P0, the signal ALE (Address Latch Enable)
clocks this byte into an address latch. Meanwhile, Port 2 (P2)
emits the high byte of the program counter (PCH), then PSEN
strobes the EPROM and the code byte is read into the
ADuC834.
If access to more than 64 Kbytes of RAM is desired, a feature unique to the MicroConverter allows addressing up to
16 Mbytes of external RAM simply by adding an additional latch
as illustrated in Figure 56.
ADuC83 4
S RA M
D0›D7
(DA TA)
P0
LATCH
A 0›A 7
A LE
A 8›A 15
P2
LATCH
A 16›A23
ADuC83 4
E P RO M
D0›D7
(INS TRUCTIO N)
P0
LATCH
A 0›A 7
PSEN
A 8›A 15
OE
Figure 54. External Program Memory Interface
Note that program memory addresses are always 16 bits wide,
even in cases where the actual amount of program memory used
is less than 64 Kbytes. External program execution sacrifices
two of the 8-bit ports (P0 and P2) to the function of addressing
the program memory. While executing from external program
memory, Ports 0 and 2 can be used simultaneously for read/
write access to external data memory, but not for general-purpose I/O.
OE
WE
Figure 56. External Data Memory Interface (16 M Bytes
Address Space)
A LE
P2
RD
WR
In either implementation, Port 0 (P0) serves as a multiplexed address/data bus. It emits the low byte of the data pointer
(DPL) as an address, which is latched by a pulse of ALE prior to
data being placed on the bus by the ADuC834 (write operation) or the SRAM (read operation). Port 2 (P2) provides the
data pointer page byte (DPP) to be latched by ALE, followed by the data pointer high byte (DPH). If no latch is
connected to P2, DPP is ignored by the SRAM, and the 8051
standard of 64 Kbyte external data memory access is maintained.
Detailed timing diagrams of external program and data
memory read and write access can be found in the timing
specification sections of this data sheet.
–66–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
Power Supplies
Power-On Reset Operation
The ADuC834’s operational power supply voltage range is
2.7 V to 5.25 V. Although the guaranteed data sheet specifications are given only for power supplies within 2.7 V to 3.6 V or
+5% of the nominal 5 V level, the chip will function equally
well at any power supply level between 2.7 V and 5.25 V.
An internal POR (power-on reset) is implemented on the
ADuC834. For DVDD below 2.63V the internal POR will hold the
ADuC834 in reset. As DVDD rises above 2.63V an internal timer
will timeout for approx 128ms before the part is released from
reset. The user must ensure that the power supply must have
reached at least a 2.7 V level by this time.
Separate analog and digital power supply pins (AVDD and
DVDD respectively) allow AVDD to be kept relatively free of
noisy digital signals often present on the system DVDD line. In
this mode the part can also operate with split supplies; that is,
using different voltage supply levels for each supply. For example, this means that the system can be designed to operate
with a DVDD voltage level of 3 V while the AVDD level can be at
5 V or vice-versa if required. A typical split supply configuration
is show in Figure 57.
A NA LOG S UP P LY
DIGITA L S UP P LY
10 ␮F
10 ␮F
+
›
+
›
ADuC834
20
34
DV DD
A V DD
5
0.1 ␮F
48
0.1 ␮F
21
35
DG N D
A GND
6
47
Figure 57. External Dual Supply Connections
As an alternative to providing two separate power supplies,
AV DD can be kept quiet by placing a small series resistor and/or
ferrite bead between it and DVDD, and then decoupling AVDD
separately to ground. An example of this configuration is shown
in Figure 58. With this configuration other analog circuitry
(such as op-amps, voltage reference, etc.) can be powered from
the AVDD supply line as well.
DIGITA L S UP P LY
+
›
10 ␮F
BEAD
1.6⍀
10 ␮F
ADuC834
20
34
DV DD
A V DD
5
A G ND
6
0.1 ␮F
48
0.1 ␮F
21
35
Power Consumption
The “CORE” values given on the spec pages represent the current drawn by DVDD, while the rest (“ADC”, and “DAC”) are
pulled by the AVDD pin and can be disabled in software when
not in use. The other on-chip peripherals (watchdog timer,
power supply monitor, etc.) consume negligible current and are
therefore lumped in with the “CORE” operating current here.
Of course, the user must add any currents sourced by the parallel and serial I/O pins, and that sourced by the DAC, in order
to determine the total current needed at the ADuC834’s supply pins. Also, current draw from the DVDD supply will increase
by approximately 5 mA during Flash/EE erase and program
cycles
Power-Saving Modes
Setting the Idle and Power-Down Mode bits, PCON.0 and
PCON.1 respectively, in the PCON SFR described in Table II,
allows the chip to be switched from normal mode into idle mode,
and also into full power-down mode.
In idle mode, the oscillator continues to run, but the core clock
generated from the PLL is halted. The on-chip peripherals continue to receive the clock, and remain functional. The CPU status
is preserved with the stack pointer, program counter, and all other
internal registers maintain their data during idle mode. Port
pins and DAC output pins also retain their states, and ALE and
PSEN outputs go high in this mode. The chip will recover from
idle mode upon receiving any enabled interrupt, or on receiving
a hardware reset.
In power-down mode, both the PLL and the clock to the core
are stopped. The on-chip oscillator can be halted or can continue
to oscillate depending on the state of the oscillator power-down
bit (OSC_PD) in the PLLCON SFR. The TIC, being driven
directly from the oscillator, can also be enabled during powerdown. All other on-chip peripherals however, are shut down.
Port pins retain their logic levels in this mode, but the DAC output
goes to a high-impedance state (three-state) while ALE and
PSEN outputs are held low. During full power-down mode,
the ADuC834 typically consumes a total of 15 µA. There are
five ways of terminating power-down mode:
DGN D
47
Figure 58. External Single Supply Connections
Notice that in both Figure 57 and Figure 58, a large value (10 µF)
reservoir capacitor sits on DVDD and a separate 10 µF capacitor
sits on AV DD. Also, local small-value (0.1 µF) capacitors are
located at each VDD pin of the chip. As per standard design practice, be sure to include all of these capacitors, and ensure
the smaller capacitors are closest to each AVDD pin with trace
lengths as short as possible. Connect the ground terminal of each
of these capacitors directly to the underlying ground plane.
Finally, it should also be noticed that, at all times, the analog
and digital ground pins on the ADuC834 should be referenced
to the same system ground reference point.
REV. PrC (12 March 2002)
Asserting the RESET pin (#15)
Returns to normal mode all registers are set to their default state
and program execution starts at the reset vector once the Reset
pin is de-asserted.
Cycling Power
All registers are set to their default state and program execution
starts at the reset vector approximately 128ms later.
Time Interval Counter (TIC) Interrupt
Power-down mode is terminated and the CPU services the TIC
interrupt. The RETI at the end of the TIC ISR will return the
core to the instruction after that which enabled power down.
SPI Interrupt
Power-down mode is terminated and the CPU services the SPI
interrupt. The RETI at the end of the ISR will return the core
to the instruction after that which enabled power down. It
–67–
PRELIMINARY TECHNICAL DATA
ADuC834
should be noted that the SPI power down interrupt enable bit
(SERIPD) in the PCON SFR must first be set to allow this
mode of operation.
INT0 Interrupt
Power-down mode is terminated and the CPU services the
INT0 interrupt. The RETI at the end of the ISR will return the
core to the instruction after that which enabled power-down. It
should be noted that the INT0 power-down interrupt enable bit
(INT0PD) in the PCON SFR must first be set to allow this
mode of operation.
Grounding and Board Layout Recommendations
As with all high resolution data converters, special attention must
be paid to grounding and PC board layout of ADuC834-based
designs in order to achieve optimum performance from the ADCs
and DAC.
Although the ADuC834 has separate pins for analog and digital
ground (AGND and DGND), the user must not tie these to two
separate ground planes unless the two ground planes are connected together very close to the ADuC834, as illustrated in the
simplified example of Figure 59a. In systems where digital and
analog ground planes are connected together somewhere else
(at the system’s power supply for example), they cannot be connected again near the ADuC834 since a ground loop would result.
In these cases, tie the ADuC834’s AGND and DGND pins all
to the analog ground plane, as illustrated in Figure 59b. In systems
with only one ground plane, ensure that the digital and analog
components are physically separated onto separate halves of the
board such that digital return currents do not flow near analog
circuitry and vice versa. The ADuC834 can then be placed between
the digital and analog sections, as illustrated in Figure 59c.
A
A GND
B
DG N D
A GND
C
DG N D
PLACE A NA LOG
CO MP O NE NTS HE RE
ADuC834 System Self-Identification
In some hardware designs it may be an advantage for the
software running on the ADuC834 target to identify the host
MicroConverter. For example, code running on the ADuC834
may also be used with the ADuC824 or the ADuC816 but is
required to operate differently.
The CHIPID SFR is a read-only register located at SFR address C2 hex. The upper nibble of this SFR is set to 2Xhex
to designate an ADuC834.
As shown in the typical external crystal connection diagram
in Figure 60, two internal 12 pF capacitors are provided on-chip.
These are connected internally, directly to the XTAL1 and
XTAL2 pins and the total input capacitances at both pins is
detailed in the specification section of this data sheet. The
value of the total load capacitance required for the external crystal
should be the value recommended by the crystal manufacturer
for use with that specific crystal. In many cases, because of the
on-chip capacitors, additional external load capacitors will not be
required.
PLACE DIGITA L
CO MP O NE NTS
HE RE
PLACE A NA LOG
CO MP O NE NTS
HE RE
If the user plans to connect fast logic signals (rise/fall time <
5 ns) to any of the ADuC834’s digital inputs, add a series
resistor to each relevant line to keep rise and fall times longer
than 5 ns at the ADuC834 input pins. A value of 100Ω or 200Ω
is usually sufficient to prevent high-speed signals from coupling
capacitively into the ADuC834 and affecting the accuracy of
ADC conversions.
Clock Oscillator
As described earlier, the core clock frequency for the
ADuC834 is generated from an on-chip PLL that locks onto
a multiple (384 times) of 32.768 kHz. The latter is generated
from an internal clock oscillator. To use the internal clock
oscillator, connect a 32.768 kHz parallel resonant crystal
between XTAL1 and XTAL2 pins (32 and 33) as shown in
Figure 60.
PLACE DIGITA L
CO MP O NE NTS HE RE
PLACE ANALOG CO MP ONE NTS HE RE
back to ground. Make sure the return paths for all currents
are as close as possible to the paths the currents took to reach
their destinations. For example, do not power components
on the analog side of Figure 59b with DVDD since that
would force return currents from DVDD to flow through
AGND. Also, try to avoid digital currents flowing under analog
circuitry, which could happen if the user placed a noisy digital chip on the left half of the board in Figure 59c.
Whenever possible, avoid large discontinuities in the ground
plane(s) (such as are formed by a long trace on the same
layer), since they force return signals to travel a longer path.
And of course, make all connections to the ground plane directly, with little or no trace separating the pin from its via to
ground.
ADuC8 34
PLACE DIGITA L CO MP ONE NTS
HE RE
X TA L1
12pF
32.768kHz
G ND
X TA L2
Figure 59. System Grounding Schemes
In all of these scenarios, and in more complicated real-life applications, keep in mind the flow of current from the supplies and
12pF
TO INTE RNAL
P LL
Figure 60. External Parallel Resonant Crystal Connections
–68–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
OTHER HARDWARE CONSIDERATIONS
the standard connector that comes with the single-pin emulator
available from Accutron Limited (www.accutron.com), use a 2pin 0.1-inch pitch "Friction Lock" header from Molex
(www.molex.com) such as their part number 22-27-2021. Be
sure to observe the polarity of this header. As
represented in Figure 61, when the Friction Lock tab is at
the right, the ground pin should be the lower of the two pins
(when viewed from the top).
To facilitate in-circuit programming, plus in-circuit debug
and emulation options, users will want to implement some
simple connection points in their hardware that will allow easy
access to download, debug, and emulation modes.
In-Circuit Serial Download Access
Nearly all ADuC834 designs will want to take advantage of
the in-circuit reprogrammability of the chip. This is accomplished
by a connection to the ADuC834’s UART, which requires an
external RS-232 chip for level translation if downloading code
from a PC. Basic configuration of an RS-232 connection is
illustrated in Figure 61 with a simple ADM202-based circuit.
If users would rather not design an RS-232 chip onto a board,
refer to the application note “uC006–A 4-Wire UART-to-PC
Interface”1 for a simple (and zero-cost-per-board) method of
gaining in-circuit serial download access to the ADuC834.
Enhanced-Hooks Emulation Mode
ADuC834 also supports enhanced-hooks emulation mode. An
enhanced-hooks-based emulator is available from Metalink Corporation (www.metaice.com). No special hardware support for
these emulators needs to be designed onto the board since
these are "pod-style" emulators where users must replace the
chip on their board with a header device that the emulator pod
plugs into. The only hardware concern is then one of determining
if adequate space is available for the emulator pod to fit into the
system enclosure.
Note
1
Application note uC006 is available at www.analog.com/microconverter
Typical System Configuration
In addition to the basic UART connections, users will also
need a way to trigger the chip into download mode. This is
accomplished via a 1 kΩ pull-down resistor that can be
jumpered onto the PSEN pin, as shown in Figure 61. To get the
ADuC834 into download mode, simply connect this jumper
and power-cycle the device (or manually reset the device, if a
manual reset button is available) and it will be ready to receive
a new program serially. With the jumper removed, the device
will come up in normal mode (and run the program) whenever
power is cycled or RESET is toggled.
A typical ADuC834 configuration is shown in Figure 61. It
summarizes some of the hardware considerations discussed
in the previous paragraphs.
Figure 61 also includes connections for a typical analog measurement application of the ADuC834, namely an interface
to an RTD (Resistive Temperature Device). The arrangement
shown is commonly referred to as a 4-wire RTD configuration.
Note that PSEN is normally an output (as described in the
External Memory Interface section) and it is sampled as an
input only on the falling edge of RESET (i.e., at power-up or
upon an external manual reset). Note also that if any external circuitry unintentionally pulls PSEN low during power-up
or reset events, it could cause the chip to enter download mode
and therefore fail to begin user code execution as it should. To
prevent this, ensure that no external signals are capable of
pulling the PSEN pin low, except for the external PSEN
jumper itself.
Embedded Serial Port Debugger
From a hardware perspective, entry to serial port debug mode
is identical to the serial download entry sequence described
above. In fact, both serial download and serial port debug
modes can be thought of as essentially one mode of operation
used in two different ways.
Here, the on-chip excitation current sources are enabled to
excite the sensor. An external differential reference voltage is
generated by the current sourced through resistor R1. This current also flows directly through the RTD, which generates a
differential voltage directly proportional to temperature. This
differential voltage is routed directly to the positive and negative inputs of the primary ADC (AIN1, AIN2 respectively). A
second external resistor, R2, is used to ensure that absolute
analog input voltage on the negative input to the primary
ADC stays within that specified for the ADuC834, i.e.,
AGND + 100 mV.
It should also be noted that variations in the excitation current
do not affect the measurement system as the input voltage from
the RTD and reference voltage across R1 vary ratiometrically
with the excitation current. Resistor R1 must, however, have
a low temperature coefficient to avoid errors in the reference
voltage over temperature.
Note that the serial port debugger is fully contained on the
ADuC834 device, (unlike "ROM monitor" type debuggers)
and therefore no external memory is needed to enable insystem debug sessions.
Single-Pin Emulation Mode
Also built into the ADuC834 is a dedicated controller for
single-pin in-circuit emulation (ICE) using standard production ADuC834 devices. In this mode, emulation access is
gained by connection to a single pin, the EA pin. Normally, this
pin is hard-wired either high or low to select execution from
internal or external program memory space, as described
earlier. To enable single-pin emulation mode, however, users
will need to pull the EA pin high through a 1 kΩ resistor as
shown in Figure 61. The emulator will then connect to the 2pin header also shown in Figure 61. To be compatible with
REV. PrC (12 March 2002)
–69–
PRELIMINARY TECHNICAL DATA
ADuC834
DO W NLOA D/D E B UG
E NA B LE JUM P E R
(NO RM A LLY O P E N)
1k ⍀
DV DD
DV DD
1k ⍀
46
45
44
43
42
41
2-P IN HE A DE R FO R
E M ULA TION A CCE S S
(NO RM A LLY O P E N)
40
EA
47
PSEN
50
48
DV DD
51
49
DG N D
52
39
38
P 1.2/I E XC 1/DA C
200 ␮A /4 00 ␮A
E XC IT A T IO N
CU R RE N T
A V DD
37
P 1.3/A IN5/DA C
36
A V DD
A IN +
A G ND
RTD
A IN ›
A D uC 834
RE FIN›
V RE F +
DV DD 34
X TA L2 33
X TA L1 32
RE FIN+
R R EF
5.6k ⍀
DV DD
DG N D 35
P 1.4/A IN1
31
P 1.5/A IN2
30
32.766kHz
DG N D
DV DD
RX D
TX D
RE S E T
29
28
27
NO T CO NNE CTE D IN THIS E X A M P LE
DV DD
DV DD
R S2 32 D O N G LE
A DM 202
C1+
V+
VCC
9-P IN D-S UB
FE MA LE
G ND
1
C1›
T1O UT
2
C2+
R1IN
3
C2›
R1O UT
4
V›
T1IN
5
T2O UT
T2IN
6
R2O UT
7
R2IN
8
9
Figure 61. Typical System Configuration
–70–
(12 March 2002) REV. PrC
PRELIMINARY TECHNICAL DATA
ADuC834
QUICKSTART DEVELOPMENT SYSTEM
The QuickStart Development System is a full featured, low cost development tool suite supporting the ADuC834. The system
consists of the following PC-based (Windows-compatible) hardware and software development tools.
Hardware:
ADuC834 Evaluation Board, and Serial Port Cable
Code Development:
8051 Assembler
Code Functionality:
ADSIM, Windows MicroConverter Code Simulator
In-Circuit Code Download:
Serial Downloader
In-Circuit Debugger/Emulator:
Serial Port/Single Pin Debugger/Emulator with Assembly and C Source debug
Misc. Other:
CD-ROM Documentation and Two
Additional Prototype Devices
Figures 62 shows the typical components of a QuickStart Development System while Figure 63 shows a typical debug session. A
brief description of some of the software tools’ components in the QuickStart Development System is given below.
Figure 62. Components of the QuickStart Dev System
Figure. 63. Typical Debug Session
Download- In Circuit Downloader
The Serial Downloader is a software program that allows the user to serially download an assembled program (Intel Hex format file)
to the on-chip program FLASH memory via the serial COM1 port on a standard PC. An Application Note (uC004) detailing
this serial download protocol is available from www.analog.com/microconverter.
DeBugger/Emulator — In-Circuit Debugger/Emulator
The Debugger/Emulator is a Windows application that allows the user to debug code execution on silicon using the MicroConverter
UART serial port or via a single pin to provide non-intrusive debug. The debugger provides access to all on-chip peripherals during a typical debug session, including single-step and multiple break-point code execution control. C source and Assembly level
debug are both possible with the emulator.
ADSIM—Windows Simulator
The Simulator is a Windows application that fully simulates the MicroConverter functionality including ADC and DAC peripherals. The simulator provides an easy-to-use, intuitive, interface to the MicroConverter functionality and integrates many
standard debug features; including multiple breakpoints, single stepping; and code execution trace capability. This tool can be
used both as a tutorial guide to the part as well as an efficient way to prove code functionality before moving to a hardware platform.
REV. PrC (12 March 2002)
–71–
ADuC834
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
52-Lead MQFP
(S-52)
0.557 (14.15)
0.094 (2.39)
0.537 (13.65)
0.398 (10.11)
0.084 (2.13)
0.390 (9.91)
0.037 (0.95)
0.026 (0.65)
52
40
39
1
0.012 (0.30)
13
14
0.006 (0.15)
0.537 (13.65)
0.398 (10.11)
TOP V IE W
(PINS D O W N )
0.390 (9.91)
0.557 (14.15)
P IN 1
S E ATING
P LA NE
27
26
0.008 (0.20)
0.006 (0.15)
0.082 (2.09)
0.078 (1.97)
0.0256
(0.65)
BSC
–72–
0.014 (0.35)
0.010 (0.25)
(12 March 2002) REV. PrC