ETC CXA1315M/P

CXA1315M/P
8-bit D/A Converter Supporting with I2C Bus
Description
The CXA1315M/P is developed as a 5-channel 8bit D/A converter supporting with I2C bus.
CXA1315M
16 pin SOP (Plastic)
CXA1315P
16 pin DIP (Plastic)
Features
• Serial control through I2C bus
• 5-channel 8-bit D/A converter
• Built-in 4general-purpose I/O ports (Digital I/O)
• I/O can be specified to respective ports independently
• Selection of 8 slave addresses possible through
address select pins (3 pins)
Applications
The IC, which cannot support I2C bus, can support
it by connecting its control pin to the CXA1315M/P.
Structure
Bipolar silicon monolithic lC
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VCC
12
V
• Operating temperature
Topr –20 to +75 °C
• Storage temperature
Tstg –65 to +150 °C
• Allowable power dissipation PD
960
mW
Operating Conditions
• Supply voltage
• Operating temperature
VCC
Topr
8.2 to 9.8
–20 to +75
V
°C
Purchase of Sony's I2C components conveys a license under the Philips I2C Patent Rights to use these components in
an I2C system, provided that the system conforms to the I2C Standard Specifications as defind by Philips.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E88Z45E26-PS
CXA1315M/P
Pin Configuration (Top View)
Slave address select pin
SCL
SDA
SAD2
SAD1
SAD0
SW3
SW2
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
DAC4
DAC3
DAC2
DAC1
DAC0
GND
SW1
16
SW0
SW I/O
VCC
I2C bus
SW I/O
DAC output
Block Diagram
SAD2 SAD1 SAD0
SW0 to 3
Open collector
Level
Conversion
Level
Conversion
LATCH
I2C BUS
SDA
Level
Conversion
SCL
I2C Decoder
Power On
Reset
VCC
LATCH
LATCH
LATCH
LATCH
LATCH
DAC
DAC
DAC
DAC
DAC
AMP
AMP
AMP
AMP
AMP
DAC4
DAC3
DAC2
DAC1
DAC0
VCC
REG
GND
–2–
CXA1315M/P
Pin Description
No.
Symbol
VCC
1
2
9
10
Description
Equivalent circuit
VCC
SW1
SW0
SW2
SW3
I/O pin for genera-purpose I/O port
VILmax: 1.5V
VIHmin: 3V
VOLmax: 0.4V
150
4.5k
14
SDA I/O pin for I2C bus
SDA
VCC
VCC
3
4
5
6
7
DAC4
DAC3
DAC2
DAC1
DAC0
8
GND
56
D/A converter output pin
20k
20k
GND pin
VCC
11
12
13
22k
SAD0
SAD1
SAD2
VCC
Slave address input pin
Input at positive logic
VILmax: 1.5V
VIHmin: 3V
150
4.5k
15
SCL
SCL input pin for I2C bus
16
VCC
Power supply pin
Electrical Characteristics
No.
1
Item
Circuit current
(Ta = 25°C, VCC = 9V)
Symbol
Test
circuit
Test conditions
lcc
1
DAC 0 to 4 = 127
Min. Typ. Max. Unit
8
11
0
15
mA
D/A Converter Block
2
Differential linearity
DLE
1
V (DAC0 to 4 = n + 1) – V (DAC0 to 4 = N)
× 128 – 1
V (DAC0 to 4 = 191) – V (DAC0 to 4 = 63)
n = 0 to 127
–1
3
Minimum output
voltage
Vmin
1
DAC 0 to 4 = 0
0.1
0.4 0.62
V
4
Maximum output
voltage
Vmax
1
DAC 0 to 4 = 255
8.3
8.5
8.9
V
5
Output current
Iout
2
Current that can be flowed from Pins 3 to 7
–1
+1
mA
6
Output impedance
Zo
2
DAC 0 to 4 = 127,
6
Ω
7
Repple rejection
Grip
3
DAC 0 to 4 = 127, REF = 0
Superimose 100Hz to VCC, 1Vp-p
–3–
V (–1mA) – V (1mA)
2mA
0
—
3
+1.1 LSB
–60 –40
dB
CXA1315M/P
SW, SAD Pins
No.
8
8
9
10
11
Item
Low level input
voItage
High level input
voltage
Low level input
current
High level input
current
Low level input
voltage
Symbol Test
circuit
Test conditions
Min. Typ. Max. Unit
VIL
4
Input voltage where ST0 to ST3 become "0"
—
—
1.5
V
VIH
4
Input voltage where ST0 to ST3 become "1" 3.0
—
—
V
IIL
4
lnput current when 0.4V is applied
–10
0
+10
µA
IIH
4
lnput current when 4.5V is applied
–10
0
+10
µA
VOL
5
SW 0 to 3 = 1,
Output voltage when 1mA flows in
0
0.2
0.4
V
I2C Bus Block Items (SDA, SCL)
No.
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Item
High level input voltage
Low level input voltage
High level input current
Symbol
VIH
VIL
IIH
Low level input current
Low level output voltage, at 3mA flow to SDA (Pin 14)
Maximum flowing current
lnput capacitance
Maximum clock frequency
Data change minimum waiting time
Data transfer start minimum waiting time
Low level clock pulse width
High level clock pulse width
Minimum start preparation waiting time
Minimum data hold time
Minimum data preparation time
Rise time
Fall time
Minimum stop preparation waiting time
IIL
VOL
IOL
CI
fSCL
tBUF
tHD; STA
tLOW
tHIGH
tSU; STA
tHD; DAT
tSU; DAT
tR
tF
tSU; STO
Min. Typ. Max.
3.0 — 5.0
— 1.5
0
— 10
—
— 10
—
— 0.4
0
— —
3
— 10
—
— 100
0
4.7 — —
4.0 — —
4.7 — —
4.0 — —
4.7 — —
— —
5
250 — —
—
1
—
— 300
—
4.7 — —
I2C bus load conditions: Pull-up resistance 4kΩ (Connected to +5V)
Load capacitance 200pF (Connected to GND)
I2C Bus Control Signal
SDA
tBUF
tHD; STA
tF
tR
SCL
tLOW
P
tHD; DAT
tHIGH
tSU; DAT
S tHD; STA
tSU; STA
Sr
–4–
tSU; STO
P
Unit
V
V
µA
µA
V
mA
pF
kHz
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
CXA1315M/P
Electrical Characteristics Measurement Circuit
Measurement Circuit 1
I2C BUS
0.022µ
+9V
Measurement Circuit 2
5V
I2C BUS
0.022µ
+9V
10µ
10µ
16
15
14
13
12
10
11
15
16
9
2
6
5
4
3
12
11
10
9
6
7
8
CXA1315M/P
CXA1315M/P
1
13
14
7
1
8
2
3
5
4
100p 100p 100p 100p 100p
100p 100p 100p 100p 100p
±1mA
Measurement Circuit 3
100Hz, 1Vp-p
0.022µ
+9V
Measurement Circuit 4
I2C BUS
+9V
I2C BUS
0.022µ
V4
10µ
10µ
16
15
14
13
12
11
10
16
9
15
14
2
6
5
4
3
12
11
10
9
6
7
8
CXA1315M/P
CXA1315M/P
1
13
7
1
8
2
3
4
5
100p 100p 100p 100p 100p
V4 =
Measurement Circuit 5
+9V
1mA
I2C BUS
0.022µ
10µ
16
15
14
13
12
11
10
9
6
7
8
CXA1315M/P
1
2
3
4
5
–5–
1.5V (No.8)
2.0V (No.9)
0.4V (No.10)
4.5V (No.11)
CXA1315M/P
Definition of I2C Bus Register
<SIave address>
MSB
0
LSB
1
0
0
SAD2 SAD1 SAD0
R/W
R/W 0: SLAVE RECEIVER
1: SLAVE TRANSMITTER
SAD0 to 2:11 to13 pin
0: "Low"
1: "High"
<Register table>
•
•
•
•
•
With the lC reset all registers are reset to "0"
∗: Not defined
x: Don't care
Sub address is auto incremented
lt can be used as a 6-bit D/A converter by setting the lower two bits of DAC0 to 4 registers to "0", but take
care that the max. voltage of DA output will lower about 100mV compared with the use of 8 bits.
Control Register
Sub address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
x x x x x 0 0 0
REF
∗
∗
∗
SW3
SW2
SW1
SW0
x x x x x 0 0 1
DAC0 (8)
x x x x x 0 1 0
DAC1 (8)
x x x x x 0 1 1
DAC2 (8)
x x x x x 1 0 0
DAC3 (8)
x x x x x 1 0 1
DAC4 (8)
Status Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PONRES
0
0
0
ST3
ST2
ST1
ST0
–6–
CXA1315M/P
<Registers> In brackets ( ) number of bits
REF
(1) : Switches D/A converter reference voltage
0: Standardizes the inner regulator
1: Standardizes voltage resistance divided from Vcc
SW0 to 3
(1) : Selects ON/OFF of Pins 1, 2, 9 and 10
(Each pin is the open collector output of NPN transistor)
0: OFF
1: ON
DAC0 to 4
(8) : Digital data input register of D/A converter
0: Output voltage turns to minimum
255: Output voItage turns to maximum
PONRES
(1) : Detects POWER ON RESET
0: Master passes from the bus and is reset to "0" after having read this status
1: Sets to "1" when power supply is turned on or when there has been a power dip
ST0 to 3
(1) : Detects and registers the voltage condition of Pins 1, 2, 9 and 10
0: 1.5V and below
1: 3.0V and above
Note) SW0 to 3 effective during "0"
I2C Bus Signal
There are 2 signals in I2C bus. SDA (Serial Data) and SCL (Serial Clock).
SDA is double-way.
• As SDA is bidirectional it has 3 state outputs, H, L and Hi-Z.
H
L
Hi-Z
L
• I2C transfer begins with Start Condition and ends with Stop Condition.
Start Condition S
Stop Condition P
SDA
SCL
–7–
CXA1315M/P
• I2C data write (Write from I2C controller to IC)
At "L" during write
MSB
MSB
LSB
Hi-Z
SDA
SCL
1
2
3
4
5
S
7
6
8
9
Address
MSB
Hi-Z
1
ACK
8
Sub Address
9
ACK
LSB
Hi-Z
1
8
Hi-Z
9
DATA (n)
1
ACK
8
9
DATA (n + 1)
Hi-Z
ACK
DATA (n + 2)
Hi-Z
∗ The number of data that can be
8
9
DATA
1
ACK
8
DATA
transferred at a time is confined to
units of 8-bit that can be set as required.
Sub Address is incremented automatically.
9
P
ACK
• I2C data read (Read from IC to I2C controller)
At "H" during read
Hi-Z
SDA
SCL
1
6
S
7
8
9
Address
1
7
ACK
DATA
• Read timing
MSB
LSB
IC output SDA
SCL
Read timing
9
1
2
ACK
3
4
5
DATA
6
7
8
9
ACK
∗ Data read is performed with SCL rise.
–8–
8
9
ACK
P
CXA1315M/P
Application Circuit
I2C BUS
10k
10k
0.022µ
+9V
General-purpose
output port
10µ
16
15
14
13
12
11
10
9
6
7
8
CXA1315M/P
1
2
3
4
5
10k
10k
2SC2785
10k
D/A converter output
10k
General-purpose
input port
2SC2785
10k
Slave address for 4Ch and 4Dh
10k
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Characteristics Diagram
D/A converter output temperture
characteristics (REF: 0)
D/A converter output temperture
characteristics (REF: 1)
0.1
0.1
VCC = 9V
Voltage variation at. 25°C [V]
Voltage variation at. 25°C [V]
VCC = 9V
Data: 0
Data: 0
Data: 128
0
Data: 128
Data: 255
Data: 0
Data: 128
Data: 128
0
Data: 255
Data: 0
Data: 255
Data: 255
–0.1
–0.1
–25
0
25
T [°C]
50
75
–25
–9–
0
25
T [°C]
50
75
CXA1315M/P
Package Outline
Unit: mm
CXA1315M
16PIN SOP (PLASTIC)
+ 0.4
1.85 – 0.15
+ 0.4
9.9 – 0.1
16
9
6.9
8
0.45 ± 0.1
+ 0.1
0.2 – 0.05
1.27
0.5 ± 0.2
1
7.9 ± 0.4
+ 0.3
5.3 – 0.1
0.15
+ 0.2
0.1 – 0.05
0.24 M
PACKAGE STRUCTURE
PACKAGE MATERIAL
SONY CODE
SOP-16P-L01
EIAJ CODE
SOP016-P-0300
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.2g
JEDEC CODE
16PIN SOP (PLASTIC)
+ 0.4
1.85 – 0.15
+ 0.4
9.9 – 0.1
16
9
6.9
8
0.45 ± 0.1
+ 0.1
0.2 – 0.05
1.27
0.5 ± 0.2
1
7.9 ± 0.4
+ 0.3
5.3 – 0.1
0.15
+ 0.2
0.1 – 0.05
0.24 M
PACKAGE STRUCTURE
PACKAGE MATERIAL
SONY CODE
SOP-16P-L01
EIAJ CODE
SOP016-P-0300
SOLDER PLATING
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.2g
JEDEC CODE
LEAD PLATING SPECIFICATIONS
ITEM
SPEC.
LEAD MATERIAL
COPPER ALLOY
SOLDER COMPOSITION
Sn-Bi Bi:1-4wt%
PLATING THICKNESS
5-18µm
EPOXY RESIN
LEAD TREATMENT
– 10 –
CXA1315M/P
Package Outline
Unit: mm
CXA1315P
+ 0.3
6.4 – 0.1
+ 0.4
19.2 – 0.1
+ 0.1
0.05
0.25 –
16PIN DIP (PLASTIC)
16
7.62
9
1
0˚ to 15˚
8
Two kinds of package surface:
1.All mat surface type.
3.0 MIN
0.5 MIN
+ 0.4
3.7 – 0.1
2.54
0.5 ± 0.1
2.All mirror surface type.
1.2 ± 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
DIP-16P-01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
DIP016-P-0300
LEAD MATERIAL
COPPER ALLOY
JEDEC CODE
Similar to MO-001-AE
PACKAGE MASS
1.0 g
SONY CODE
9
7.62
16
+ 0.3
6.4 – 0.1
+ 0.4
19.2 – 0.1
+ 0.1
0.05
0.25 –
16PIN DIP (PLASTIC)
1
0˚ to 15˚
8
Two kinds of package surface:
1.All mat surface type.
2.All mirror surface type.
3.0 MIN
0.5 MIN
+ 0.4
3.7 – 0.1
2.54
0.5 ± 0.1
1.2 ± 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
DIP-16P-01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
DIP016-P-0300
LEAD MATERIAL
COPPER ALLOY
JEDEC CODE
Similar to MO-001-AE
PACKAGE MASS
1.0 g
SONY CODE
LEAD PLATING SPECIFICATIONS
ITEM
SPEC.
LEAD MATERIAL
COPPER ALLOY
SOLDER COMPOSITION
Sn-Bi Bi:1-4wt%
PLATING THICKNESS
5-18µm
– 11 –
CXA1315M/P
Package Outline
Unit: mm
CXA1315P
6.35 ± 0.127
19.35 ± 0.5
16
+ 0.1
0.28 – 0.06
16PIN DIP (PLASTIC) 300mil
9
7.62
0˚ to 10˚
1
8
3.1 MIN
1.016
5.08 MAX
0.508 MIN
2.54 ± 0.254
0.457 ± 0.076
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
DIP-16P-191
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
DIP016-P-0300-AU
LEAD MATERIAL
COPPER
JEDEC CODE
MS-001-AA
PACKAGE MASS
1.0g
– 12 –
Sony Corporation