NCN6011 Low Power Level Shifter The NCN6011 is a level shifter analog circuit designed to translate the voltages between a SIM Card and an external micro controller. The device handles all the signals needed to control the data transaction between the external Card and the MPU. Features • • • • • • http://onsemi.com 2.7 to 6.0 V Input and/or Output Voltage Range 500 nA Quiescent Supply Current All Pins are Fully ESD Protected Supports 10 MHz Clock Provides a Logic I/O Enable Function Rx/Tx Communication Capability MARKING DIAGRAMS 14 1 Typical Applications • SIM/GSM/SMARTCARD Interface 1 10 Micro–10 DM SUFFIX CASE 846B 10 Vsupply VCC 6011 AYW 1 1 POWER MANAGEMENT UNIT VDD A WL, L Y WW, W C3 4.7 µF C1 6.8 F PIN CONNECTIONS C2 100 nF U1 NCN6011 1 P3 2 3 P2 4 P1 5 P0 I/O = Assembly Location = Wafer Lot = Year = Work Week GND GND VCC MPU or GSM Controller NCN 6011 ALYW TSSOP–14 DTB SUFFIX CASE 948G 14 10 SIM_IO GND 9 VDD SIM_VCC CLOCK SIM_CLK RESET SIM_RST I/O_ENABLE GND TSSOP–14 NA 1 14 NA I/O 2 13 SIM_IO VDD 3 12 SIM_VCC 8 CLOCK 4 11 SIM_CLK 7 RESET 5 10 SIM_RST 6 IO_ENABLE 6 9 GND NA 7 8 NA (Top View) GND Micro–10 IRQ 10 SIM_IO 5 9 SIM_VCC GND 1 VDD 2 CLOCK 3 8 SIM_CLK RESET 4 7 VPP VCC 2 3 CLK RST 4 8 7 I/O C4 C8 18 Swa GND Swb 17 I/O 1 GND IO_ENABLE 5 SIM_RST 6 GND (Top View) Figure 1. Typical Interface Application ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. Semiconductor Components Industries, LLC, 2001 June, 2001 – Rev. 2 1 Publication Order Number: NCN6011/D NCN6011 VDD 2 CLOCK 3 RESET 4 (3) (12) (4) (11) (5) (10) 9 SIM_VCC 8 SIM_CLK 7 SIM_RST 10 SIM_IO 6 GROUND GND VDD SIM_VCC 20 k 20 k I/O 1 (2) I/O DATA DATA (13) I/O GND I/O_ENABLE 5 (6) (9) GND NOTES: 1. Numbers in parenthesis adjacent to the pins are related to the TSSOP–14 package. 2. TSSOP–14 package Pins 1, 7, 8 and 14 are not connected. Figure 2. Block Diagram http://onsemi.com 2 NCN6011 ABBREVIATIONS CLOCK Input Logic Clock RESET Input Logic Reset VDD Interface Power Supply Input SIM_VCC Interface IC Card Power Supply Output SIM_CLK Interface IC Card Clock Output SIM_RST Interface IC Card Reset Output SIM_IO Interface IC Card I/O Signal Line Class A 5.0 V Smart Card Class B 3.0 V Smart Card PIN DESCRIPTIONS (Pin numbers in parenthesis are related to the TSSOP–14 package) (Pin numbers in bold are related to the MIcro–10 package) Pin Name Type (1) – NA 1 (2) I/O INPUT This pin is connected to an external microcontroller. A bidirectional level translator adapts the serial I/O signal between the smart card and the external controller. A built–in constant 20 kΩ typical resistor provides a high impedance state when not activated. 2 (3) VDD POWER This pin is connected to the system controller power supply and the input voltage can range from 2.7 to 6.0 V. 3 (4) CLOCK INPUT The clock signal, coming from the external controller, must have a Duty Cycle within the Min/Max limits defined by the specification (typically 50%). The built–in level shifter translates the input signal to the external SIM card voltage supply. 4 (5) RESET INPUT The RESET signal present at this pin is provided by the MPU. The internal level shifter translates the level according to the voltages applied to pin 3 and pin 12. 5 (6) IO_ENABLE INPUT This logic input pin switches the active pull down MOS connected across SIM_IO and GND to the ON state when IO_ENABLE = L. The signal is not latched and the SIM_IO pin is released when IO_ENABLE returns to a High state. When the MPU uses two different channels to exchange data with the SIM card, this pin can be used as a Write line to the external card, the I/O pin being used to Read data from the SIM card. (7) – NA No Connection. (TSSOP–14 Only) No Connection. (TSSOP–14 Only) Description No Connection. (TSSOP–14 Only) (8) – NA 6 (9) GND GROUND This pin is the GROUND reference for the integrated circuit and associated signals. High frequency layout techniques are requested to connect the GND pin to the external functions. 7 (10) SIM_RST OUTPUT This pin is connected to the RST pin of the card connector. A voltage level translator adapts the external RESET signal (coming from the MPU) to the smart card. 8 (11) SIM_CLK OUTPUT This pin is connected to the CLK pin of the card connector. The CLOCK signal comes from the external clock generator. The internal voltage level shifter adapts the clock signal flowing through this link. Care must be observed to prevent AC coupling with adjacent lines and signals PCB tracks. 9 (12) SIM_VCC POWER This pin is connected to the smart card VCC power supply pin. The voltage, provided by an external power supply, can range from 2.7 V to 6.0 V. The NCN6011 does not regulate or protect the voltage supply applied to the external card. 10 (13) SIM_I/O OUTPUT This pin handles the connection to the serial I/O of the card connector. A bidirectional voltage level translator adapts the serial I/O signal between the card and the microcontroller. A 20 kΩ typical pull up resistor provides a High impedance state for the SIM card I/O link. (14) – NA No Connection. (TSSOP–14 Only) http://onsemi.com 3 NCN6011 MAXIMUM RATINGS Rating Symbol Value Unit VDD 7.0 V V SIM_VCC 7.0 V V Digital Input Voltage Digital Input Current RESET, IO_ENABLE –0.3 V VDD 1.0 V mA Digital Input Voltage Digital Input Current CLOCK –0.3 V VDD 1.0 V mA Digital Input Voltage Digital Input Current I/O –0.3 V VDD 1.0 V mA SIM_RST –0.3 V SIM_VCC 25 V mA SIM_I/O –0.3 V SIM_VCC 25 V mA SIM_CLK –0.3 V SIM_VCC 50 V mA 4.0 2.0 kV kV Power Supply External Card and Level Shifter Power Supply Digital Output Voltage Digital Output Current Digital Output/Input Voltage Digital Output/Input Current Digital Output Voltage Digital Output Current Human Body Model: R = 1500 Ω, C = 100 pF SIM card side, pins 7, 8, 9, 10 (10, 11, 12, 13) All other pins ESD Micro–10 Package Power Dissipation @ TA = +85°C Thermal Resistance Junction to Air PD RTHhja 200 200 mW °C/W TSSOP–14 Package Power Dissipation @ TA = +85°C Thermal Resistance Junction to Air PD RTHhja 320 125 mW °C/W Operating Ambient Temperature Range TA –25 to +85 °C Operating Junction Temperature Range TJ –25 to +125 °C TJmax +150 °C Tstg –65 to +150 °C Maximum Junction Temperature Storage Temperature Range Maximum electrical ratings define the values beyond which permanent damage(s) may occur internally to the chip regardless of the operating temperature. Pin numbers in parenthesis are related to the TSSOP–14 package. http://onsemi.com 4 NCN6011 POWER SUPPLY SECTION (–25°C to +85°C ambient temperature, unless otherwise noted) (Pin numbers in parenthesis are related to the TSSOP–14 package) (Pin numbers in bold are related to the MIcro–10 package) Rating Symbol Pin Min Typ Max Unit Power Supply VDD 2 (3) 2.7 – 6.0 V Standby Supply Current, CLOCK = L, I/O = H, SIM_VCC = 3.0 V, No SIM Card Inserted IVDD 2 (3) – 0.5 2.0 µA SIM_VCC 9 (12) 2.7 – 6.0 V Standby Current, SIM_VCC = 3.0 V, I/O = H, No SIM Card Inserted, CLOCK = L IVCC 9 (12) – 0.2 0.5 µA Power Supply Normal Operating Current @ VDD = +5.0 V, SIM_VCC = +5.0 V, CLOCK = 5.0 MHz, RESET = H, IO_ENABLE = H, I/O Data = 100 kHz IDD 2 (3) – 230 – µA Power Supply Normal Operating Current @ VDD = +5.0 V, SIM_VCC = +5.0 V, CLOCK = 5.0 MHz, RESET = H, IO_ENABLE = H, I/O Data = H IDD 2 (3) – 80 – µA Card Level Shifter Operating Current @ VDD = +5.0 V, SIM_VCC = +5.0 V, CLOCK = 5.0 MHz, RESET = H, IO_ENABLE = H, I/O Data = 100 kHz ICC 9 (12) – 1.50 – mA Card Level Shifter Operating Current @ VDD = +5.0 V, SIM_VCC = +5.0 V, CLOCK = 5.0 MHz, RESET = H, IO_ENABLE = H, I/O Data = H ICC 9 (12) – 1.30 – mA Input External Power Supply DIGITAL INPUT SECTION: CLOCK, RESET, I/O, IO_ENABLE (–25°C to +85°C ambient temperature, unless otherwise noted) (Note 1) Rating CLOCK, RESET, IO_ENABLE High Level Input Voltage Low Level Input Voltage Input Rise Time Input Fall Time Input Capacitance Input @ Duty Cycle = 50% 1% (Note 2) Clock Rise Time Clock Fall Time Input Clock Capacitance Symbol Pin Min Typ Max Unit VCC 0.3 * VDD 50 50 10 V V ns ns pF 5.0 50 50 10 MHz ns ns pF – VIH VIL tr tf Cin 1, 3, 4, 5 (2, 4, 5, 6) 0.7 * VDD CLOCK 3 (4) – – Input/Output Data Transfer Frequency I/O 1 – – 160 kHz I/O Rise Time (2) 0.8 µs I/O Fall Time 0.8 µs Input I/O Capacitance 10 pF 1. Digital inputs undershoot –0.30 V, Digital inputs overshoot 0.30 V. 2. The SIM_CLK clock can operate up to 10 MHz, but, in this case, the rise and fall time are not guaranteed to be fully within the GSM specification over the temperature range. http://onsemi.com 5 NCN6011 SIM INTERFACE SECTION (Note 3) Max Unit SIM_VCC – 0.7 V 0 SIM_VCC 0.6 100 100 V V ns ns 0.8 * SIM_VCC 0 SIM_VCC 0.2 * SIM_VCC 100 100 V V ns ns 40 60 % 0.7 * SIM_VCC 0 18 18 SIM_VCC +0.5 ns ns V V 40 60 % 0.7 * SIM_VCC 0 18 18 SIM_VCC 0.2 * SIM_VCC ns ns V V 0.7 * SIM_VCC 0 160 0.8 0.8 SIM_VCC 0.4 kHz µs µs V V SIM_VCC = +3.0 V @ IO_ENABLE = H SIM_I/O Data Transfer Frequency SIM_I/O Rise Time @ Cout = 30 pF SIM_I/O Fall Time @ Cout = 30 pF Output VOH @ ISIM_IO = +20 µA, VIH = VDD Output VOL @ ISIM_IO = –1.0 mA, I/O VIL = 0 V 0.7 * SIM_VCC 0 160 0.8 0.8 SIM_VCC 0.4 kHz µs µs V V SIM_VCC = +5.0 V @ IO_ENABLE = L SIM_I/O Fall Time @ Cout = 30 pF Output VOL @ ISIM_IO = –1.0 mA, I/O VIL = 0 V 150 0 800 0.4 ns V SIM_VCC = +3.0 V @ IO_ENABLE = L SIM_I/O Fall Time @ Cout = 30 pF Output VOL @ ISIM_IO = –1.0 mA, I/O VIL = 0 V 150 0 800 0.4 ns V Rating SIM_VCC = +5.0 V Output RESET VOH @ Irst = +200 µA Output RESET VOL @ Irst = –200 µA Output RESET Rise Time @ Cout = 30 pF Output RESET Fall Time @ Cout = 30 pF Symbol Pin SIM_RST 7 (10) Min SIM_VCC = +3.0 V Output RESET VOH @ Irst = +200 µA Output RESET VOL @ Irst = –200 µA Output RESET Rise Time @ Cout = 30 pF Output RESET Fall Time @ Cout = 30 pF SIM_VCC = +5.0 V Output Duty Cycle @ Fin = 5.0 MHz DC = 50% 1% Output SIM_CLK Rise Time @ Cout = 30 pF Output SIM_CLK Fall Time @ Cout = 30 pF Output VOH @ Iclk = +20 µA Output VOL @ Iclk = –200 µA SIM_CLK 8 (11) SIM_VCC = +3.0 V Output Duty Cycle @ Fin = 5.0 MHz DC = 50% 1% Output SIM_CLK Rise Time @ Cout = 30 pF Output SIM_CLK Fall Time @ Cout = 30 pF Output VOH @ Iclk = +20 µA Output VOL @ Iclk = –20 µA SIM_VCC = +5.0 V @ IO_ENABLE = H SIM_I/O Data Transfer Frequency SIM_I/O Rise Time @ Cout = 30 pF SIM_I/O Fall Time @ Cout = 30 pF Output VOH @ ISIM_IO = +20 µA, VIH = VDD Output VOL @ ISIM_IO = –1.0 mA, I/O VIL = 0 V SIM_I/O Typ 10 (13) SIM_VCC = +5.0 V @ I/O = H, IO_ENABLE Returns to High SIM_I/O Rise Time @ Cout = 30 pF 2.0 µs SIM_VCC = +3.0 V @ I/O = H, IO_ENABLE Returns to High SIM_I/O Rise Time @ Cout = 30 pF 1.5 µs I/O Pull Up Resistor Card I/O Pull Up Resistor I/O_RPLD 1 (2) 13 20 kΩ SIM_I/O_RPLD 10 (13) 13 20 kΩ 3. SIM logic input undershoot –0.30 V, SIM logic input overshoot 0.30 V. http://onsemi.com 6 NCN6011 120 300 100 250 5 MHz 5 MHz 200 IDD (µA) IDD (µA) 80 3 MHz 60 40 3 MHz 150 1 MHz 100 1 MHz 20 50 0 2 3 4 0 6 5 3 4 5 VDD (V) VDD (V) Figure 3. SIM Supply Current as a Function of the VDD Voltage, I/O = High Figure 4. SIM Supply Current as a Function of the VDD Voltage, I/O = 100 kHz Data Transfer 1600 1800 5 MHz 6 5 MHz 1600 1400 1400 1200 1200 ICC (µA) 1000 ICC (µA) 2 3 MHz 3 MHz 1000 800 600 800 600 400 1 MHz 1 MHz 400 200 200 0 0 2 3 4 5 2 6 3 4 5 VDD (V) VDD (V) Figure 5. Power Supply Current as Function of the VCC Input Voltage, I/O = High Figure 6. Power Supply Current as Function of the VCC Input Voltage, I/O = 100 kHz Data Transfer http://onsemi.com 7 6 NCN6011 VDD Level Shifters The built–in level shifters accommodate the differential voltage between the external MPU and the SIM card. Neither the logic nor the functions of the SIM signals are affected by the interface. The NCN6011 does not regulate the SIM_VCC, nor does it detect the overload current. VCC Q1 Q2 20 k 20 k 200 ns 200 ns I/O Bidirectional Level Shifter The NCN6011 carries out the voltage difference between the MPU and the Smart Card I/O signals. When the start sequence is completed, and if no failures have been detected, the device becomes essentially transparent for the data transferred on the I/O line. To fulfill the ISO7816–3 specification, both sides of the I/O line have built–in pulsed circuitry to accelerate the signal rise transient. The I/O line is connected on both sides of the interface by a NMOS switch which provide the level shifter and, thanks to its relative high internal impedance, protects the Smart Card in the event of data collision. Such a situation could occur if either the MPU of the smart card forces a signal in the opposite logic level direction. SIM_IO GND Q5 I/O CONTROL LOGIC GND ENABLE Figure 7. Basic Internal I/O Level Shifter SIM_IO SIM_IO ENABLE I/O Figure 8. Typical I/O and SIM_IO Waveform, VDD = VCC = 5.0 V, ENABLE = Low Figure 9. Typical SIM_IO Activated by ENABLE Pin, I/O = High (open drain) http://onsemi.com 8 NCN6011 Input Schmitt Triggers All the Logic Input pins have built–in schmitt trigger circuits to prevent the NCN6011 against uncontrolled operation. The typical dynamic characteristics of the related pins are depicted in Figure 10. The output signal is guaranteed to go High when the input voltage is above 0.70*Vbat, and will go Low when the input voltage is below 0.30*Vbat. ESD Protection The NCN6011 includes silicon devices to protect the pins against the ESD spikes voltages. To cope with the different ESD voltages developed across these pins, the built–in structures have been designed to handle either 2.0 kV, when related to the microcontroller side, or 4.0 kV when connected with the external contacts. Practically, the SIM_RST, SIMD_CLK and SIM_IO pins can sustain 4.0 kV. Output Printed Circuit Board Layout Since the NCN6011 carries high speed currents together with high frequency clock, the printed circuit board must be carefully designed to avoid the risk of uncontrolled operation of the interface. Care must be observed to avoid common copper track sharing small signal and high power with a relative high impedance. On top of that, the clock signal (both input and output) shall be properly shielding to minimize the high frequency cross talk between this line and the rest of the circuit. In particular, the SIM_RST signal shall be protected from interference generated by the SIM_CLK line. Such protection can be achieved by surrounding the SIM_CLK track by a copper track connected to ground. Generally speaking, the ground plane shall be as large as possible for a given printed circuit board area. Vbat ON OFF 0.70 *Vbat 0.30 *Vbat Input Vbat Figure 10. Typical Schmitt Trigger Characteristic Vsupply VCC POWER MANAGEMENT UNIT VDD C3 4.7 µF C1 6.8 µF VCC U1 NCN6011 1 GND MPU or GSM Controller P3 2 3 P2 P1 P0 4 5 6 GND NA NA I/O SIM_IO 14 13 C2 100 nF 12 VDD SIM_VCC CLOCK SIM_CLK 11 GND 10 RESET SIM_RST 9 I/O_ENABLE GND 8 7 NA NA GND 5 1 3 2 4 8 18 7 GND VPP VCC CLK I/O C4 C8 RST GND GND Swb Swa 17 IRQ Figure 11. Typical NCN6011/TSSOP–14 Application http://onsemi.com 9 NCN6011 ORDERING INFORMATION Device Package Shipping NCN6011DTB TSSOP–14 96 Units/Rail NCN6011DTBR2 TSSOP–14 2500 Tape & Reel NCN6011DMR2 Micro–10 4000 Tape & Reel http://onsemi.com 10 NCN6011 PACKAGE DIMENSIONS TSSOP–14 DTB SUFFIX CASE 948G–01 ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. 14X K REF 0.10 (0.004) 0.15 (0.006) T U T U M V S S S N 2X 14 L/2 0.25 (0.010) 8 M B –U– L PIN 1 IDENT. F 7 1 0.15 (0.006) T U N S DETAIL E K ÉÉ ÇÇ ÇÇ ÉÉ ÇÇ A –V– K1 J J1 SECTION N–N –W– C 0.10 (0.004) –T– SEATING PLANE H G D DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 Micro–10 DM SUFFIX CASE 846B–02 ISSUE A NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A" DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B" DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. 846B-01 OBSOLETE. NEW STANDARD 846B-02 –A– –B– K D 8 PL 0.08 (0.003) PIN 1 ID G –T– M T B S A S SEATING PLANE 0.038 (0.0015) C H L J http://onsemi.com 11 DIM A B C D G H J K L MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.95 1.10 0.20 0.35 0.50 BSC 0.05 0.15 0.10 0.21 4.75 5.05 0.40 0.70 INCHES MIN MAX 0.114 0.122 0.114 0.122 0.037 0.043 0.008 0.014 0.020 BSC 0.002 0.006 0.004 0.008 0.187 0.199 0.016 0.028 NCN6011 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: [email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone: 81–3–5740–2700 Email: [email protected] ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. N. American Technical Support: 800–282–9855 Toll Free USA/Canada http://onsemi.com 12 NCN6011/D