HM62W16255HC Series 4M High Speed SRAM (256-kword × 16-bit) ADE-203-1200D (Z) Rev. 3.0 Dec. 5, 2002 Description The HM62W16255HC is a 4-Mbit high speed static RAM organized 256-kword × 16-bit. It has realized high speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. The HM62W16255HC is packaged in 400-mil 44-pin SOJ and 400-mil 44-pin plastic TSOPII for high density surface mounting. Features • Single 3.3 V supply: 3.3 V ± 0.3 V • Access time: 10/12 ns (max) • Completely static memory No clock or timing strobe required • Equal access and cycle times • Directly TTL compatible All inputs and outputs • Operating current: 145/130 mA (max) • TTL standby current: 40 mA (max) • CMOS standby current : 5 mA (max) : 1 mA (max) (L-version) • Data retention current: 0.6 mA (max) (L-version) • Data retention voltage: 2.0 V (min) (L-version) • Center VCC and VSS type pin out HM62W16255HC Series Ordering Information Type No. Access time Device marking Package HM62W16255HCJP-10 HM62W16255HCJP-12 10 ns 12 ns 400-mil 44-pin plastic SOJ (CP-44D) HM62W16255CJP10 HM62W16255CJP12 HM62W16255HCLJP-10 10 ns HM62W16255HCLJP-12 12 ns HM62W16255CLJP10 HM62W16255CLJP12 HM62W16255HCTT-10 HM62W16255HCTT-12 HM62W16255CTT10 HM62W16255CTT12 10 ns 12 ns HM62W16255HCLTT-10 10 ns HM62W16255HCLTT-12 12 ns Rev.3, Dec. 2002, page 2 of 18 HM62W16255CLTT10 HM62W16255CLTT12 400-mil 44-pin plastic TSOPII (TTP-44DE) HM62W16255HC Series Pin Arrangement 44-pin SOJ A0 A1 A2 A3 A4 I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 (Top View) 44-pin TSOP A17 A16 A15 I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A14 A13 A12 A11 A10 A0 A1 A2 A3 A4 I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 A5 A6 A7 A8 A9 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A17 A16 A15 I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A14 A13 A12 A11 A10 (Top View) Pin Description Pin name Function A0 to A17 Address input I/O1 to I/O16 Data input/output CS Chip select OE Output enable WE Write enable UB Upper byte select LB Lower byte select VCC Power supply VSS Ground NC No connection Rev.3, Dec. 2002, page 3 of 18 HM62W16255HC Series Block Diagram (LSB) A14 A13 A12 A5 A6 A7 A11 A10 A3 (MSB) A1 VCC Row decoder Memory matrix 1024 rows × 32 columns × 8 blocks × 16 bit (4,194,304 bits) VSS CS I/O1 .. . I/O8 Column I/O Input data control I/O9 .. . I/O16 Column decoder CS (LSB) A8 A9 A17 A15 A16 A0 A2 A4 (MSB) CS Rev.3, Dec. 2002, page 4 of 18 HM62W16255HC Series Operation Table CS OE WE LB UB Mode VCC current I/O1− −I/O8 I/O9− −I/O16 Ref. cycle H × × × × Standby ISB, ISB1 High-Z High-Z L H H × × Output disable ICC High-Z High-Z L L H L L Read ICC Output Output Read cycle L L H L H Lower byte read ICC Output High-Z Read cycle L L H H L Upper byte read ICC High-Z Output Read cycle L L H H H ICC High-Z High-Z L × L L L Write ICC Input Input Write cycle L × L L H Lower byte write ICC Input High-Z Write cycle L × L H L Upper byte write ICC High-Z Input Write cycle L × L H H High-Z High-Z ICC Note: H: VIH, L: VIL, ×: VIH or VIL Absolute Maximum Ratings Parameter Symbol Value Supply voltage relative to VSS VCC −0.5 to +4.6 Voltage on any pin relative to VSS VT −0.5* to VCC + 0.5* V Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 °C Storage temperature Tstg −55 to +125 °C Storage temperature under bias Tbias −10 to +85 °C 1 Unit V 2 Notes: 1. VT (min) = −2.0 V for pulse width (under shoot) ≤ 6 ns. 2. VT (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns. Rev.3, Dec. 2002, page 5 of 18 HM62W16255HC Series Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Symbol Supply voltage Min Typ Max Unit 3 3.0 3.3 3.6 V 4 0 0 0 VIH 2.0 VCC + 0.5* V VIL −0.5* 0.8 V VCC* VSS* Input voltage Notes: 1. 2. 3. 4. 1 V 2 VIL (min) = −2.0 V for pulse width (under shoot) ≤ 6 ns. VIH (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. DC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) Parameter Symbol Min Input leakage current |ILI| Output leakage current |ILO| Operation power supply current 1 Max Unit Test conditions 2 µA VIN = VSS to VCC 2 µA VIN = VSS to VCC 10 ns cycle ICC 145 mA Min cycle CS = VIL, IOUT = 0 mA Other inputs = VIH/VIL 12 ns cycle ICC Standby power supply current 130 mA ISB 40 mA Min cycle, CS = VIH, Other inputs = VIH/VIL ISB1 2.5 5 mA f = 0 MHz VCC ≥ CS ≥ VCC − 0.2 V, (1) 0 V ≤ VIN ≤ 0.2 V or (2) VCC ≥ VIN ≥ VCC − 0.2 V * 0.5* 1.0* mA VOL 0.4 V IOL = 8 mA VOH 2.4 V IOH = −4 mA 2 Output voltage Typ* 2 2 Notes: 1. Typical values are at VCC = 3.3 V, Ta = +25°C and not guaranteed. 2. This characteristics is guaranteed only for L-version. Rev.3, Dec. 2002, page 6 of 18 HM62W16255HC Series Capacitance (Ta = +25°C, f = 1.0 MHz) Parameter Input capacitance* 1 1 Input/output capacitance* Note: Symbol Min Typ Max Unit Test conditions CIN 6 pF VIN = 0 V CI/O 8 pF VI/O = 0 V 1. This parameter is sampled and not 100% tested. Rev.3, Dec. 2002, page 7 of 18 HM62W16255HC Series AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, unless otherwise noted.) Test Conditions • Input pulse levels: 3.0 V/0.0 V • Input rise and fall time: 3 ns • Input and output timing reference levels: 1.5 V • Output load: See figures (Including scope and jig) 3.3 V 1.5 V RL = 50 Ω DOUT Zo = 50 Ω 319 Ω DOUT 353 Ω 30 pF 5 pF Output load (B) (for tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ, tWHZ, and tOW) Output load (A) Read Cycle HM62W16255HC -10 -12 Parameter Symbol Min Max Min Max Unit Read cycle time tRC 10 12 ns Address access time tAA 10 12 ns Chip select access time tACS 10 12 ns Output enable to output valid tOE 5 6 ns Byte select to output valid tBA 5 6 ns Notes Output hold from address change tOH 3 3 ns Chip select to output in low-Z tCLZ 3 3 ns 1 Output enable to output in low-Z tOLZ 0 0 ns 1 Byte select to output in low-Z tBLZ 0 0 ns 1 Chip deselect to output in high-Z tCHZ 5 6 ns 1 Output disable to output in high-Z tOHZ 5 6 ns 1 Byte deselect to output in high-Z tBHZ 5 6 ns 1 Rev.3, Dec. 2002, page 8 of 18 HM62W16255HC Series Write Cycle HM62W16255HC -10 -12 Parameter Symbol Min Max Min Max Unit Notes Write cycle time tWC 10 12 ns Address valid to end of write tAW 7 8 ns Chip select to end of write tCW 7 8 ns 8 Write pulse width tWP 7 8 ns 7 Byte select to end of write tBW 7 8 ns Address setup time tAS 0 0 ns 5 Write recovery time tWR 0 0 ns 6 Data to write time overlap tDW 5 6 ns Data hold from write time tDH 0 0 ns Write disable to output in low-Z tOW 3 3 ns 1 Output disable to output in high-Z tOHZ 5 6 ns 1 Write enable to output in high-Z tWHZ 5 6 ns 1 Notes: 1. Transition is measured ±200 mV from steady voltage with output load (B). This parameter is sampled and not 100% tested. 2. If the CS or LB or UB low transition occurs simultaneously with the WE low transition or after the WE transition, output remains a high impedance state. 3. WE and/or CS must be high during address transition time. 4. If CS, OE, LB and UB are low during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 5. tAS is measured from the latest address transition to the latest of CS, WE, LB or UB going low. 6. tWR is measured from the earliest of CS, WE, LB or UB going high to the first address transition. 7. A write occurs during the overlap of a low CS, a low WE and a low LB or a low UB (tWP). A write begins at the latest transition among CS going low, WE going low and LB going low or UB going low. A write ends at the earliest transition among CS going high, WE going high and LB going high or UB going high. 8. tCW is measured from the later of CS going low to the end of write. Rev.3, Dec. 2002, page 9 of 18 HM62W16255HC Series Timing Waveforms Read Timing Waveform (1) (WE = VIH) t RC Address Valid address tAA tACS CS tOE tCHZ *1 tBA tOHZ *1 tBLZ *1 tBHZ *1 OE LB, UB tOLZ *1 tOH tCLZ *1 DOUT High impedance *4 Rev.3, Dec. 2002, page 10 of 18 Valid data *4 HM62W16255HC Series Read Timing Waveform (2) (WE = VIH, LB = VIL, UB = VIL) tRC Address Valid address tOH tAA tACS CS tOE tCHZ*1 tOHZ*1 OE tOLZ*1 tCLZ *1 DOUT High impedance *4 Valid data *4 Rev.3, Dec. 2002, page 11 of 18 HM62W16255HC Series Write Timing Waveform (1) (WE Controlled) tWC Valid address Address tWR tAW tAS tWP WE*3 tCW CS*3 OE tBW LB, UB tOLZ tWHZ tOW tOHZ High impedance DOUT *2 DIN Rev.3, Dec. 2002, page 12 of 18 tDW tDH Valid data HM62W16255HC Series Write Timing Waveform (2) (CS Controlled) tWC Valid address Address tWR tAW tAS tWP WE *3 tCW CS *3 OE tBW LB, UB tOLZ tWHZ tOW tOHZ High impedance * 4 DOUT *2 DIN tDW tDH Valid data Rev.3, Dec. 2002, page 13 of 18 HM62W16255HC Series Write Timing Waveform (3) (LB, UB Controlled, OE = VIH) tWC Address Valid address tAW tWR tWP WE*3 tCW CS*3 tAS tBW UB (LB) tBW LB (UB) tDW DIN-UB (DIN-LB) tDH Valid data tDW DIN-LB (DIN-UB) DOUT Rev.3, Dec. 2002, page 14 of 18 tDH Valid data High impedance HM62W16255HC Series Low VCC Data Retention Characteristics (Ta = 0 to +70°C) This characteristics is guaranteed only for L-version. Parameter Symbol Min Typ Max Unit Test conditions VCC for data retention VDR 2.0 V VCC ≥ CS ≥ VCC − 0.2 V, (1) 0 V ≤ VIN ≤ 0.2 V or (2) VCC ≥ VIN ≥ VCC − 0.2 V Data retention current ICCDR 600 µA VCC = 3 V VCC ≥ CS ≥ VCC − 0.2 V, (1) 0 V ≤ VIN ≤ 0.2 V or (2) VCC ≥ VIN ≥ VCC − 0.2 V Chip deselect to data retention time tCDR 0 ns See retention waveform Operation recovery time tR 5 ms Low VCC Data Retention Timing Waveform t CDR Data retention mode tR V CC 3.0 V V DR 2.0 V 0V VCC ≥ ≥ VCC – 0.2 V Rev.3, Dec. 2002, page 15 of 18 HM62W16255HC Series Package Dimensions HM62W16255HCJP/HCLJP Series (CP-44D) As of July, 2002 Unit: mm 28.33 28.90 Max 1.27 *0.43 ± 0.10 0.41 ± 0.08 0.10 *Dimension including the plating thickness Base material dimension Rev.3, Dec. 2002, page 16 of 18 2.65 ± 0.12 1.30 Max 0.80 +0.25 –0.17 22 0.74 3.50 ± 0.26 1 11.18 ± 0.13 23 10.16 ± 0.13 44 9.40 ± 0.25 Hitachi Code JEDEC JEITA Mass (reference value) CP-44D Conforms — 1.8 g HM62W16255HC Series HM62W16255HCTT/HCLTT Series (TTP-44DE) As of July, 2002 Unit: mm 18.41 18.81 Max 23 10.16 44 0.80 *0.27 ± 0.07 0.25 ± 0.05 22 0.80 0.13 M 11.76 ± 0.20 1.005 Max *Dimension including the plating thickness Base material dimension 0.13 ± 0.05 0.10 *0.145 ± 0.05 0.125 ± 0.04 1.20 Max 0˚ – 5˚ 0.50 ± 0.10 Hitachi Code JEDEC JEITA Mass (reference value) 0.68 1 TTP-44DE — — 0.43 g Rev.3, Dec. 2002, page 17 of 18 HM62W16255HC Series Disclaimer 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. 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(Taipei Branch Office) 4/F, No. 167, Tun Hwa North Road Hung-Kuo Building Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TP URL : http://semiconductor.hitachi.com.tw Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel : <852>-2735-9218 Fax : <852>-2730-0281 URL : http://semiconductor.hitachi.com.hk Copyright © Hitachi, Ltd., 2002. All rights reserved. Printed in Japan. Colophon 7.0 Rev.3, Dec. 2002, page 18 of 18