HM62W1400H Series 4M High Speed SRAM (4-Mword × 1-bit) ADE-203-773E (Z) Rev. 2.0 Nov. 11, 1998 Description The HM62W1400H is a 4-Mbit high speed static RAM organized 4-Mword × 1-bit. It has realized high speed access time by employing CMOS process (4-transistor + 2-poly resistor memory cell)and high speed circuit designing technology. It is most appropriate for the application which requires high speed and high density memory, such as cache and buffer memory in system. The HM62W1400H is packaged in 400-mil 32-pin SOJ and 400-mil 32-pin TSOP II for high density surface mounting. Features • Single 3.3 V supply : 3.3 V ± 0.3 V • Access time 12/15 ns (max) • Completely static memory No clock or timing strobe required • Equal access and cycle times • Directly TTL compatible All inputs and outputs • Operating current: 180/160 mA (max) • TTL standby current: 60/50 mA (max) • CMOS standby current: 5 mA (max) : 1 mA (max) (L-version) • Data retension current: 0.6 mA (max) (L-version) • Data retension voltage: 2 V (min) (L-version) • Center VCC and VSS type pinout HM62W1400H Series Ordering Information Type No. Access time Package HM62W1400HJP-12 HM62W1400HJP-15 12 ns 15 ns 400-mil 32-pin plastic SOJ (CP-32DB) HM62W1400HLJP-12 HM62W1400HLJP-15 12 ns 15 ns HM62W1400HTT-12 HM62W1400HTT-15 12 ns 15 ns HM62W1400HLTT-12 HM62W1400HLTT-15 12 ns 15 ns 400-mil 32-pin plastic TSOP II (TTP-32DC) Pin Arrangement HM62W1400HJP/HLJP Series A0 A1 A2 A3 A4 A5 CS VCC VSS Din WE A6 A7 A8 A9 A10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 (Top view) 2 A21 A20 A19 A18 A17 A16 OE VSS VCC Dout A15 A14 A13 A12 A11 NC HM62W1400HTT/HLTT Series A0 A1 A2 A3 A4 A5 CS VCC VSS Din WE A6 A7 A8 A9 A10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 (Top view) A21 A20 A19 A18 A17 A16 OE VSS VCC Dout A15 A14 A13 A12 A11 NC HM62W1400H Series Pin Description Pin name Function A0 to A21 Address input Din Data input Dout Data output CS Chip select OE Output enable WE Write enable VCC Power supply VSS Ground NC No connection Block Diagram (LSB) A2 A18 A8 A12 A17 A3 A7 A6 (MSB) VCC Memory matrix 256 rows × 64 columns × 256 blocks × 1 bit (4,194,304 bits) Row decoder VSS CS Din Column I/O Dout CS Column decoder A11 A9 A10A20 A21 A0 A13 A14 A15 A1 A19 A16 A4 A5 CS WE OE (LSB) (MSB) CS 3 HM62W1400H Series Operation Table CS OE WE Mode VCC current Dout Ref. cycle H × × Standby I SB , I SB1 High-Z — L H H Output disable I CC High-Z — L L H Read I CC Dout Read cycle (1) to (3) L H L Write I CC High-Z Write cycle (1) L L Write I CC High-Z Write cycle (2) L Note: ×: H or L Absolute Maximum Ratings Parameter Symbol Value Supply voltage relative to VSS VCC –0.5 to +4.6 Unit V 1 2 Voltage on any pin relative to V SS VT –0.5* to V CC+0.5* V Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 °C Storage temperature Tstg –55 to +125 °C Storage temperature under bias Tbias –10 to +85 °C Notes: 1. VT (min) = –2.0 V for pulse width (under shoot) ≤ 8 ns 2. VT (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 8 ns Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Symbol Supply voltage Input voltage Min Typ Max Unit VCC* 3 3.0 3.3 3.6 V VSS * 4 0 0 0 VIH VIL Notes: 1. 2. 3. 4. 4 2.2 1 –0.5* V 2 — VCC + 0.5* V — 0.8 V VIL (min) = –2.0 V for pulse width (under shoot) ≤ 8 ns VIH (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 8 ns The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. HM62W1400H Series DC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0V) Parameter Symbol Min Typ*1 Max Unit Test conditions Input leakage current IILII — — 2 µA Vin = VSS to V CC Output leakage current IILO I — — 2 µA Vin = VSS to V CC 12 ns cycle I CC — — 180 mA Min cycle CS = VIL, lout = 0 mA Other inputs = VIH/VIL 15 ns cycle I CC — — 160 12 ns cycle I SB — — 60 mA Min cycle, CS = VIH, Other inputs = VIH/VIL 15 ns cycle I SB — — 50 — 0.05 5 mA f = 0 MHz VCC ≥ CS ≥ VCC - 0.2 V, (1) 0 V ≤ Vin ≤ 0.2 V or (2) VCC ≥ Vin ≥ VCC - 0.2 V —* 2 0.05*2 1* 2 VOL — — 0.4 V I OL = 8 mA VOH 2.4 — — V I OH = –4 mA Operation power supply current Standby power supply current I SB1 Output voltage Notes: 1. Typical values are at VCC = 3.3 V, Ta = +25°C and not guaranteed. 2. This characteristics is guaranteed only for L-version. Capacitance (Ta = +25°C, f = 1.0 MHz) Parameter 1 Input capacitance* Input/output capacitance* Note: 1 Symbol Min Typ Max Unit Test conditions Cin — — 6 pF Vin = 0 V CDIN — — 8 pF VDIN = 0 V CDOUT — — 8 pF VDOUT = 0 V 1. This parameter is sampled and not 100% tested. 5 HM62W1400H Series AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, unless otherwise noted.) Test Conditions • • • • Input pulse levels: 3.0 V/0.0 V Input rise and fall time: 3 ns Input and output timing reference levels: 1.5 V Output load: See figures (Including scope and jig) 3.3 V 319Ω Dout Zo=50 Ω Dout RL=50 Ω 353Ω 1.5 V Output load (A) 5 pF Output load (B) (for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW) Read Cycle HM62W1400H -12 -15 Parameter Symbol Min Max Min Max Unit Read cycle time t RC 12 — 15 — ns Address access time t AA — 12 — 15 ns Chip select access time t ACS — 12 — 15 ns Output enable to outpput valid t OE — 6 — 7 ns Output hold from address change t OH 3 — 3 — ns Chip select to output in low-Z t CLZ 3 — 3 — ns 1 Output enable to output in low-Z t OLZ 0 — 0 — ns 1 Chip deselect to output in high-Z t CHZ — 6 — 7 ns 1 Output disable to output in high-Z t OHZ — 6 — 7 ns 1 6 Notes HM62W1400H Series Write Cycle HM62W1400H -12 -15 Parameter Symbol Min Max Min Max Unit Write cycle time t WC 12 — 15 — ns Address valid to end of write t AW 8 — 10 — ns Chip select to end of write t CW 8 — 10 — ns 9 Write pulse width t WP 8 — 10 — ns 8 Address setup time t AS 0 — 0 — ns 6 Write recovery time t WR 0 — 0 — ns 7 Data to write time overlap t DW 6 — 7 — ns Data hold from write time t DH 0 — 0 — ns Write disable to output in low-Z t OW 3 — 3 — ns 1 Output disable to output in high-Z t OHZ — 6 — 7 ns 1 Write enable to output in high-Z t WHZ — 6 — 7 ns 1 Note: Notes 1. Transition is measured ±200 mV from steady voltage with Load (B). This parameter is sampled and not 100% tested. 2. Address should be valid prior to or coincident with CS transition low. 3. WE and/or CS must be high during address transition time. 4. if CS and OE are low during this period, Dout pins are in the output state. Then, the data input signals of opposite phase to the outputs must not be applied to them. 5. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, output remains a high impedance state. 6. t AS is measured from the latest address transition to the later of CS or WE going low. 7. t WR is measured from the earlier of CS or WE going high to the first address transition. 8. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going low and WE going low. A write ends at the earliest transition among CS going high and WE going high. tWP is measured from the beginnig of write to the end of write. 9. t CW is measured from the later of CS going low to the the end of write. 7 HM62W1400H Series Timing Waveforms Read Timing Waveform (1) (WE = VIH) tRC Address Valid address tOH tAA tACS tCHZ CS tOE tOHZ OE tOLZ tCLZ Dout High Impedance Valid data Read Timing Waveform (2) (WE = VIH, CS = VIL , OE = VIL ) tRC Address Valid address tAA tOH tOH Dout 8 Valid data HM62W1400H Series Read Timing Waveform (3) (WE = VIH, CS = VIL , OE = VIL )*2 tRC CS tACS tCHZ tCLZ Dout High Impedance Valid data High Impedance Write Timing Waveform (1) (WE Controlled) tWC Valid address Address tWR tAW OE tCW CS*3 tAS tWP WE*3 tOHZ High impedance*5 Dout tDW Din *4 tDH Valid data *4 9 HM62W1400H Series Write Timing Waveform (2) (CS Controlled) tWC Valid address Address tWR tCW CS *3 tAW tWP WE *3 tAS tWHZ tOW High impedance*5 Dout tDW Din 10 *4 tDH Valid data *4 HM62W1400H Series Low VCC Data Retention Characteristics (Ta = 0 to +70°C) This characteristics is guaranteed only for L-version. Parameter Symbol Min Typ*1 Max Unit Test conditions VCC for data retention VDR 2.0 — — V VCC ≥ CS ≥ VCC – 0.2 V (1) 0 V ≤ Vin ≤ 0.2 V or (2) VCC ≥ Vin ≥ VCC – 0.2 V Data retention current I CCDR — 40 600 µA VCC = 3 V, VCC ≥ CS ≥ VCC – 0.2 V (1) 0 V ≤ Vin ≤ 0.2 V or (2) VCC ≥ Vin ≥ VCC – 0.2 V Chip deselect to data retention time t CDR 0 — — ns See retention waveform Operation recovery time tR 5 — — ms Note: 1. Typical values are at V CC = 3.0 V, Ta = +25˚C, and not guaranteed. Low V CC Data Retention Timing Waveform tCDR Data retention mode tR VCC 3.0 V VDR 2.2 V CS 0V VCC ≥ CS ≥ VCC – 0.2 V 11 HM62W1400H Series Package Dimensions HM62W1400HJP/HLJP Series (CP-32DB) Unit: mm 3.50 ± 0.26 1.30 Max 0.43 ± 0.10 0.41 ± 0.08 1.27 0.10 Dimension including the plating thickness Base material dimension 12 2.85 ± 0.12 16 0.74 0.80 +0.25 –0.17 1 11.18 ± 0.13 17 10.16 ± 0.13 32 20.71 21.08 Max 9.40 ± 0.25 Hitachi Code JEDEC EIAJ Weight (reference value) CP-32DB Conforms Conforms 1.2 g HM62W1400H Series HM62W1400HTT/HLTT Series (TTP-32DC) Unit: mm 20.95 21.35 Max 17 10.16 32 1.27 0.21 M 0.80 11.76 ± 0.20 0.10 *Dimension including the plating thickness Base material dimension *0.145 ± 0.05 0.125 ± 0.04 1.20 Max 1.15 Max 0° – 5° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) 0.68 *0.42 ± 0.08 0.40 ± 0.06 16 0.13 ± 0.05 1 TTP-32DC Conforms — 0.51 g 13 HM62W1400H Series Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 URL NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to: Hitachi Semiconductor (America) Inc. 2000 Sierra Point Parkway Brisbane, CA 94005-1897 Tel: <1> (800) 285-1601 Fax: <1> (303) 297-0447 Hitachi Europe GmbH Electronic components Group Dornacher Straße 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan. 14 HM62W1400H Series Revision Record Rev. Date Contents of Modification Drawn by Approved by A. Ide A. Ide K. Makuta 0.0 Apr. 28, 1997 Initial issue 0.1 Nov. 20, 1997 Change of Subtitle K. Makuta 0.2 Dec. 5, 1997 Features Addition of Operating current Addition of TTL standby current Addition of CMOS standby current Addition of Data retention current Addition of Data retention voltage Change of Block Diagram Operation table Title: I/O to Dout Dout: Din to High-Z Absolute Maximum Ratings Change of notes Recommended DC Operatig Conditions Change of notes DC Characteristics I CC (max): 240/200/190 mA to 160/140/120 mA I SB (max): 100/100/100 mA to 70/60/50 mA I SB1 (max): 10/0.5 mA to 5/1 mA Testconditions ICC and ISB : Addition of Min cycle Testconditions ISB1: Addition of f = 0 MHz Chapacitance Addition of C DIN Input/output capacitance: CI/O to CDOUT AC Characteristics Change of Output load (A) t OE, tCHZ and tOHZ (max): 5/6/8 ns to 5/6/7 ns t AW, t CW and tWP (min): 6/8/10 ns to 7/8/10 ns t DW (min): 5/6/8 ns to 5/6/7 ns t OHZ and t WHZ (max): 5/6/8 ns to 5/6/7 ns Note 4.: Correct error Low VCC Data Retention Characteristics I CCDR: —/2/300 µA to —/—/300 µA T. Fukazawa K. Makuta 0.3 May. 15, 1998 Features Change of Operating current Change of Block Diagram DC Characteristics I CC (max): 170/150/130 mA to 200/180/160 mA T. Fukazawa K. Makuta 1.0 Sep. 15, 1998 Delete of HM62W1400H-10 Series Features Change of Data retention current DC Characteristics I SB1 (typ): —/— mA to 0.05/0.05 mA Low VCC Data Retention Characteristics I CCDR: —/—/300 µA to —/40/600 µA T. Fukazawa K. Makuta 15 HM62W1400H Series Rev. Date 2.0 16 Contents of Modification Nov. 11, 1998 Addition of TTP-32DC Ordering Information Addition of HM62W1400HTT/ HM62W1400HLTT Series Drawn by Approved by