ISL9N305ASK8T
N-Channel Logic Level PWM Optimized UltraFET® Trench Power MOSFET
General Description
Features
This device employs a new advanced trench MOSFET
technology and features low gate charge while maintaining
low on-resistance.
• Fast switching
Optimized for switching applications, this device improves
the overall efficiency of DC/DC converters and allows
operation to higher switching frequencies.
• rDS(ON) = 0.0064Ω (Typ), VGS = 4.5V
Applications
• Qgd (Typ) = 11.5nC
• DC/DC converters
• CISS (Typ) = 4260pF
• rDS(ON) = 0.004Ω (Typ), VGS = 10V
• Qg (Typ) = 38nC, VGS = 5V
Branding Dash
5
1
2
3
4
SOURCE (1)
DRAIN (8)
SOURCE (2)
DRAIN (7)
SOURCE (3)
DRAIN (6)
GATE (4)
DRAIN (5)
SO-8
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Symbol
VDSS
Drain to Source Voltage
Parameter
Ratings
30
Units
V
VGS
Gate to Source Voltage
±20
V
Continuous (TA = 25oC, VGS = 10V)
18
A
Continuous (TA = 100oC, VGS = 4.5V)
9
A
Drain Current
`ID
Pulsed
PD
Power dissipation
Derate above 25oC
TJ, TSTG
Operating and Storage Temperature
Figure 4
A
2.5
20
W
mW/oC
o
-55 to 150
C
Thermal Characteristics
RθJA
FR-4 board with 0.76 in2( 490 mm2 ) copper pad at 10 seconds
in2(
34.8
mm2
50
RθJA
FR-4 board with 0.054
) copper pad at 1000 seconds
RθJA
FR-4 board with 0.0115 in2( 7.42 mm2 ) copper pad at 1000 seconds
o
C/W
152
oC/W
189
o
C/W
Package Marking and Ordering Information
Device Marking
N305ASK8
©2002 Fairchild Semiconductor Corporation
Device
ISL9N305ASK8T
Reel Size
330mm
Tape Width
12mm
Quantity
2500units
ISL9N305ASK8T Rev A1
ISL9N305ASK8T
October 2002
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
30
-
-
-
V
-
1
-
-
250
µA
-
-
±100
nA
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250µA, VGS = 0V
VDS = 25V
VGS = 0V
TA = 150oC
VGS = ±20V
On Characteristics
VGS(TH)
rDS(ON)
Gate to Source Threshold Voltage
Drain to Source On Resistance
VGS = VDS, ID = 250µA
1
-
3
V
ID = 18A, VGS = 10V
-
0.004
0.005
ID = 9A, VGS = 4.5V
-
0.0064
0.008
Ω
-
4260
-
-
750
-
pF
-
340
-
pF
nC
Dynamic Characteristics
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
VDS = 15V, VGS = 0V,
f = 1MHz
Qg(TOT)
Total Gate Charge at 10V
VGS = 0V to 10V
Qg(5)
Total Gate Charge at 5V
Qg(TH)
Threshold Gate Charge
Qgs
Gate to Source Gate Charge
VGS = 0V to 5V V = 15V
DD
VGS = 0V to 1V ID = 9A
Ig = 1.0mA
Qgd
Gate to Drain “Miller” Charge
Switching Characteristics
pF
72
108
-
38
57
nC
-
4.1
6.1
nC
-
10.4
-
nC
-
11.5
-
nC
(VGS = 4.5V)
tON
Turn-On Time
-
-
158
ns
td(ON)
Turn-On Delay Time
-
24
-
ns
tr
Rise Time
-
81
-
ns
td(OFF)
Turn-Off Delay Time
-
44
-
ns
tf
Fall Time
-
52
-
ns
tOFF
Turn-Off Time
-
-
145
ns
Switching Characteristics
VDD = 15V, ID = 9A
VGS = 4.5V, RGS = 3.9Ω
(VGS = 10V)
tON
Turn-On Time
-
-
100
ns
td(ON)
Turn-On Delay Time
-
12
-
ns
tr
Rise Time
-
55
-
ns
td(OFF)
Turn-Off Delay Time
-
66
-
ns
tf
Fall Time
-
50
-
ns
tOFF
Turn-Off Time
-
-
173
ns
145
-
-
µs
VDD = 15V, ID = 9A
VGS = 10V, RGS = 3.9Ω
Unclamped Inductive Switching
tAV
Avalanche Time
ID = 2.2A, L = 3mH
Drain-Source Diode Characteristics
ISD = 9A
-
-
1.25
V
ISD = 4A
-
-
1.0
V
Reverse Recovery Time
ISD = 9A, dISD/dt = 100A/µs
-
-
40
ns
Reverse Recovered Charge
ISD = 9A, dISD/dt = 100A/µs
-
-
38
nC
VSD
Source to Drain Diode Voltage
trr
QRR
©2002 Fairchild Semiconductor Corporation
ISL9N305ASK8T Rev A1
ISL9N305ASK8T
Electrical Characteristics TA = 25°C unless otherwise noted
ISL9N305ASK8T
Typical Characteristic
20
1.2
VGS = 10V, RθJA = 50oC/W
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.0
0.8
0.6
0.4
15
10
VGS = 4.5V, RθJA = 189oC/W
5
0.2
0
0
0
25
50
75
125
100
TA , AMBIENT TEMPERATURE
25
150
50
75
100
125
150
Ta, CASE TEMPERATURE (oC)
(oC)
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
3
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
ZθJA, NORMALIZED
THERMAL IMPEDANCE
1
RθJA = 50oC/W
0.1
PDM
t1
0.01
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
SINGLE PULSE
0.001
10-5
10-4
10-3
10-2
10-1
100
101
102
103
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
2000
IDM , PEAK CURRENT (A)
RθJA = 50oC/W
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
1000
TA = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
I = I25
VGS = 4.5V
150 - TA
125
100
10
10-5
10-4
10-3
10-2
10-1
t, PULSE WIDTH (s)
100
101
102
103
Figure 4. Peak Current Capability
©2002 Fairchild Semiconductor Corporation
ISL9N305ASK8T Rev A1
ISL9N305ASK8T
Typical Characteristic (Continued)
50
50
30
TJ = 25oC
20
TJ = 150oC
TJ = -55oC
10
0
1
2
3
4
VGS = 3.5V
30
VGS = 3V
20
10
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TA = 25oC
0
0
0.2
VGS , GATE TO SOURCE VOLTAGE (V)
0.6
0.4
0.6
1.0
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure 6. Saturation Characteristics
1.8
20
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
VGS = 4.5V
40
ID, DRAIN CURRENT (A)
40
ID , DRAIN CURRENT (A)
VGS = 10V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
ID = 18A
15
10
ID = 1A
5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
1.5
1.2
0.9
VGS = 10V, ID = 18A
0.6
0
2
4
6
8
-80
10
-40
Figure 7. Drain To Source On Resistance vs Gate
Voltage And Drain Current
40
80
120
160
Figure 8. Normalized Drain to Source On
Resistance vs Junction Temperature
1.2
1.4
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
VGS = VDS, ID = 250µA
1.2
NORMALIZED GATE
THRESHOLD VOLTAGE
0
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
1.0
0.8
0.6
ID = 250µA
1.1
1.0
0.9
0.4
-80
-40
0
40
80
TJ, JUNCTION TEMPERATURE
120
160
(oC)
Figure 9. Noramlized Gate Threshold Voltage vs
Junction Temperature
©2002 Fairchild Semiconductor Corporation
-80
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
Figure 10. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
ISL9N305ASK8T Rev A1
ISL9N305ASK8T
Typical Characteristic (Continued)
6000
10
VGS , GATE TO SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
CISS = CGS + CGD
COSS ≅ CGS + CGD
1000
CRSS = CGD
VGS = 0V, f = 1MHz
100
VDD = 15V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 18A
ID = 1A
2
0
0.1
1
30
10
0
25
VDS , DRAIN TO SOURCE VOLTAGE (V)
50
75
Qg, GATE CHARGE (nC)
Figure 11. Capacitance vs Drain to Source
Voltage
Figure 12. Gate Charge Waveforms for Constant
Gate Currents
600
300
VGS = 4.5V, VDD = 15V, ID = 9A
VGS = 10V, VDD = 15V, ID = 9A
tr
200
tf
td(ON)
100
SWITCHING TIME (ns)
SWITCHING TIME (ns)
td(OFF)
td(OFF)
400
tf
200
tr
td(ON)
0
0
0
10
20
30
40
0
50
10
20
30
40
50
RGS, GATE TO SOURCE RESISTANCE (Ω)
RGS, GATE TO SOURCE RESISTANCE (Ω)
Figure 13. Switching Time vs Gate Resistance
Figure 14. Switching Time vs Gate Resistance
Test Circuits and Waveforms
VDS
BVDSS
tP
VDS
L
IAS
VDD
VARY tP TO OBTAIN
REQUIRED PEAK IAS
+
RG
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
Figure 15. Unclamped Energy Test Circuit
©2002 Fairchild Semiconductor Corporation
Figure 16. Unclamped Energy Waveforms
ISL9N305ASK8T Rev A1
VDS
VDD
Qg(TOT)
RL
VDS
VGS = 10V
VGS
Qg(5)
+
VDD
VGS = 5V
VGS
-
VGS = 1V
DUT
0
Ig(REF)
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON
tOFF
td(ON)
td(OFF)
tr
RL
VDS
tf
90%
90%
+
VGS
VDD
-
10%
0
10%
DUT
90%
RGS
VGS
50%
50%
PULSE WIDTH
VGS
0
Figure 19. Switching Time Test Circuit
©2002 Fairchild Semiconductor Corporation
10%
Figure 20. Switching Time Waveforms
ISL9N305ASK8T Rev A1
ISL9N305ASK8T
Test Circuits and Waveforms (Continued)
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
application.
Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
P
DM
(T
–T )
JM
A
= ----------------------------RθJA
(EQ. 1)
In using surface mount devices such as the SO8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of PDM is complex
and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
PDM.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2. RθJA is defined as the natural log of the area
times a coefficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
R θ JA = 83.2 – 23.6 ×
ZθJA, THERMAL
IMPEDANCE (oC/W)
150
120
90
(EQ. 2)
The transient thermal impedance (ZθJA) is also effected by
varied top copper board area. Figure 22 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package.
Therefore, CTHERM1 through CTHERM5 and RTHERM1
through RTHERM5 remain constant for each of the thermal
models. A listing of the model component values is available
in Table 1.
240
RθJA = 83.2 - 23.6*ln(AREA)
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Displayed on the curve are RθJA values listed in the
Electrical Specifications table. The points were chosen to
ln ( Area )
RθJA (oC/W)
200
189oC/W - 0.0115in2
160
152oC/W - 0.054in2
120
80
0.01
0.1
1.0
AREA, TOP COPPER AREA (in2)
Figure 21. Thermal Resistance vs Mounting
Pad Area
COPPER BOARD AREA - DESCENDING ORDER
0.04 in2
0.28 in2
0.52 in2
0.76 in2
1.00 in2
60
30
0
10-1
100
101
102
103
t, RECTANGULAR PULSE DURATION (s)
Figure 22. Thermal Impedance vs Mounting Pad Area
©2002 Fairchild Semiconductor Corporation
ISL9N305ASK8T Rev A1
ISL9N305ASK8T
Thermal Resistance vs. Mounting Pad Area
rev May 2001
LDRAIN
DPLCAP
10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
RSLC2
5
51
LGATE
EVTEMP
RGATE +
18 22
9
20
21
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1e-3
RGATE 9 20 2.34
RLDRAIN 2 5 10
RLGATE 1 9 12.9
RLSOURCE 3 7 1.75
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 3.3e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
EBREAK
16
+
17
18
-
DBODY
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
S1A
S1B
S2A
S2B
EVTHRES
+ 19 8
+
GATE
1
11
50
RDRAIN
6
8
ESG
DBREAK
ESLC
-
LDRAIN 2 5 1e-9
LGATE 1 9 1.29e-9
LSOURCE 3 7 1.75e-10
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 32.8
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
DRAIN
2
5
+
.SUBCKT ISL9N305ASK8 2 1 3 ;
CA 12 8 2e-9
CB 15 14 2.3e-9
CIN 6 8 4.1e-9
RLSOURCE
S1A
12
S2A
13
8
14
13
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
VBAT
5
8
EDS
-
IT
14
+
+
-
+
8
22
RVTHRES
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*150),5))}
.MODEL DBODYMOD D (IS = 2e-11 N = 1.04 RS = 4e-3 TRS1 = 1e-3 TRS2 = 1e-6 XTI=2 CJO = 1.4e-9 TT = 9e-10 M = 0.45
XTI=2)
.MODEL DBREAKMOD D (RS = 0.22 TRS1 = 8e-4 TRS2 = -8.9e-6)
.MODEL DPLCAPMOD D (CJO = 1.27e-9 IS = 1e-30 N = 10 M = 0.46)
.MODEL MMEDMOD NMOS (VTO = 1.87 KP = 10 IS=1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.34)
.MODEL MSTROMOD NMOS (VTO = 2.25 KP = 140 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.5 KP = 0.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 23.4 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 9.2e-4 TC2 = 0)
.MODEL RDRAINMOD RES (TC1 = 1.2e-2 TC2 = 3e-5)
.MODEL RSLCMOD RES (TC1 = 1e-3 TC2 = 1e-7)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.6e-3 TC2 = -8e-6)
.MODEL RVTEMPMOD RES (TC1 = -2.9e-3 TC2 = 1e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.0 VOFF= -2.0)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.0 VOFF= -3.0)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF= 0.2)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.2 VOFF= -0.5)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2002 Fairchild Semiconductor Corporation
ISL9N305ASK8T Rev A1
ISL9N305ASK8T
PSPICE Electrical Model
ISL9N305ASK8T
SABER Electrical Model
REV May 20001
template isl9n305ask8 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 2e-11, nl=1.04, rs = 4e-3, trs1 = 1e-3, trs2 = 1e-6, xti=2, cjo = 1.4e-9, tt = 9e-10, m = 0.45)
dp..model dbreakmod = (rs = 0.22, trs1 = 8e-4, trs2 = -8.9e-6)
dp..model dplcapmod = (cjo = 1.29e-9, isl=10e-30, nl=10, m=0.46)
m..model mmedmod = (type=_n, vto = 1.87, kp=10, is=1e-30, tox=1)
m..model mstrongmod = (type=_n, vto = 2.25, kp = 140, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.5, kp = 0.1, is = 1e-30, tox = 1, rs=0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -3.0, voff = -2.0)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.0, voff = -3.0)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.2)
LDRAIN
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.5)
DPLCAP
c.ca n12 n8 = 2e-9
c.cb n15 n14 = 2.3e-9
c.cin n6 n8 = 4.1e-9
5
10
DRAIN
2
RLDRAIN
RSLC1
51
RSLC2
ISCL
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 1.29e-9
l.lsource n3 n7 = 1.75e-10
RDRAIN
6
8
ESG
i.it n8 n17 = 1
GATE
1
EVTEMP
RGATE + 18 22
9
20
6
EBREAK
+
17
18
-
MMED
RLGATE
CIN
8
LSOURCE
7
RSOURCE
S1A
12
13
8
S2A
14
13
S1B
CA
DBODY
MWEAK
MSTRO
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 9.2e-4, tc2 = 0
res.rdrain n50 n16 = 1e-3, tc1 = 1.2e-2, tc2 = 3e-5
res.rgate n9 n20 = 2.34
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 12.9
res.rlsource n3 n7 = 1.75
res.rslc1 n5 n51= 1e-6, tc1 = 1e-3, tc2 =1e-7
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 3.3e-3, tc1 = 1e-3, tc2 =1e-6
res.rvtemp n18 n19 = 1, tc1 = -2.9e-3, tc2 = 1e-7
res.rvthres n22 n8 = 1, tc1 = -1.6e-3, tc2 = -8e-6
11
EVTHRES
16
21
+ 19 8
+
LGATE
DBREAK
50
-
RLSOURCE
RBREAK
15
17
18
RVTEMP
S2B
13
CB
+
+
6
8
EGS
-
SOURCE
3
19
IT
14
VBAT
5
8
EDS
-
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 32.8
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/150))** 5))
}
}
©2002 Fairchild Semiconductor Corporation
ISL9N305ASK8T Rev A1
th
REV 18 May 2001
ISL9N305ASK8_76T
Copper Area = 0.76 in2
CTHERM1 th 8 2.0e-3
CTHERM2 8 7 5.0e-3
CTHERM3 7 6 1.0e-2
CTHERM4 6 5 4.0e-2
CTHERM5 5 4 9.0e-2
CTHERM6 4 3 0.2
CTHERM7 3 2 1.0
CTHERM8 2 tl 3.0
JUNCTION
RTHERM1
CTHERM1
8
RTHERM2
RTHERM1 th 8 0.1
RTHERM2 8 7 0.5
RTHERM3 7 6 1.0
RTHERM4 6 5 5.0
RTHERM5 5 4 8.0
RTHERM6 4 3 13
RTHERM7 3 2 19
RTHERM8 2 tl 29.7
CTHERM2
7
RTHERM3
CTHERM3
6
SABER Thermal Model
RTHERM4
CTHERM4
2
Copper Area = 0.76 in
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 = 2.0e-3
ctherm.ctherm2 8 7 = 5.0e-3
ctherm.ctherm3 7 6 = 1.0e-2
ctherm.ctherm4 6 5 = 4.0e-2
ctherm.ctherm5 5 4 = 9.0e-2
ctherm.ctherm6 4 3 = 0.2
ctherm.ctherm7 3 2 = 1.0
ctherm.ctherm8 2 tl = 3.0
5
RTHERM5
CTHERM5
4
RTHERM6
CTHERM6
3
rtherm.rtherm1 th 8 = 0.1
rtherm.rtherm2 8 7 = 0.5
rtherm.rtherm3 7 6 = 1.0
rtherm.rtherm4 6 5 = 5.0
rtherm.rtherm5 5 4 = 8.0
rtherm.rtherm6 4 3 = 13
rtherm.rtherm7 3 2 = 19
rtherm.rtherm8 2 tl = 29.7
}
RTHERM7
CTHERM7
2
CTHERM8
RTHERM8
tl
CASE
TABLE 1. THERMAL MODELS
0.04 in2
0.28 in2
0.52 in2
0.76 in2
1.0 in2
CTHERM6
1.2e-1
1.5e-1
2.0e-1
2.0e-1
2.0e-1
CTHERM7
0.5
1.0
1.0
1.0
1.0
CTHERM8
1.3
2.8
3.0
3.0
3.0
RTHERM6
26
20
15
13
12
RTHERM7
39
24
21
19
18
RTHERM8
55
38.7
31.3
29.7
25
COMPONANT
©2002 Fairchild Semiconductor Corporation
ISL9N305ASK8T Rev A1
ISL9N305ASK8T
SPICE Thermal Model
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