CYPRESS W134MHT

W134M/W134S
Direct Rambus™ Clock Generator
Features
Description
• Differential clock source for Direct Rambus™ memory
subsystem for up to 800-MHz data transfer rate
• Provide synchronization flexibility: the Rambus®
Channel can optionally be synchronous to an external
system or processor clock
The Cypress W134M/W134S provides the differential clock
signals for a Direct Rambus memory subsystem. It includes
signals to synchronize the Direct Rambus Channel clock to an
external system clock but can also be used in systems that do
not require synchronization of the Rambus clock.
• Power-managed output allows Rambus Channel clock
to be turned off to minimize power consumption for
mobile applications
• Works with Cypress CY2210, W133, W158, W159, W161,
and W167 to support Intel® architecture platforms
• Low-power CMOS design packaged in a 24-pin QSOP
(150-mil SSOP) package
Block Diagram
REFCLK
MULT0:1
PCLKM
Pin Configuration
PLL
Phase
Alignment
CLK
Output
Logic
1
24
S0
2
23
S1
VDD
3
22
VDD
GND
4
21
GND
GND
5
20
CLK
PCLKM
6
19
NC
SYNCLKN
7
18
CLKB
GND
8
17
GND
CLKB
SYNCLKN
S0:1
VDDIR
REFCLK
VDD
9
16
VDD
VDDIPD
10
15
MULT0
STOPB
11
14
MULT1
PWRDNB
12
13
GND
Test
Logic
STOPB
Cypress Semiconductor Corporation
Document #: 38-07426 Rev. *C
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised June 1, 2005
W134M/W134S
Pin Definitions
Pin Name
No.
Type
Description
REFCLK
2
I
Reference Clock Input. Reference clock input, normally supplied by a system frequency
synthesizer (Cypress W133).
PCLKM
6
I
Phase Detector Input. The phase difference between this signal and SYNCLKN is used
to synchronize the Rambus Channel Clock with the system clock. Both PCLKM and
SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If Gear Ratio
Logic is not used, this pin would be connected to Ground.
SYNCLKN
7
I
Phase Detector Input. The phase difference between this signal and PCLKM is used to
synchronize the Rambus Channel Clock with the system clock. Both PCLKM and
SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If Gear Ratio
Logic is not used, this pin would be connected to Ground.
STOPB
11
I
Clock Output Enable. When this input is driven to active LOW, it disables the differential
Rambus Channel clocks.
PWRDNB
12
I
Active LOW Power-down. When this input is driven to active LOW, it disables the differential Rambus Channel clocks and places the W134M/W134S in power-down mode.
MULT 0:1
15, 14
I
PLL Multiplier Select. These inputs select the PLL prescaler and feedback dividers to
determine the multiply ratio for the PLL for the input REFCLK.
MULT0
0
0
1
1
W134M
PLL/REFCLK
4.5
6
8
5.333
MULT1
0
1
1
0
W134S
PLL/REFCLK
4
6
8
5.333
CLK, CLKB
20, 18
O
Complementary Output Clock. Differential Rambus Channel clock outputs.
S0, S1
24, 23
I
Mode Control Input. These inputs control the operating mode of the W134M/W134S.
S0
0
0
1
1
NC
19
–
S1
0
1
0
1
MODE
Normal
Output Enable Test
Bypass
Test
No Connect
VDDIR
1
RefV Reference for REFCLK. Voltage reference for input reference clock.
VDDIPD
10
RefV Reference for Phase Detector. Voltage reference for phase detector inputs and StopB.
VDD
3, 9, 16, 22
P
Power Connection. Power supply for core logic and output buffers. Connected to 3.3V
supply.
GND
4, 5, 8, 13, 17,
21
G
Ground Connection. Connect all ground pins to the common system ground plane.
Phase
Align
PLL
Busclk
D
RAC
Synclk/N
RMC
W134M/W134S
Refclk
Pclk/M
W133
W158
W159
W161
W167
CY2210
M
N
Pclk
Gear
4
DLL
Synclk
Ratio
Logic
Figure 1. DDLL System Architecture
Document #: 38-07426 Rev. *C
Page 2 of 12
W134M/W134S
Key Specifications
(Rambus Channel). At the mid-point of the channel, the RAC
senses Busclk using its own DLL for clock alignment, followed
by a fixed divide-by-4 that generates Synclk.
Supply Voltage: ...................................... VDD = 3.3V±0.165V
Pclk is the clock used in the memory controller (RMC) in the
core logic, and Synclk is the clock used at the core logic
interface of the RAC. The DDLL together with the Gear Ratio
Logic enables users to exchange data directly from the Pclk
domain to the Synclk domain without incurring additional
latency for synchronization. In general, Pclk and Synclk can
be of different frequencies, so the Gear Ratio Logic must
select the appropriate M and N dividers such that the
frequencies of Pclk/M and Synclk/N are equal. In one interesting example, Pclk = 133 MHz, Synclk = 100 MHz, and
M = 4 while N = 3, giving Pclk/M = Synclk/N = 33 MHz. This
example of the clock waveforms with the Gear Ratio Logic is
shown in Figure 2.
Operating Temperature: ................................... 0°C to +70°C
Input Threshold: .................................................. 1.5V typical
Maximum Input Voltage: ........................................ VDD+0.5V
Maximum Input Frequency: .....................................100 MHz
Output Duty Cycle:...................................40/60% worst case
Output Type: ...........................Rambus signaling level (RSL)
DDLL System Architecture and Gear Ratio
Logic
Figure 1 shows the Distributed Delay Lock Loop (DDLL)
system architecture, including the main system clock source,
the Direct Rambus clock generator (DRCG), and the core logic
that contains the Rambus Access Cell (RAC), the Rambus
Memory Controller (RMC), and the Gear Ratio Logic. (This
diagram abstractly represents the differential clocks as a
single Busclk wire.)
The output clocks from the Gear Ratio Logic, Pclk/M, and
Synclk/N, are output from the core logic and routed to the
DRCG Phase Detector inputs. The routing of Pclk/M and
Synclk/N must be matched in the core logic as well as on the
board.
After comparing the phase of Pclk/M vs. Synclk/N, the DRCG
Phase Detector drives a phase aligner that adjusts the phase
of the DRCG output clock, Busclk. Since everything else in the
distributed loop is fixed delay, adjusting Busclk adjusts the
phase of Synclk and thus the phase of Synclk/N. In this
manner the distributed loop adjusts the phase of Synclk/N to
match that of Pclk/M, nulling the phase error at the input of the
DRCG Phase Detector. When the clocks are aligned, data can
be exchanged directly from the Pclk domain to the Synclk
domain.
The purpose of the DDLL is to frequency-lock and phase-align
the core logic and Rambus clocks (Pclk and Synclk) at the
RMC/RAC boundary in order to allow data transfers without
incurring additional latency. In the DDLL architecture, a PLL is
used to generate the desired Busclk frequency, while a
distributed loop forms a DLL to align the phase of Pclk and
Synclk at the RMC/RAC boundary.
The main clock source drives the system clock (Pclk) to the
core logic, and also drives the reference clock (Refclk) to the
DRCG. For typical Intel architecture platforms, Refclk will be
half the CPU front side bus frequency. A PLL inside the DRCG
multiplies Refclk to generate the desired frequency for Busclk,
and Busclk is driven through a terminated transmission line
Table 1 shows the combinations of Pclk and Busclk
frequencies of greatest interest, organized by Gear Ratio.
Table 1. Supported Pclk and Busclk Frequencies, by Gear Ratio
Gear Ratio and Busclk
Pclk
2.0
1.5
1.33
67 MHz
1.0
267 MHz
100 MHz
300 MHz
133 MHz
267 MHz
150 MHz
356 MHz
400 MHz
400 MHz
400 MHz
200 MHz
400 MHz
Pclk
Synclk
Pclk/M =
Synclk/N
Figure 2. Gear Ratio Timing Diagram
Document #: 38-07426 Rev. *C
Page 3 of 12
W134M/W134S
S0/S1 StopB
W133
W158
W159
W161
W167
CY2210
Phase
Align
PLL
Busclk
D
RAC
Synclk/N
Pclk/M
RMC
W134M/W134S
Refclk
M
N
Pclk
Gear
4
DLL
Synclk
Ratio
Logic
Figure 3. DDLL Including Details of DRCG
Figure 3 shows more details of the DDLL system architecture,
including the DRCG output enable and bypass modes.
Phase Detector Signals
The DRCG Phase Detector receives two inputs from the core
logic, PclkM (Pclk/M) and SynclkN (Synclk/N). The M and N
dividers in the core logic are chosen so that the frequencies of
PclkM and SynclkN are identical. The Phase Detector detects
the phase difference between the two input clocks, and drives
the DRCG Phase Aligner to null the input phase error through
the distributed loop. When the loop is locked, the input phase
error between PclkM and SynclkN is within the specification
tERR,PD given in the Device Characteristics table after the lock
time given in the State Transition Section.
The Phase Detector aligns the rising edge of PclkM to the
rising edge of SynclkN. The duty cycle of the phase detector
input clocks will be within the specification DCIN,PD given in the
Operating Conditions table. Because the duty cycles of the two
phase detector input clocks will not necessarily be identical,
the falling edges of PclkM and SynclkN may not be aligned
when the rising edges are aligned.
The voltage levels of the PclkM and SynclkN signals are determined by the controller. The pin VDDIPD is used as the voltage
reference for the phase detector inputs and should be
connected to the output voltage supply of the controller. In
some applications, the DRCG PLL output clock will be used
directly, by bypassing the Phase Aligner. If PclkM and SynclkN
are not used, those inputs must be grounded.
Selection Logic
Table 2 shows the logic for selecting the PLL prescaler and
feedback dividers to determine the multiply ratio for the PLL
from the input Refclk. Divider A sets the feedback and divider
B sets the prescaler, so the PLL output clock frequency is set
by: PLLclk = Refclk*A/B.
Document #: 38-07426 Rev. *C
Table 2. PLL Divider Selection
W134M
W134S
Mult0
Mult1
A
B
A
B
0
0
9
2
4
1
0
1
6
1
6
1
1
1
8
1
8
1
1
0
16
3
16
3
Table 3 shows the logic for enabling the clock outputs, using
the StopB input signal. When StopB is HIGH, the DRCG is in
its normal mode, and Clk and ClkB are complementary outputs
following the Phase Aligner output (PAclk). When StopB is
LOW, the DRCG is in the Clk Stop mode, the output clock
drivers are disabled (set to Hi-Z), and the Clk and ClkB settle
to the DC voltage VX,STOP as given in the Device Characteristics table. The level of VX,STOP is set by an external resistor
network.
Table 3. Clock Stop Mode Selection
Mode
StopB
Clk
ClkB
Normal
1
PAclk
PAclkB
Clk Stop
0
VX,STOP
VX,STOP
Table 4 shows the logic for selecting the Bypass and Test
modes. The select bits, S0 and S1, control the selection of
these modes. The Bypass mode brings out the full-speed PLL
output clock, bypassing the Phase Aligner. The Test mode
brings the Refclk input all the way to the output, bypassing
both the PLL and the Phase Aligner. In the Output Test mode
(OE), both the Clk and ClkB outputs are put into a
high-impedance state (Hi-Z). This can be used for component
testing and for board-level testing.
Page 4 of 12
W134M/W134S
Normal
0
0
Gnd
PAclk
PAclkB
and S1 must be stable before power is applied to the device,
and can only be changed in Power-down mode (PwrDnB = 0).
The reference inputs, VDDR and VDDPD, may remain on or may
be grounded during the Power-down mode.
Table 6. Examples of Frequencies, Dividers, and Gear Ratios
Output Test (OE)
0
1
–
Hi-Z
Hi-Z
Bypass
1
0
PLLclk
PLLclk
PLLclkB
Pclk Refclk Busclk Synclk A B M N Ratio [email protected]
Test
1
1
Refclk
Refclk
RefclkB
Table 4. Bypass and Test Mode Selection
Mode
S0
S1
Bypclk
(int.)
Clk
ClkB
Table 5 shows the logic for selecting the Power-down mode,
using the PwrDnB input signal. PwrDnB is active LOW
(enabled when 0). When PwrDnB is disabled, the DRCG is in
its normal mode. When PwrDnB is enabled, the DRCG is put
into a powered-off state, and the Clk and ClkB outputs are
three-stated.
Table 5. Power-down Mode Selection
Mode
PwrDnB
Clk
ClkB
Normal
1
PAclk
PAclkB
Power-down
0
GND
GND
67
33
267
67
8 1 2 2
1.0
33
100
50
300
75
6 1 8 6
1.33
12.5
100
50
400
100
8 1 4 4
1.0
25
133
67
267
67
4 1 4 2
2.0
33
133
67
400
100
6 1 8 6
1.33
16.7
The control signals Mult0 and Mult1 can be used in two ways.
If they are changed during Power-down mode, then the
Power-down transition timings determine the settling time of
the DRCG. However, the Mult0 and Mult1 control signals can
also be changed during Normal mode. When the Mult control
signals are “hot-swapped” in this manner, the Mult transition
timings determine the settling time of the DRCG.
In Normal mode, the clock source is on, and the output is
enabled.
Table of Frequencies and Gear Ratios
Table 6 shows several supported Pclk and Busclk
frequencies, the corresponding A and B dividers required in
the DRCG PLL, and the corresponding M and N dividers in the
gear ratio logic. The column Ratio gives the Gear Ratio as
defined Pclk/Synclk (same as M and N). The column [email protected]
gives the divided down frequency (in MHz) at the Phase
Detector, where [email protected] = Pclk/M = Synclk/N.
State Transitions
The clock source has three fundamental operating states.
Figure 4 shows the state diagram with each transition labelled
A through H. Note that the clock source output may NOT be
glitch-free during state transitions.
Upon powering up the device, the device can enter any state,
depending on the settings of the control signals, PwrDnB and
StopB.
In Power-down mode, the clock source is powered down with
the control signal, PwrDnB, equal to 0. The control signals S0
VDD Turn-On
M
Table 7 lists the control signals for each state.
Table 7. Control Signals for Clock Source States
State
Power-down
Clock Stop
Normal
PwrDnB
0
1
1
StopB
X
0
1
Clock
Source
OFF
ON
ON
Output
Buffer
Ground
Disabled
Enabled
Figure 5 shows the timing diagrams for the various transitions
between states, and Table 8 specifies the latencies of each
state transition. Note that these transition latencies assume
the following.
Refclk input has settled and meets specification shown in the
Operating Conditions table.
The Mult0, Mult1, S0 and S1 control signals are stable.
VDD Turn-On
J
G
L
Test
K
VDD Turn-On
N
B
Power-Down
Normal
F
A
E
D
VDD Turn-On
Clk Stop
C
H
Figure 4. Clock Source State Diagram
Document #: 38-07426 Rev. *C
Page 5 of 12
W134M/W134S
Timing Diagrams
Power-down Exit and Entry
PwrDnB
tPOWERDN
tPOWERUP
Clk/ClkB
Output Enable Control
tON
StopB
tSTOP
tCLKON
tCLKOFF
tCLKSETL
Clk/ClkB
Output clock Clock enabled
not specified and glitch-free
glitches may
occur
Clock output settled within
50 ps of the phase before
disabled
Figure 5. State Transition Timing Diagrams
Mult0 and/or Mult1
tMULT
Clk/ClkB
Figure 6. Multiply Transition Timing
Table 8. State Transition Latency Specifications
Transition Latency
Transition
From
To
Parameter
Max.
A
Power-down
Normal
tPOWERUP
3 ms
Time from PwrDnB to Clk/ClkB output settled
(excluding tDISTLOCK).
C
Power-down
Clk Stop
tPOWERUP
3 ms
Time from PwrDnB until the internal PLL and clock has
turned ON and settled.
K
Power-down
Test
tPOWERUP
3 ms
Time from PwrDnB to Clk/ClkB output settled
(excluding tDISTLOCK).
G
VDD ON
Normal
tPOWERUP
3 ms
Time from VDD is applied and settled until Clk/ClkB
output settled (excluding tDISTLOCK).
H
VDD ON
Clk Stop
tPOWERUP
3 ms
Time from VDD is applied and settled until internal PLL
and clock has turned ON and settled.
M
VDD ON
Test
tPOWERUP
3 ms
Time from VDD is applied and settled until internal PLL
and clock has turned ON and settled.
J
Normal
Normal
tMULT
1 ms
Time from when Mult0 or Mult1 changed until Clk/ClkB
output resettled (excluding tDISTLOCK).
Document #: 38-07426 Rev. *C
Description
Page 6 of 12
W134M/W134S
Table 8. State Transition Latency Specifications (continued)
Transition Latency
Transition
From
To
Parameter
Max.
E
Clk Stop
Normal
tCLKON
10 ns
E
Clk Stop
Normal
tCLKSETL
F
Normal
Clk Stop
tCLKOFF
5 ns
Time from StopB to Clk/ClkB output disabled.
L
Test
Normal
tCTL
3 ms
Time from when S0 or S1 is changed until CLK/CLKB
output has resettled (excluding tDISTLOCK).
N
Normal
Test
tCTL
3 ms
Time from when S0 or S1 is changed until CLK/CLKB
output has resettled (excluding tDISTLOCK).
1 ms
Time from PwrDnB to the device in Power-down.
B,D
Description
Time from StopB until Clk/ClkB provides glitch-free
clock edges.
20 cycles Time from StopB to Clk/ClkB output settled to within 50
ps of the phase before CLK/CLKB was disabled.
Normal or Clk Stop Power-down tPOWERDN
Figure 5 shows that the Clk Stop to Normal transition goes
through three phases. During tCLKON, the clock output is not
specified and can have glitches. For tCLKON < t < tCLKSETL, the
clock output is enabled and must be glitch-free. For
t > tCLKSETL, the clock output phase must be settled to within
50 ps of the phase before the clock output was disabled. At
this time, the clock output must also meet the voltage and
timing specifications of the Device Characteristics table. The
outputs are in a high-impedance state during the Clk Stop
mode.
Table 9. Distributed Loop Lock Time Specification
Parameter
Description
tDISTLOCK
Time from when Clk/ClkB output is settled to when the phase error between SynclkN and
PclkM falls within the tERR,PD spec in Table .
Min.
Max.
Unit
5
ms
Min.
Max.
Unit
Table 10.Supply and Reference Current Specification
Parameter
Description
IPOWERDOWN
“Supply” current in Power-down state (PwrDnB 1 = 0)
–
250
µA
ICLKSTOP
“Supply” current in Clk Stop state (StopB = 0)
–
65
mA
INORMAL
“Supply” current in Normal state (StopB = 1, PwrDnB = 1)
–
100
mA
IREF,PWDN
Current at VDDIR or VDDIPD reference pin in Power-down state (PwrDnB = 0)
–
50
µA
IREF,NORM
Current at VDDIR or VDDIPD reference pin in Normal or Clk Stop state (PwrDnB = 1)
–
2
mA
Document #: 38-07426 Rev. *C
Page 7 of 12
W134M/W134S
Absolute Maximum Conditions[1]
Parameter
Description
Min.
Max.
Unit
VDD, ABS
Max. voltage on VDD with respect to ground
–0.5
4.0
V
VI, ABS
Max. voltage on any pin with respect ground
–0.5
VDD + 0.5
V
External Component Values[2]
Parameter
Description
Min.
Max.
Unit
39
±5%
Ω
RS
Serial Resistor
RP
Parallel Resistor
51
±5%
Ω
CF
Edge Rate Filter Capacitor
4–15[3]
±10%
pF
CMID
AC Ground Capacitor
470 pF
0.1 µF
±20%
Operating Conditions[4]
Parameter
Description
Min.
Max.
Unit
3.135
3.465
V
Ambient Operating Temperature
0
70
°C
Refclk Input Cycle Time
10
40
ns
VDD
Supply Voltage
TA
tCYCLE,IN
Jitter[5]
tJ,IN
Input Cycle-to-Cycle
–
250
ps
DCIN
Input Duty Cycle over 10,000 Cycles
40
60
%tCYCLE
FMIN
Input Frequency of Modulation
30
33
kHz
PMIN[6]
Modulation Index for Triangular Modulation
–
0.6
%
%
ns
Modulation Index for Non-Triangular Modulation
–
0.5[8]
tCYCLE,PD
Phase Detector Input Cycle Time at PclkM & SynclkN
30
100
tERR,INIT
Initial Phase error at Phase Detector Inputs
–0.5
0.5
tCYCLE,PD
DCIN,PD
Phase Detector Input Duty Cycle over 10,000 Cycles
25
75
tCYCLE,PD
tI,SR
Input Slew Rate (measured at 20%-80% of input voltage) for PclkM,
SynclkN, and Refclk
1
4
V/ns
CIN,PD
Input Capacitance at PclkM, SynclkN, and Refclk[7]
–
7
pF
DCIN,PD
Input Capacitance matching at PclkM and SynclkN[7]
–
0.5
pF
CIN,CMOS
Input Capacitance at CMOS pins (excluding PclkM, SynclkN, and
Refclk)[7]
–
10
pF
VIL
Input (CMOS) Signal Low Voltage
–
0.3
VDD
VIH
Input (CMOS) Signal High Voltage
0.7
–
VDD
VIL,R
Refclk input Low Voltage
–
0.3
VDDIR
VIH,R
Refclk input High Voltage
0.7
–
VDDIR
VIL,PD
Input Signal Low Voltage for PD Inputs and StopB
–
0.3
VDDIPD
VIH,PD
Input Signal High Voltage for PD Inputs and StopB
0.7
–
VDDIPD
VDDIR
Input Supply Reference for Refclk
1.235
3.465
V
VDDIPD
Input Supply Reference for PD Inputs
1.235
2.625
V
Notes:
1. Represents stress ratings only, and functional operation at the maximums is not guaranteed.
2. Gives the nominal values of the external components and their maximum acceptable tolerance, assuming ZCH = 28Ω.
3. Do not populate CF. Leave pads for future use.
4. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
5. Refclk jitter measured at VDDIR (nom)/2.
6. If input modulation is used: input modulation is allowed but not required.
7. Capacitance measured at Freq=1 MHz, DC bias = 0.9V and VAC < 100 mV.
8. The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew, which cannot exceed the skew
generated by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about 0.5%.
Document #: 38-07426 Rev. *C
Page 8 of 12
W134M/W134S
Device Characteristics
Parameter
Description
tCYCLE
Clock Cycle Time
tJ
Cycle-to-Cycle Jitter at Clk/ClkB[9]
Total Jitter over 2, 3, or 4 Clock
Cycles[9]
266-MHz Cycle-to-Cycle Jitter[10]
266-MHz Total Jitter over 2, 3, or 4 Clock
Cycles[10]
Min.
Max.
Unit
2.5
3.75
ns
–
60
ps
–
100
ps
–
100
ps
–
160
ps
1
–
ps
tSTEP
Phase Aligner Phase Step Size (at Clk/ClkB)
tERR,PD
Phase Detector Phase Error for Distributed Loop Measured at
PclkM-SynclkN (rising edges) (does not include clock jitter)
–100
100
ps
tERR,SSC
PLL Output Phase Error when Tracking SSC
–100
100
ps
VX,STOP
Output Voltage during Clk Stop (StopB=0)
1.1
2.0
V
VX
Differential Output Crossing-Point Voltage
1.3
1.8
V
VCOS
Output Voltage Swing (p-p single-ended)[11]
0.4
0.6
V
VOH
Output High Voltage
–
2.0
V
VOL
Output Low voltage
1.0
–
V
rOUT
Output Dynamic Resistance (at pins)[12]
12
50
Ω
IOZ
Output Current during Hi-Z (S0 = 0, S1 = 1)
–
50
µA
IOZ,STOP
Output Current during Clk Stop (StopB = 0)
–
500
µA
DC
Output Duty Cycle over 10,000 Cycles
40
60
%tCYCLE
tDC,ERR
Output Cycle-to-Cycle Duty Cycle Error
–
50
ps
tR,tF
Output Rise and Fall Times (measured at 20%–80% of output voltage)
250
500
ps
tCR,CF
Difference between Output Rise and Fall Times on the Same Pin of a
Single Device (20%–80%)
–
100
ps
Notes:
9. Output Jitter spec measured at tCYCLE = 2.5 ns.
10. Output Jitter Spec measured at tCYCLE = 3.75 ns.
11. VCOS = VOH–VOL.
12. rOUT = DVO/ D IO. This is defined at the output pins.
Document #: 38-07426 Rev. *C
Page 9 of 12
W134M/W134S
Layout Example
+3.3V Supply
FB
C4
0.005 µF
G
10 µF
C3
G
VDDIR
G
G
G
G
G
G
G
VDDIPD
1
2
3
4G
5G
6
7
8G
9
10
11
12
24
23
22
G21
20
19
18
G17
46
15
14
G13
G
G
G
G
G
Internal Power Supply Plane
FB = Dale ILB1206 - 300 (300Ω @ 100 MHz)
G = VIA to GND plane layer
All Bypass cap = 0.1 Ceramic XR7
Ordering Information
Ordering Code
Package Type
W134MH
24-pin QSOP (150 mils, SSOP)
W134MHT
24-pin QSOP (150 mils, SSOP) – Tape and Reel
W134SH
24-pin QSOP (150 mils, SSOP)
W134SHT
24-pin QSOP (150 mils, SSOP) – Tape and Reel
Lead-free
CYW134MOXC
24-pin QSOP (150 mils, SSOP)
CYW134MOXCT
24-pin QSOP (150 mils, SSOP), Tape and Reel
CYW134SOXC
24-pin QSOP (150 mils, SSOP)
CYW134SOXCT
24-pin QSOP (150 mils, SSOP), Tape and Reel
Document #: 38-07426 Rev. *C
Page 10 of 12
W134M/W134S
Package Diagram
24-Lead Quarter Size Outline Q13
51-85055-*B
Direct Rambus is a trademark and Rambus is a registered trademark of Rambus Inc. Intel is a registered trademark of Intel
Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-07426 Rev. *C
Page 11 of 12
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
W134M/W134S
Document History Page
Document Title: W134M/W134S Direct Rambus™ Clock Generator
Document Number: 38-07426
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
115531
05/10/02
DSG
Change from Spec number: 38-00822 to 38-07246
*A
122927
12/14/02
RBI
Add power-up requirements to operating information
*B
131671
12/15/03
RGL
Added Lead-free to the W134M device in the ordering information table
*C
375120
See ECN
RGL
Corrected the lead-free coding
Document #: 38-07426 Rev. *C
Page 12 of 12