CY7C1018DV33 1-Mbit (128K x 8) Static RAM Functional Description[1] Features • Pin- and function-compatible with CY7C1018CV33 • High speed — tAA = 10 ns • Low Active Power — ICC = 60 mA @ 10 ns • Low CMOS Standby Power • • • • • • — ISB2 = 3 mA 2.0V Data retention Automatic power-down when deselected CMOS for optimum speed/power Center power/ground pinout Easy memory expansion with CE and OE options Available in Pb-free 32-pin 300-Mil wide Molded SOJ The CY7C1018DV33 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1018DV33 is available in Pb-free 32-pin 300-Mil wide Molded SOJ. Logic Block Diagram Pin Configuration SOJ Top View I/O0 INPUTBUFFER CE WE CE I/O0 I/O1 VCC V SS I/O1 I/O2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A0 A1 A2 A3 128K × 8 ARRAY I/O3 I/O2 I/O3 WE A4 A5 A6 A7 I/O4 I/O5 COLUMN DECODER POWER DOWN I/O6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A12 A11 A10 A9 A8 I/O7 A9 A10 A11 A12 A13 A14 A15 A16 OE Note 1. For guidelines on SRAM system designs, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05465 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 8, 2006 [+] Feedback CY7C1018DV33 Selection Guide –10 (Industrial) Unit Maximum Access Time 10 ns Maximum Operating Current 60 mA Maximum Standby Current 3 mA DC Input Voltage[2] ................................ –0.3V to VCC + 0.3V Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND[2] ... –0.3V to + 4.6V DC Voltage Applied to Outputs[2] in High-Z State .......................................–0.3V to VCC + 0.3V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Operating Range Range Ambient Temperature VCC Speed Industrial –40°C to +85°C 3.3V ± 0.3V 10 ns DC Electrical Characteristics Over the Operating Range Parameter Description –10 (Industrial) Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage Min. Max. 2.4 Voltage[2] Unit V 0.4 V 2.0 VCC + 0.3 V VIL Input LOW –0.3 0.8 V IIX Input Leakage Current GND < VI < VCC –1 +1 µA IOZ Output Leakage Current GND < VI < VCC, Output Disabled –1 +1 µA ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 100MHz 60 mA 83MHz 55 mA 66MHz 45 mA 40MHz 30 mA ISB1 Automatic CE Power-down Current—TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX 10 mA ISB2 Automatic CE Power-down Current—CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 3 mA Note 2. VIL (min.) = –2.0V and VIH(max) = VCC + 1V for pulse durations of less than 5 ns. Document #: 38-05465 Rev. *D Page 2 of 9 [+] Feedback CY7C1018DV33 Capacitance[3] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 8 pF 8 pF 400-Mil Wide SOJ Unit 57.61 °C/W 40.53 °C/W TA = 25°C, f = 1 MHz, VCC = 3.3V Thermal Resistance[3] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board AC Test Loads and Waveforms[4] ALL INPUT PULSES 3.0V Z = 50Ω 90% OUTPUT 50 Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT GND 30 pF* 90% 10% 10% 1.5V Rise Time: 1 V/ns (a) (b) Fall Time: 1 V/ns High-Z characteristics: R 317Ω 3.3V OUTPUT R2 351Ω 5 pF (c) Notes 3. Tested initially and after any design or process changes that may affect these parameters. 4. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c). Document #: 38-05465 Rev. *D Page 3 of 9 [+] Feedback CY7C1018DV33 AC Switching Characteristics Over the Operating Range [5] Parameter Description –10 (Industrial) Min. Max. Unit Read Cycle tpower[6] VCC(typical) to the first access 100 µs tRC Read Cycle Time 10 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 10 ns tDOE OE LOW to Data Valid 5 ns tLZOE OE LOW to Low-Z tHZOE OE HIGH to High-Z[7, 8] CE LOW to Low-Z[8] tHZCE CE HIGH to High-Z[7, 8] tPU[9] tPD[9] CE LOW to Power-up tLZCE Write Cycle 10 3 ns 0 ns 5 3 ns ns 5 0 CE HIGH to Power-down ns ns ns 10 ns [10, 11] tWC Write Cycle Time 10 ns tSCE CE LOW to Write End 8 ns tAW Address Set-up to Write End 8 ns tHA Address Hold from Write End 0 ns tSA Address Set-up to Write Start 0 ns tPWE WE Pulse Width 7 ns tSD Data Set-up to Write End 5 ns tHD Data Hold from Write End 0 ns 3 ns tLZWE tHZWE WE HIGH to Low-Z[8] WE LOW to High-Z[7, 8] 5 ns Notes 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. This parameter is guaranteed by design and is not tested. 10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05465 Rev. *D Page 4 of 9 [+] Feedback CY7C1018DV33 Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current tCDR [3] Chip Deselect to Data Retention Time tR[12] Operation Recovery Time Min. Max. 2 Unit V 3 VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V mA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE 3.0V VCC VDR > 2V 3.0V tR tCDR CE Switching Waveforms Read Cycle No. 1 (Address Transition Controlled)[13, 14] tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[14, 15] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tHZCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU 50% ICC 50% ISB Notes 12. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs. 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for Read cycle. 15. Address valid prior to or coincident with CE transition LOW. Document #: 38-05465 Rev. *D Page 5 of 9 [+] Feedback CY7C1018DV33 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[16, 17] tWC ADDRESS tSCE CE tSA tSCE tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[16, 17] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 18 tHZOE Notes 16. Data I/O is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 18. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05465 Rev. *D Page 6 of 9 [+] Feedback CY7C1018DV33 Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW)[11, 17] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 18 tHD DATA VALID tLZWE tHZWE Truth Table CE OE WE I/O0–I/O7 Mode Power H X X High-Z Power-down Standby (ISB) L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High-Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 10 Ordering Code CY7C1018DV33-10VXI Package Diagram 51-85041 Package Type 32-pin (300-Mil) Molded SOJ (Pb-free) Operating Range Industrial Please contact your local Cypress sales representative for availability of these parts. Document #: 38-05465 Rev. *D Page 7 of 9 [+] Feedback CY7C1018DV33 Package Diagram Figure 1. 32-pin (300-Mil) Molded SOJ (51-85041) PIN 1 I.D DIMENSIONS IN INCHES 0.330 0.292 0.340 0.305 MIN. MAX. LEAD COPLANARITY 0.004 MAX. 0.810 0.830 0.128 * 0.140 0.050 TYP. 0.026 0.032 0.014 * 0.025 MIN. 0.006 0.012 0.260 * 0.275 51-85041-*A 0.020 All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05465 Rev. *D Page 8 of 9 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1018DV33 Document History Page Document Title: CY7C1018DV33, 1-Mbit (128K x 8) Static RAM Document Number: 38-05465 REV. ECN NO. Issue Date Orig. of Change ** 201560 See ECN SWI Advance Information data sheet for C9 IPP *A 238471 See ECN RKF DC parameters modified as per EROS (Spec # 01-02165) Pb-free Offering in the Ordering Information *B 262950 See ECN RKF Added Data Retention Characteristics table Added Tpower Spec in Switching Characteristics table Shaded Ordering Information *C 307598 See ECN RKF Reduced Speed bins to -8 and -10 ns *D 520647 See ECN VKN Converted from Preliminary to Final Removed Commercial Operating range Removed 8 ns speed bin Added ICC values for the frequencies 83MHz, 66MHz and 40MHz Updated Thermal Resistance table Updated Ordering Information Table Changed Overshoot spec from VCC+2V to VCC+1V in footnote #2 Document #: 38-05465 Rev. *D Description of Change Page 9 of 9 [+] Feedback