fax id: 6007 1P AL C2 2V 10D For new designs, please refer to the PALCE22V10. PALC22V10D Flash Erasable, Reprogrammable CMOS PAL® Device Features • Advanced second-generation PAL architecture • Low power — 90 mA max. commercial (10 ns) — 130 mA max. commercial (7.5 ns) • CMOS Flash EPROM technology for electrical erasability and reprogrammability • Variable product terms — 2 x(8 through 16) product terms • User-programmable macrocell — Output polarity control — Individually selectable for registered or combinatorial operation • Up to 22 input terms and 10 outputs Additional features of the Cypress PALC22V10D include a synchronous preset and an asynchronous reset product term. These product terms are common to all macrocells, eliminating the need to dedicate standard product terms for initialization functions. The device automatically resets upon power-up. • DIP, LCC, and PLCC available — 7.5 ns commercial version 5 ns tCO 5 ns tS 7.5 ns tPD 133-MHz state machine — 10 ns military and industrial versions 6 ns tCO 6 ns tS 10 ns tPD 110-MHz state machine — 15-ns commercial and military versions — 25-ns commercial and military versions • High reliability — Proven Flash EPROM technology 100% programming and functional testing Functional Description The Cypress PALC22V10D is a CMOS Flash Erasable second-generation programmable array logic device. It is implemented with the familiar sum-of-products (AND-OR) logic structure and the programmable macrocell. The PALC22V10D is executed in a 24-pin 300-mil molded DIP, a 300-mil cerDIP, a 28-lead square ceramic leadless chip carrier, a 28-lead square plastic leaded chip carrier, and provides up to 22 inputs and 10 outputs. The 22V10D can be electrically erased and reprogrammed. The programmable macrocell pro- Cypress Semiconductor Corporation vides the capability of defining the architecture of each output individually. Each of the 10 potential outputs may be specified as “registered” or “combinatorial.” Polarity of each output may also be individually selected, allowing complete flexibility of output configuration. Further configurability is provided through “array” configurable “output enable” for each potential output. This feature allows the 10 outputs to be reconfigured as inputs on an individual basis, or alternately used as a combination I/O controlled by the programmable array. PALC22V10D features a variable product term architecture. There are 5 pairs of product term sums beginning at 8 product terms per output and incrementing by 2 to 16 product terms per output. By providing this variable structure, the PAL C 22V10D is optimized to the configurations found in a majority of applications without creating devices that burden the product term structures with unusable product terms and lower performance. • The PALC22V10D, featuring programmable macrocells and variable product terms, provides a device with the flexibility to implement logic functions in the 500- to 800-gate-array complexity. Since each of the 10 output pins may be individually configured as inputs on a temporary or permanent basis, functions requiring up to 21 inputs and only a single output and down to 12 inputs and 10 outputs are possible. The 10 potential outputs are enabled using product terms. Any output pin may be permanently selected as an output or arbitrarily enabled as an output and an input through the selective use of individual product terms associated with each output. Each of these outputs is achieved through an individual programmable macrocell. These macrocells are programmable to provide a combinatorial or registered inverting or non-inverting output. In a registered mode of operation, the output of the register is fed back into the array, providing current status information to the array. This information is available for establishing the next result in applications such as control state machines. In a combinatorial configuration, the combinatorial output or, if the output is disabled, the signal present on the I/O pin is made available to the array. The flexibility provided by both programmable product term control of the outputs and variable product terms allows a significant gain in functional density through the use of programmable logic. Along with this increase in functional density, the Cypress PALC22V10D provides lower-power operation through the use of CMOS technology, and increased testability with Flash reprogrammability. PAL is a registered trademark of Advanced Micro Devices 3901 North First Street • San Jose • CA 95134 • 408-943-2600 July 1991 – Revised October 1995 PALC22V10D Logic Block Diagram (PDIP/CDIP) VSS 12 I I I I I I I I I I 11 10 9 8 7 6 5 4 3 2 14 12 10 Macrocell Macrocell Macrocell CP/I 1 PROGRAMMABLE AND ARRAY (132 X 44) 8 10 12 14 Macrocell Macrocell Macrocell 16 16 8 Reset Macrocell Macrocell Macrocell Macrocell Preset 13 14 15 16 17 18 19 20 21 22 23 24 I I/O9 I/O8 I/O 7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCC V10D–1 Pin Configuration PLCC Top View LCC Top View 4 3 2 1 2827 26 4 3 2 1 282726 I I I NC I I I 5 6 7 8 9 10 11 25 24 23 22 21 20 19 I/O 2 I/O 3 I/O 4 N/C I/O 5 I/O 6 I/O 7 I I I NC I I I 12131415161718 5 6 7 8 9 10 11 121314 1516 1718 25 24 23 22 21 20 19 I/O 2 I/O 3 I/O 4 N/C I/O 5 I/O 6 I/O 7 V10D–2 V10D–3 Configuration Table Configuration Table Registered/Combinatorial Registered/Combinatorial C1 C0 Configuration 0 0 Registered/Active LOW 0 1 Registered/Active HIGH 2 C1 C0 1 0 Combinatorial/Active LOW Configuration 1 1 Combinatorial/Active HIGH PALC22V10D Macrocell AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AR AA AA AA AA AA AA AA AA OUTPUT AA AA AA AA SELECT AA AA AA AA MUX D Q AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA S S Q CP 1 0 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA SP AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA INPUT/ AA AA AA FEEDBACK AA AA AA AA AA MUX AA AA AA AA AA AA AA AA S1 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA MACROCELL AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA C1 C0 V10D–4 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-Up Current ..................................................... >200 mA Storage Temperature .....................................−65°C to +150°C Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2001V Ambient Temperature with Power Applied..................................................−55°C to +125°C Operating Range Supply Voltage to Ground Potential (Pin 24 to Pin 12).................................................−0.5V to +7.0V Ambient Temperature Range 0°C to +75°C DC Voltage Applied to Outputs in High Z State .....................................................−0.5V to +7.0V Commercial DC Input Voltage............................................. -0.5V to +7.0V Industrial Output Current into Outputs (LOW) ............................. 16 mA Note: 1. TA is the “instant on” case temperature. Military DC Programming Voltage .............................................12.5V VCC 5V ±5% −55°C to +125°C 5V ±10% −40°C to +85°C 5V ±10% ]] Electrical Characteristics Over the Operating Parameter Range Description Test Conditions Min. VOH Output HIGH Voltage VCC = Min., VIN = VIH or VIL IOH = -3.2 mA Com’l IOH = -2 mA Mil/Ind VOL Output LOW Voltage VCC = Min., VIN = VIH or VIL IOL = 16 mA Com’l IOL = 12 mA Mil/Ind Max. 2.4 Unit V 0.5 V Input HIGH Level Guaranteed Input Logical HIGH Voltage for All Inputs 2.0 VIL Input LOW Level Guaranteed Input Logical LOW Voltage for All Inputs -0.5 0.8 V IIX Input Leakage Current -10 10 µA IOZ Output Leakage Current VSS < VIN < VCC, VCC = Max. VCC = Max., VSS < VOUT < VCC -40 40 µA -30 -90 mA VIH  ISC Output Short Circuit Current VCC = Max., VOUT = 3 0.5V[5,6] V PALC22V10D Electrical Characteristics Over the Operating Range Parameter ICC1 Description Standby Power Supply Current ICC2 Operating Power Supply Current Test Conditions Min. Max. Unit VCC = Max., 10, 15, 25 ns VIN = GND, 7.5 ns Outputs Open in Unprogrammed De- 15, 25 ns vice 10 ns Com’l 90 mA Com’l 130 mA Mil/Ind 120 mA Mil/Ind 120 mA VCC = Max., VIL = 0V, VIH = 3V, Output Open, Device Programmed as a 10-Bit Counter, f = 25 MHz 10, 15, 25 ns Com’l 110 mA 7.5 ns Com’l 140 mA 15, 25 ns Mil/Ind 130 mA 10 ns Mil/Ind 130 mA Notes: 2. See the last page of this specification for Group A subgroup testing information. 3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 4. VIL (Min.) is equal to -3.0V for pulse durations less than 20 ns. 5. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 6. Tested initially and after any design or process changes that may affect these parameters. Capacitance Parameter Description CIN Input Capacitance COUT Output Capacitance  Test Conditions Min. Max. Unit VIN = 2.0V @ f = 1 MHz 10 pF VOUT = 2.0V @ f = 1 MHz 10 pF Endurance Characteristics Parameter N Description Minimum Reprogramming Cycles Test Conditions Min. Normal Programming Conditions 100 Max. Unit Cycles AC Test Loads and Waveforms R1238 Ω (319Ω MIL) R1238 Ω (319Ω MIL) 5V 5V OUTPUT CL R2170 Ω (236Ω MIL) OUTPUT INCLUDING JIG AND SCOPE 5 pF R2170 Ω (236Ω MIL) OUTPUT 750Ω (1.2KΩ MIL) CL INCLUDING JIG AND SCOPE (a) (b) (c) ALL INPUT PULSES 3.0V 90% GND 90% 10% 10% < 2 ns < 2 ns V10D–5 (d) Equivalent to: THÉVENIN EQUIVALENT(Commercial) Equivalent to: THÉVENIN EQUIVALENT(Military) 99Ω OUTPUT 136Ω OUTPUT 2.08V=V thc V10D–6 2.13V=V thm V10D–7 4 PALC22V10D Load Speed CL Package 7.5, 10, 15, 25 ns 50 pF PDIP, CDIP, PLCC, LCC Parameter VX t ER (- ) 1.5V t ER (+) 2.6V t EA (+) 0V t EA (- ) V thc Output Waveform Measurement Level V OH V OL VX VX VX 0.5V 0.5V V10D–8 VX V10D–9 1.5V V OH V10D–10 V OL 0.5V (e) Test Waveforms 5 V10D–11 PALC22V10D Commercial Switching Characteristics PALC22V10D[2, 7] 22V10D-7 Parameter Description 22V10D-10 22V10D-15 22V10D-25 Min. Max. Min. Max. Min. Max. Min. Max. Unit 3 7.5 3 10 3 15 3 25 ns tPD Input to Output Propagation Delay[8, 9] tEA Input to Output Enable Delay 8 10 15 25 ns tER Input to Output Disable Delay 8 10 15 25 ns [8, 9] tCO Clock to Output Delay tS1 Input or Feedback Set-Up Time 5 2 5 6 2 10 15 ns tS2 Synchronous Preset Set-Up Time 6 7 10 15 ns tH Input Hold Time 0 0 0 0 ns tP External Clock Period (tCO + tS) 10 12 20 30 ns tWH Clock Width HIGH 3 3 6 13 ns tWL Clock Width LOW 3 3 6 13 ns fMAX1 External Maximum Frequency (1/(tCO + tS)) 100 76.9 55.5 33.3 MHz fMAX2 Data Path Maximum Frequency (1/(tWH + tWL))[6, 13] 166 142 83.3 35.7 MHz fMAX3 Internal Feedback Maximum Frequency (1/(tCF + tS))[6,14] 133 111 68.9 38.5 MHz tCF Register Clock to Feedback Input[6, 15] tAW Asynchronous Reset Width 8 10 15 25 ns tAR Asynchronous Reset Recovery Time 5 6 10 25 ns tAP Asynchronous Reset to Registered Output Delay tSPR Synchronous Preset Recovery Time 6 8 10 15 ns tPR Power-Up Reset Time[6,16] 1 1 1 1 µs 2.5 7 2 3 12 8 2 4.5 13 15 13 20 25 ns ns ns Notes: 7. Part (a) of AC Test Loads and Waveforms is used for all parameters except tER and tEA(+). Part (b) of AC Test Loads and Waveforms is used for tER. Part (c) of AC Test Loads and Waveforms is used for tEA(+). 8. Min. times are tested initially and after any design or process changes that may affect these parameters. 9. This specification is guaranteed for all device outputs changing state in a given access cycle. 10. The test load of part (a) of AC Test Loads and Waveforms is used for measuring tEA(-). The test load of part (c) of AC Test Loads and Waveforms is used for measuring tEA(+) only. Please see part (e) of AC Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels. 11. This parameter is measured as the time after output disable input that the previous output data state remains stable on the output. This delay is measured to the point at which a previous HIGH level has fallen to 0.5 volts below VOH min. or a previous LOW level has risen to 0.5 volts above VOL max. Please see part (e) of AC Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels. 12. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate. 13. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode. 14. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate. 15. This parameter is calculated from the clock period at fMAX internal (1/fMAX3) as measured (see Note above) minus tS. 16. The registers in the PALC22V10D have been designed with the capability to reset during system power-up. Following power-up, all registers will be reset to a logic LOW state. The output state will depend on the polarity of the output buffer. This feature is useful in establishing state machine initialization. To insure proper operation, the rise in VCC must be monotonic and the timing constraints depicted in Power-Up Reset Waveform must be satisfied. 6 PALC22V10D Military and Industrial Switching Characteristics PALC22V10D[2, 7] 22V10D-10 Parameter Description 22V10D-15 22V10D-25 Min. Max. Min. Max. Min. Max. Unit 3 10 3 15 3 25 ns tPD Input to Output Propagation Delay[8, 9] tEA Input to Output Enable Delay 10 15 25 ns tER Input to Output Disable Delay 10 15 25 ns [8, 9] tCO Clock to Output Delay tS1 Input or Feedback Set-Up Time 6 2 7 10 2 8 18 2 15 ns ns tS2 Synchronous Preset Set-Up Time 7 10 18 ns tH Input Hold Time 0 0 0 ns tP External Clock Period (tCO + tS) 12 20 33 ns tWH Clock Width HIGH 3 6 14 ns tWL Clock Width LOW 3 6 14 ns fMAX1 External Maximum Frequency (1/(tCO + tS)) 76.9 50.0 30.3 MHz fMAX2 Data Path Maximum Frequency (1/(tWH + tWL))[6, 13] 142 83.3 35.7 MHz fMAX3 Internal Feedback Maximum Frequency (1/(tCF + tS))[6,14] 111 68.9 32.2 MHz tCF Register Clock to Feedback Input[6,15] tAW Asynchronous Reset Width 10 15 25 ns tAR Asynchronous Reset Recovery Time 6 12 25 ns tAP Asynchronous Reset to Registered Output Delay tSPR Synchronous Preset Recovery Time 8 20 25 ns tPR Power-Up Reset Time[6, 16] 1 1 1 µs 3 4.5 12 7 13 20 25 ns ns PALC22V10D Switching Waveform INPUTS I/O, REGISTERED FEEDBACK SYNCHRONOUS PRESET tS t WH tH t WL CP t SPR tP t AW ASYNCHRONOUS RESET t CO t AR t AP tER[NO TAG] tEA[NO TAG] tER[NO TAG] tEA[NO TAG] REGISTERED OUTPUTS t PD COMBINATORIAL OUTPUTS V10D–12 Power-Up Reset Waveform POWER SUPPLY VOLTAGE 10% VCC 90% t PR REGISTERED ACTIVE LOW OUTPUTS tS CLOCK tPR MAX = 1 µs 8 t WL V10D–13 PALC22V10D Functional Logic Diagram for PALC22V10D 1 0 4 8 12 16 20 24 32 28 36 40 AR OE 0 S S S 7 Macro– cell 23 Macro– cell 22 Macro– cell 21 Macro– cell 20 Macro– cell 19 Macro– cell 18 Macro– cell 17 Macro– cell 16 Macro– cell 15 Macro– cell 14 OE 0 S S S 2 9 OE 0 S S S 3 11 OE 0 S S S 4 13 OE 0 S S S 5 15 OE 0 S S S 6 15 OE 0 S S S 7 13 OE 0 S S S 11 8 OE 0 S S S 9 9 OE 0 S S S 7 10 SP 13 11 V10D–14 9 PALC22V10D Ordering Information ICC (mA) tPD (ns) tS (ns) tCO (ns) 130 7.5 5 5 90 150 150 10 10 10 6 6 6 7 7 7 Ordering Code Package Name Package Type PALC22V10D-7JC J64 28-Lead Plastic Leaded Chip Carrier PALC22V10D-7PC P13 24-Lead (300-Mil) Molded DIP PALC22V10D-10JC J64 28-Lead Plastic Leaded Chip Carrier PALC22V10D-10PC P13 24-Lead (300-Mil) Molded DIP PALC22V10D-10JI J64 28-Lead Plastic Leaded Chip Carrier PALC22V10D-10PI P13 24-Lead (300-Mil) Molded DIP PALC22V10D-10DMB D14 24-Lead (300-Mil) CerDIP PALC22V10D-10KMB K73 24-Lead Rectangular Cerpack PALC22V10D-10LMB L64 28-Square Leadless Chip Carrier 90 15 7.5 10 PALC22V10D-15JC J64 28-Lead Plastic Leaded Chip Carrier PALC22V10D-15PC P13 24-Lead (300-Mil) Molded DIP 120 15 7.5 10 PALC22V10D-15JI J64 28-Lead Plastic Leaded Chip Carrier PALC22V10D-15PI P13 24-Lead (300-Mil) Molded DIP 120 15 7.5 10 PALC22V10D-15DMB D14 24-Lead (300-Mil) CerDIP PALC22V10D-15KMB K73 24-Lead Rectangular Cerpack PALC22V10D-15LMB L64 28-Square Leadless Chip Carrier PALC22V10D-25JC J64 28-Lead Plastic Leaded Chip Carrier PALC22V10D-25PC P13 24-Lead (300-Mil) Molded DIP PALC22V10D-25JI J64 28-Lead Plastic Leaded Chip Carrier PALC22V10D-25PI P13 24-Lead (300-Mil) Molded DIP PALC22V10D-25DMB D14 24-Lead (300-Mil) CerDIP PALC22V10D-25KMB K73 24-Lead Rectangular Cerpack PALC22V10D-25LMB L64 28-Square Leadless Chip Carrier 90 120 120 25 25 25 15 15 15 15 15 15 MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Switching Characteristics Subgroups VOH 1, 2, 3 VOL 1, 2, 3 VIH 1, 2, 3 VIL 1, 2, 3 IIX 1, 2, 3 IOZ 1, 2, 3 ICC 1, 2, 3 Parameter Subgroups tPD 9, 10, 11 tCO 9, 10, 11 tS 9, 10, 11 tH 9, 10, 11 Document #: 38-00185-H 10 Operating Range Commercial Commercial Industrial Military Commercial Industrial Military Commercial Industrial Military PALC22V10D Package Diagrams 24–Lead (300–Mil) CerDIP D14 MIL-STD-1835 28–Lead Plastic Leaded Chip Carrier J64 D-9 Config. A 24–Lead Rectangular Cerpack K73 MIL-STD-1835 28–Square Leadless Chip Carrier L64 F-6 Config. A MIL-STD-1835 C-4 11 PALC22V10D Package Diagrams (continued) 24–Lead (300–Mil) Molded DIP P13/P13A © Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.