0RA10 PLDC20RA10 Reprogrammable Asynchronous CMOS Logic Device — ICC max = 85 mA (Military) • High reliability — Proven EPROM technology Features • • • • • • • • • Advanced-user programmable macrocell CMOS EPROM technology for reprogrammability Up to 20 input terms 10 programmable I/O macrocells Output macrocell programmable as combinatorial or asynchronous D-type registered output Product-term control of register clock, reset and set and output enable Register preload and power-up reset Four data product terms per output macrocell Fast — Commercial tPD = 15 ns tCO = 15 ns tSU = 7 ns — >2001V input protection — 100% programming and functional testing • Windowed DIP, windowed LCC, DIP, LCC, PLCC available Functional Description The Cypress PLDC20RA10 is a high-performance, second-generation programmable logic device employing a flexible macrocell structure that allows any individual output to be configured independently as a combinatorial output or as a fully asynchronous D-type registered output. The Cypress PLDC20RA10 provides lower-power operation with superior speed performance than functionally equivalent bipolar devices through the use of high-performance 0.8-micron CMOS manufacturing technology. — Military tPD = 20 ns tCO = 20 ns tSU = 10 ns • Low power — ICC max - 80 mA (Commercial) The PLDC20RA10 is packaged in a 24 pin 300-mil molded DIP, a 300-mil windowed cerDIP, and a 28-lead square leadless chip carrier, providing up to 20 inputs and 10 outputs. When the windowed device is exposed to UV light, the 20RA10 is erased and can then be reprogrammed. Logic Block Diagram VSS I9 I8 12 11 10 4 I7 I6 I5 I4 I3 I2 I1 I0 PL 9 8 7 6 5 4 3 2 1 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL 13 14 15 16 17 18 19 20 21 22 23 24 OE I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCC RA10–1 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 December 1987 - Revised March 26, 1997 PLDC20RA10 Selection Guide tPD ns Generic Part Number 20RA10-15 20RA10-20 20RA10-25 20RA10-35 Com‘l 15 20 tSU ns Mil Com’l 7 10 20 25 35 tCO ns Mil Com’l 15 20 10 15 20 tCC ns Mil 20 25 35 Com’l 80 80 Mil 85 85 85 Pin Configurations STD PLCC/HLCC Top View PLDC20RA10 25 24 23 22 21 20 19 NC I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 5 6 7 8 9 10 11 PLDC20RA10 121314 1516 1718 7 I I 8 9 VSS OE I/O9 I/O8 NC 12131415161718 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 NC I2 I3 I4 NC I5 I6 I7 5 6 7 8 9 10 11 PL NC VCC I/O0 I/O1 PLDC20RA10 CG7C324 121314 1516 1718 25 24 23 22 21 20 19 I/O 2 I/O 3 I/O 4 NC I/O 5 I/O 6 I/O 7 I I RA10–3 Macrocell Architecture  4 3 2 1 2827 26 25 24 23 22 21 20 19 I I I RA10–2 I1 I0 4 3 2 1 2827 26 NC I3 I4 NC I5 I6 NC 8 9 VSS OE I/O9 I/O8 5 6 7 8 9 10 11 8 9 VSS NC OE I/O9 I/O8 4 3 2 1 282726 I2 I3 I4 I5 I6 I 7 NC JEDEC PLCC/HLCC Top View PL VCC I/O0 I/O1 I2 I1 I0 NC I1 I0 PL VCC I/O0 I/O1 LCC Top View RA10–4 product terms and four uncommitted product terms of each programmable I/O macrocell that has been configured as an output. Figure 1 illustrates the architecture of the 20RA10 macrocell. The cell dedicates three product terms for fully asynchronous control of the register set, reset, and clock functions, as well as, one term for control of the output enable function. An I/O cell is programmed as an input by tying the output enable pin (pin 13) HIGH or by programming the output enable product term to provide a LOW, thereby disabling the output buffer, for all possible input combinations. The output enable product term output is ANDed with the input from pin 13 to allow either product term or hardwired external control of the output or a combination of control from both sources. If product-term-only control is selected, it is automatically chosen for all outputs since, for this case, the external output enable pin must be tied LOW. The active polarity of each output may be programmed independently for each output cell and is subsequently fixed. Figure 2 illustrates the output enable options available. When utilizing the I/O macrocell as an output, the input path functions as a feedback path allowing the output signal to be fed back as an input to the product term array. When the output cell is configured as a registered output, this feedback path may be used to feed back the current output state to the device inputs to provide current state control of the next output state as required for state machine implementation. Preload and Power-Up Reset When an I/O cell is configured as an output, combinatorial-only capability may be selected by forcing the set and reset product term outputs to be HIGH under all input conditions. This is achieved by programming all input term programming cells for these two product terms. Figure 3 illustrates the available output configuration options. Functional testability of programmed devices is enhanced by inclusion of register preload capability, which allows the state of each register to be set by loading each register from an external source prior to exercising the device. Testing of complex state machine designs is simplified by the ability to load an arbitrary state without cycling through long test vector sequences to reach the desired state. Recovery from illegal states can be verified by loading illegal states and observing recovery. Preload of a particular register is accomplished by impressing the desired state on the register output pin and lowering the signal level on the preload control pin (pin1) to a logic LOW level. If the specified preload set-up, hold and pulse width minimums have been observed, the desired state is loaded into the register. To insure predictable system initialization, all registers are preset to a logic LOW state upon power-up, thereby setting the active LOW outputs to a logic HIGH. An additional four uncommitted product terms are provided in each output macrocell as resources for creation of user-defined logic functions. Programmable I/O Because any of the ten I/O pins may be selected as an input, the device input configuration programmed by the user may vary from a total of nine programmable plus ten dedicated inputs (a total of nineteen inputs) and one output down to a ten-input, ten-output configuration with all ten programmable I/O cells configured as outputs. Each input pin available in a given configuration is available as an input to the four control Note: 1. The CG7C324 is the PLDC20RA10 packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for both PLCC pinouts. The principal difference is in the location of the “no connect” (NC) pins 2 PLDC20RA10 . OUTPUT ENABLE (FROM PIN 13) PRELOAD (FROM PIN 1) 1 S S D Q TO I/O PIN O O C0 PL P R RA10–5 Figure 1. PLDC20RA10 Macrocell Output Always Enabled Programmable RA10–7 RA10–6 Combination of Programmable and Hardwired External Pin OE RA10–8 RA10–9 Figure 2. Four Possible Output Enable Alternatives for the PLDC20RA10 3 PLDC20RA10 Registered/ActiveLOW Combinatorial/Active LOW S Q D R RA10–10 RA10–11 Combinatorial/Active HIGH Registered/Active HIGH S Q D R RA10–12 Figure 3. Four Possible Macrocell Configurations for the PLDC20RA10 4 RA10–13 PLDC20RA10 Maximum Ratings Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Latch-Up Current ..................................................... >200 mA Ambient Temperature with Power Applied ............................................. –55°C to +125°C Operating Range DC Program Voltage..................................................... 13.0V Supply Voltage to Ground Potential (Pin 24 to Pin 12) ........................................... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... –0.5V to +7.0V Range Ambient Temperature VCC Commercial 0°C to +75°C 5V ± 10% –55°C to +125°C 5V ± 10% Military DC Input Voltage......................................... –3.0 V to + 7.0 V  ] Output Current into Outputs (LOW) ............................. 16 mA Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. VOH Output HIGH Voltage VCC = Min., VIN =VIH or VIL IOH = –3.2 mA Com’l IOH = –2 mA Mil VOL Output LOW Voltage VCC = Min., VIN = VIH or VIL IOL = 8 mA VIH Input HIGH Level Guaranteed Input Logical HIGH Voltage for All Inputs VIL Input LOW Level Guaranteed Input Logical LOW Voltage for All Inputs IIX Input Leakage Current VSS ≤ V IN ≤ VCC, V CC = Max IOZ Output Leakage Current VCC = Max., VSS ≤ VOUT ≤ VCC  Output Short Circuit Current VCC = Max., VOUT = 0.5V ICC1 Standby Power Supply Current VCC= Max., VIN = GND Outputs Open ICC2 Power Supply Current at Frequency VCC = Max., Outputs Disabled (In High Z State) Device Operating at fMAX 2.4 Unit V 0.5  ISC Max. 2.0 V V 0.8 V –10 +10 µA –40 +40 µA –30 –90 mA Com’l 75 mA Mil 80 mA Com’l 80 mA Mil 85 mA Capacitance Parameter Description Test Conditions Max. Unit CIN Input Capacitance VIN = 2.0 V @ f = 1 MHz 10 pF COUT Output Capacitance VOUT = 2.0 V @ f = 1 MHz 10 pF Notes: 2. TA is the “instant on” case temperature. 3. See the last page of this specification for Group A subgroup testing information. 4. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 5. Tested initially and after any design or process changes that may affect these parameters. 6. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 5 PLDC20RA10 AC Test Loads and Waveforms (Commercial) R1 457Ω (470Ω MIL) R1 457Ω (470Ω MIL) 5V ALL INPUT PULSES 3.0V 90% 5V OUTPUT OUTPUT R2 270Ω 5 pF (319Ω Mil) INCLUDING JIG AND SCOPE 50 pF INCLUDING JIG AND SCOPE (a) Equivalent to: GND R2 270Ω < 5 ns (319Ω Mil) t PXZ(– ) t PXZ(+) 170Ω Equivalent to: 1.86V=Vthc Vth 1.5V 2.6V V OH VX t PZX(– ) V thc VX t ER(–) 1.5V V OH t ER(+) 2.6V V OL V thc V thc 0.5V 0.5V V OL V thc t EA(– ) RA10–15 THÉVENIN EQUIVALENT(Military) OUTPUT 190Ω 2.02V=Vthc Output Waveform Measurement Level t PZX(+) t EA(+) < 5 ns RA10–14 RA10–16 Parameter 10% (b) THÉVENIN EQUIVALENT(Commercial) OUTPUT 90% 10% RA10–18 VX RA10–19 0.5V V OH RA10–20 0.5V V OL RA10–21 0.5V VX RA10–22 0.5V VX RA10–23 0.5V VX VX VX V OH RA10–24 0.5V (c) 6 V OL RA10–25 RA10–17 PLDC20RA10 Switching Characteristics Over the Operating Range[3, 7, 8] Commercial –15 Parameter Description Min. Military –20 Max. Min. –20 Min. Max. Unit Input or Feedback to Non-Registered Output 15 20 20 25 35 ns tEA Input to Output Enable 15 20 20 30 35 ns tER Input to Output Disable 15 20 20 30 35 ns tPZX Pin 13 to Output Enable 12 15 15 20 25 ns tPXZ Pin 13 to Output Disable 12 15 15 20 25 ns tCO Clock to Output 35 ns tSU Input or Feedback Set-Up Time 7 10 10 15 20 ns tH Hold Time 3 5 3 5 5 ns tP Clock Period (tSU + tCO) 22 30 30 40 55 ns tWH Clock Width HIGH  10 13 12 18 25 ns tWL Clock Width LOW 10 13 12 18 25 ns fMAX Maximum Frequency (1/tP) 45.5 33.3 33.3 25.0 18.1 MHz tS Input of Asynchronous Set to Registered Output 15 20 20 25 40 ns tR Input of Asynchronous Reset to Registered Output 15 20 20 25 40 ns tARW Asynchronous Reset Width 15 20 20 25 25 ns tASW Asynchronous S-Width 15 20 20 25 25 ns tAR Asynchronous Set/ Reset Recovery Time 10 12 12 15 20 ns tWP Preload Pulse Width 15 15 15 15 15 ns tSUP Preload Set-Up Time 15 15 15 15 15 ns tHP Preload Hold Time 15 15 15 15 15 ns 20 Max. Min. –35 tPD 15 Max. –25 20 Max. Min. 25 Notes: 7. Part (a) of AC Test Loads was used for all parameters except tEA, tER, tPZX and tPXZ, which use part (b). 8. The parameters tER and tPXZ are measured as the delay from the input disable logic threshold transition to VOH - 0.5 V for an enabled HIGH output or VOL +0.5V for an enabled LOW output. Please see part (c) of AC Test Loads and Waveforms for waveforms and measurement reference levels. 7 PLDC20RA10 Switching Waveform tH INPUTS,REGISTERED FEEDBACK t SU tP CP t WH ASYNCHRONOUS RESET ASYNCHRONOUS SET t WL t AR tPD t CO OUTPUTS (HIGHASSERTED) t ER t EA OUTPUT ENABLE INPUTPIN RA10–26 Preload Switching Waveform PIN 13 OUTPUT ENABLE t ER t EA REGISTER OUTPUTS t SUP PIN 1 PRELOAD CLOCK t HP t WP RA10–27 Asynchronous Reset ASYNCHRONOUS RESET t ARW tR OUTPUT RA10–28 Asynchronous Set ASYNCHRONOUS SET tASW tS OUTPUT RA10–29 8 PLDC20RA10 Functional Logic Diagram 9 PLDC20RA10 Ordering Information ICC2 tPD (ns) tSU (ns) tCO (ns) 80 15 7 15 20 85 20 25 35 10 20 10 20 15 25 20 35 Ordering Code Package Name Package Type PLDC20RA10-15JC J64 28-Lead Plastic Leaded Chip Carrier PLDC20RA10-15PC P13 24-Lead (300-Mil) Molded DIP CG7C324-A15JC J64 28-Lead Plastic Leaded Chip Carrier PLDC20RA10-20PC P13 24-Lead (300-Mil) Molded DIP CG7C324-A20JC J64 28-Lead Plastic Leaded Chip Carrier PLDC20RA10-20DMB D14 24-Lead (300-Mil) CerDIP PLDC20RA10-20WMB W14 24-Lead (300-Mil) Windowed CerDIP PLDC20RA10-25DMB D14 24-Lead (300-Mil) CerDIP PLDC20RA10-25WMB W14 24-Lead (300-Mil) Windowed CerDIP PLDC20RA10-35DMB D14 24-Lead (300-Mil) CerDIP PLDC20RA10-35WMB W14 24-Lead (300-Mil) Windowed CerDIP MILITARY SPECIFICATIONS Group A Subgroup Testing Switching Characteristics Parameter DC Characteristics Parameter Subgroups Subgroups tPD 9, 10, 11 tPZX 9, 10, 11 VOH 1, 2, 3 tCO 9, 10, 11 VOL 1, 2, 3 tSU 9, 10, 11 VIH 1, 2, 3 tH 9, 10, 11 VIL 1, 2, 3 IIX 1, 2, 3 IOZ 1, 2, 3 ICC 1, 2, 3 Document #: 38-00073-F 10 Operating Range Commercial Military PLDC20RA10 Package Diagrams 24-Lead (300-Mil) CerDIP D14 MIL-STD-1835 28-Lead Plastic Leaded Chip Carrier J64 D- 9Config.A 28-Square L64 Carrier Chip Leadless 28-Pin Windowed Leadless Chip Carrier Q64 MIL-STD-1835 C-4 MIL-STD-1835 C-4 11 PLDC20RA10 Package Diagrams (continued) 28-Pin Windowed Leaded Chip Carrier H64 12 PLDC20RA10 Package Diagrams (continued) 24-Lead (300-Mil) Molded DIP P13/P13A 24-Lead (300-Mil) Windowed CerDIP W14 MIL-STD-1835 D- 9 Config.A © Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.