March 2007 HYS72T32000HR–[2.5/3/3S/3.7/5]–A HYS72T64001HR–[2.5/3/3S/3.7/5]–A HYS72T64020HR–[2.5/3/3S/3.7/5]–A 240-Pin Registered DDR2 SDRAM Modules DDR2 SDRAM RDIMM SDRAM RoHS Compliant Internet Data Sheet Rev. 1.21 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules HYS72T32000HR–[2.5/3/3S/3.7/5]–A, HYS72T64001HR–[2.5/3/3S/3.7/5]–A, HYS72T64020HR–[2.5/3/3S/3.7/5]–A Revision History: 2007-03, Rev. 1.21 Page Subjects (major changes since last revision) All Qimonda update All Adapted internet edition Previous Revision: 2005-09, Rev. 1.2 Chapter 4 SPD Codes update: Byte 49 Bit 0 = 1 (HighT_SRFEntry) for all product types Chapter 5 Package Outlines updated Previous Revision: 2005-06, Rev. 1.1 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] qag_techdoc_rev400 / 3.2 QAG / 2006-08-07 09152006-J5FK-C565 2 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules 1 Overview This chapter gives an overview of the 240-pin Registered DDR2 SDRAM Modules product family and describes its main characteristics. 1.1 Features • Programmable CAS Latencies (3, 4, 5 & 6), Burst Length (4 & 8) and Burst Type • Auto Refresh (CBR) and Self Refresh • All inputs and outputs SSTL_18 compatible • Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT) • Serial Presence Detect with E2PROM • RDIMM Dimensions (nominal): 30 mm high, 133.35 mm wide • Based on Standard reference layouts Raw Card “A-F”, “BG” & “C-H” • RoHS compliant products1) • 240-pin PC2-6400, PC2-5300, PC2-4200 and PC2-3200 DDR2 SDRAM memory modules for PC, Workstation and Server main memory applications • One rank 32M x 72, 64M x 72 and two ranks 64M × 72 module organization and 32M × 8, 64M × 4 chip organization • Standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power supply • All Speed Grades faster than DDR2–400 comply with DDR2–400 timing specifications • Built with 256-Mbit DDR2 SDRAMs in P-TFBGA-60 chipsize packages. TABLE 1 Performance for –2.5 & –3 (S) Product Type Speed Code –2.5 –3 –3S Unit Speed Grade PC2–6400 6–6–6 PC2–5300 4–4–4 PC2–5300 5–5–5 — 400 333 333 333 333 333 MHz 266 333 266 MHz 200 200 200 MHz 15 12 15 ns 15 12 15 ns 45 45 45 ns 60 57 60 ns max. Clock Frequency @CL6 @CL5 @CL4 @CL3 min. RAS-CAS-Delay min. Row Precharge Time min. Row Active Time min. Row Cycle Time fCK6 fCK5 fCK4 fCK3 tRCD tRP tRAS tRC 1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. Rev. 1.21, 2007-03 09152006-J5FK-C565 3 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules TABLE 2 Performance for DDR2-533 and DDR2-400 Product Type Speed Code –3.7 –5 Units Speed Grade PC2–4200 4–4–4 PC2–3200 3–3–3 — 266 200 MHz 266 200 MHz 200 200 MHz 15 15 ns 15 15 ns 45 40 ns 60 55 ns Max. Clock Frequency @CL5 @CL4 @CL3 Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time Rev. 1.21, 2007-03 09152006-J5FK-C565 fCK5 fCK4 fCK3 tRCD tRP tRAS tRC 4 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules 1.2 Description devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and are write-protected; the second 128 bytes are available to the customer. The QIMONDA HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A module family are Registered DIMM modules “RDIMMs” with 30 mm height based on DDR2 technology. DIMMs are available as ECC modules in 32M x 72 (256 MByte) and 64M x 72 (512 MByte) organization and density, intended for mounting into 240-pin connector sockets. The memory array is designed with 256-Mbit Double-DataRate-Two (DDR2) Synchronous DRAMs. All control and address signals are re-driven on the DIMM using register TABLE 3 Ordering Information for RoHS Compliant Products Product Type1) Compliance Code2) Description SDRAM Technology HYS72T32000HR–2.5–A 256 MB 1R×8 PC2–6400R–666–12–F0 1 Rank, ECC 256 Mbit (×8) HYS72T64001HR–2.5–A 512 MB 1R×4 PC2–6400R–666–12–H0 1 Rank, ECC 256 Mbit (×4) HYS72T64020HR–2.5–A 512 MB 2R×8 PC2–6400R–666–12–G0 2 Rank, ECC 256 Mbit (×8) PC2-6400 PC2-5300 HYS72T32000HR–3–A 256 MB 1R×8 PC2–5300R–444–12–F0 1 Rank, ECC 256 Mbit (×8) HYS72T64001HR–3–A 512 MB 1R×4 PC2–5300R–444–12–H0 1 Rank, ECC 256 Mbit (×4) HYS72T64020HR–3–A 512 MB 2R×8 PC2–5300R–444–12–G0 2 Rank, ECC 256 Mbit (×8) HYS72T32000HR–3S–A 256 MB 1R×8 PC2–5300R–555–12–F0 1 Rank, ECC 256 Mbit (×8) HYS72T64001HR–3S–A 512 MB 1R×4 PC2–5300R–555–12–H0 1 Rank, ECC 256 Mbit (×4) HYS72T64020HR–3S–A 512 MB 2R×8 PC2–5300R–555–12–G0 2 Rank, ECC 256 Mbit (×8) HYS72T32000HR–3.7–A 256 MB 1R×8 PC2–4200R–444–11–F0 1 rank, ECC 256 Mbit (×8) HYS72T64001HR–3.7–A 512 MB 1R×4 PC2–4200R–444–11–H0 1 rank, ECC 256 Mbit (×4) HYS72T64020HR–3.7–A 512 MB 2R×8 PC2–4200R–444–11–G0 2 rank, ECC 256 Mbit (×8) PC2–4200 PC2-3200 HYS72T32000HR–5–A 256 MB 1R×8 PC2–3200R–333–11–F0 1 Rank, ECC 256 Mbit (×8) HYS72T64001HR–5–A 512 MB 1R×4 PC2–3200R–333–11–H0 1 Rank, ECC 256 Mbit (×4) HYS72T64020HR–5–A 512 MB 2R×8 PC2–3200R–333–11–G0 2 Rank, ECC 256 Mbit (×8) 1) All part numbers end with a place code, designating the silicon die revision. Example: HYS72T32000HR–5–A, indicating Rev. “A” dies are used for DDR2 SDRAM components. For all QIMONDA DDR2 module and component nomenclature see Chapter 6 of this data sheet. 2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200R–444–11–F0”, where 4200R means Registered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-11” means Column Address Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.1 and produced on the Raw Card “F” Rev. 1.21, 2007-03 09152006-J5FK-C565 5 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules TABLE 4 Address Format DIMM Density Module Organization Memory Ranks ECC/ Non-ECC # of SDRAMs # of row/bank/columns bits Raw Card 256 MB 32M ×72 512 MB 64M ×72 1 ECC 9 13/2/10 A-F 1 ECC 18 13/2/11 C-H 512 MB 64M ×72 2 ECC 18 13/2/10 B-G TABLE 5 Components on Modules Product Type1) DRAM Components1) DRAM Density DRAM Organization Note2) HYS72T32000HR HYB18T256800AF 256 Mbit 32M × 8 — HYS72T64001HR HYB18T256400AF 256 Mbit 64M × 4 — HYS72T64020HR HYB18T256800AF 256 Mbit 32M × 8 — 1) Green Product 2) For a detailed description of all available functions of the DRAM components on these modules see the component data sheet. Rev. 1.21, 2007-03 09152006-J5FK-C565 6 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules 2 Pin Configuration and Table 8 respectively. The pin numbering is depicted in Figure 1. The pin configuration of the Registered DDR2 SDRAM DIMM is listed by function in Table 6 (240 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 7 TABLE 6 Pin Configuration of RDIMM Ball No. Name Pin Type Buffer Type Function 185 CK0 I SSTL Clock Signal CK0, Complementary Clock Signal CK0 186 CK0 I SSTL 52 CKE0 I SSTL 171 CKE1 I SSTL NC NC — Not Connected Note: 1-Rank module 193 S0 I SSTL 76 S1 I SSTL Chip Select Rank 1:0 Note: 2-Ranks module NC NC — Not Connected Note: 1-Rank module 192 RAS I SSTL 74 CAS I SSTL Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) 73 WE I SSTL 18 RESET I CMOS Register Reset 71 BA0 I SSTL Bank Address Bus 1:0 190 BA1 I SSTL 54 BA2 I SSTL Bank Address Bus 2 Greater than 512Mb DDR2 SDRAMS NC I SSTL Not Connected Less than 1Gb DDR2 SDRAMS Clock Signals Clock Enables 1:0 Note: 2-Ranks module Control Signals Address Signals Rev. 1.21, 2007-03 09152006-J5FK-C565 7 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Ball No. Name Pin Type Buffer Type Function 188 A0 I SSTL Address Bus 12:0, Address Signal 10/AutoPrecharge 183 A1 I SSTL 63 A2 I SSTL 182 A3 I SSTL 61 A4 I SSTL 60 A5 I SSTL 180 A6 I SSTL 58 A7 I SSTL 179 A8 I SSTL 177 A9 I SSTL 70 A10 I SSTL AP I SSTL 57 A11 I SSTL 176 A12 I SSTL 196 A13 I SSTL Address Signal 13 NC NC — Not Connected Note: Non CA parity modules based on 256 Mbit component A14 I SSTL Address Signal 14 Note: CA Parity module NC NC — Not Connected Note: Non CA parity module. Less than 1 GBit per DRAM die. A15 I SSTL Address Signal 14 Note: CA Parity module NC NC — Not Connected Note: Non CA parity module. Less than 1 GBit per DRAM die. 174 173 Rev. 1.21, 2007-03 09152006-J5FK-C565 8 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Ball No. Name Pin Type Buffer Type Function Data Bus 63:0 Data Input/Output pins Data Signals 3 DQ0 I/O SSTL 4 DQ1 I/O SSTL 9 DQ2 I/O SSTL 10 DQ3 I/O SSTL 122 DQ4 I/O SSTL 123 DQ5 I/O SSTL 128 DQ6 I/O SSTL 129 DQ7 I/O SSTL 12 DQ8 I/O SSTL 13 DQ9 I/O SSTL 21 DQ10 I/O SSTL 22 DQ11 I/O SSTL 131 DQ12 I/O SSTL 132 DQ13 I/O SSTL 140 DQ14 I/O SSTL 141 DQ15 I/O SSTL 24 DQ16 I/O SSTL 25 DQ17 I/O SSTL 30 DQ18 I/O SSTL 31 DQ19 I/O SSTL 143 DQ20 I/O SSTL 144 DQ21 I/O SSTL 149 DQ22 I/O SSTL 150 DQ23 I/O SSTL 33 DQ24 I/O SSTL 34 DQ25 I/O SSTL 39 DQ26 I/O SSTL 40 DQ27 I/O SSTL 152 DQ28 I/O SSTL 153 DQ29 I/O SSTL 158 DQ30 I/O SSTL 159 DQ31 I/O SSTL 80 DQ32 I/O SSTL 81 DQ33 I/O SSTL 86 DQ34 I/O SSTL 87 DQ35 I/O SSTL 199 DQ36 I/O SSTL 200 DQ37 I/O SSTL 205 DQ38 I/O SSTL Rev. 1.21, 2007-03 09152006-J5FK-C565 9 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Ball No. Name Pin Type Buffer Type Function 206 DQ39 I/O SSTL Data Bus 63:0 89 DQ40 I/O SSTL 90 DQ41 I/O SSTL 95 DQ42 I/O SSTL 96 DQ43 I/O SSTL 208 DQ44 I/O SSTL 209 DQ45 I/O SSTL 214 DQ46 I/O SSTL 215 DQ47 I/O SSTL 98 DQ48 I/O SSTL 99 DQ49 I/O SSTL 107 DQ50 I/O SSTL 108 DQ51 I/O SSTL 217 DQ52 I/O SSTL 218 DQ53 I/O SSTL 226 DQ54 I/O SSTL 227 DQ55 I/O SSTL 110 DQ56 I/O SSTL 111 DQ57 I/O SSTL 116 DQ58 I/O SSTL 117 DQ59 I/O SSTL 229 DQ60 I/O SSTL 230 DQ61 I/O SSTL 235 DQ62 I/O SSTL 236 DQ63 I/O SSTL 42 CB0 I/O SSTL 43 CB1 I/O SSTL 48 CB2 I/O SSTL 49 CB3 I/O SSTL 161 CB4 I/O SSTL 162 CB5 I/O SSTL 167 CB6 I/O SSTL 168 CB7 I/O SSTL Check Bits Rev. 1.21, 2007-03 09152006-J5FK-C565 Check Bits 7:0 Check Bit Input / Output pins Note: NC on Non-ECC module 10 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Ball No. Name Pin Type Buffer Type Function Data Strobes 17:0 Data Strobe Bus 7 DQS0 I/O SSTL 6 DQS0 I/O SSTL 16 DQS1 I/O SSTL 15 DQS1 I/O SSTL 28 DQS2 I/O SSTL 27 DQS2 I/O SSTL 37 DQS3 I/O SSTL 36 DQS3 I/O SSTL 84 DQS4 I/O SSTL 83 DQS4 I/O SSTL 93 DQS5 I/O SSTL 92 DQS5 I/O SSTL 105 DQS6 I/O SSTL 104 DQS6 I/O SSTL 114 DQS7 I/O SSTL 113 DQS7 I/O SSTL 46 DQS8 I/O SSTL 45 DQS8 I/O SSTL 125 DQS9 I/O SSTL 126 DQS9 I/O SSTL 134 DQS10 I/O SSTL 135 DQS10 I/O SSTL 146 DQS11 I/O SSTL 147 DQS11 I/O SSTL 155 DQS12 I/O SSTL 156 DQS12 I/O SSTL 202 DQS13 I/O SSTL 203 DQS13 I/O SSTL 211 DQS14 I/O SSTL 212 DQS14 I/O SSTL 223 DQS15 I/O SSTL 224 DQS15 I/O SSTL 232 DQS16 I/O SSTL 233 DQS16 I/O SSTL 164 DQS17 I/O SSTL 165 DQS17 I/O SSTL Rev. 1.21, 2007-03 09152006-J5FK-C565 11 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Ball No. Name Pin Type Buffer Type Function 125 DM0 I SSTL 134 DM1 I SSTL Data Masks 8:0 Note: ×8 based module 146 DM2 I SSTL 155 DM3 I SSTL 202 DM4 I SSTL 211 DM5 I SSTL 223 DM6 I SSTL 232 DM7 I SSTL 164 DM8 I SSTL 120 SCL I CMOS Serial Bus Clock 119 SDA I/O OD Serial Bus Data 239 SA0 I CMOS Serial Address Select Bus 2:0 240 SA1 I CMOS 101 SA2 I CMOS Data Mask EEPROM Parity 55 ERR_OUT O CMOS PAR_IN I CMOS VREF VDDSPD VDDQ AI — I/O Reference Voltage PWR — EEPROM Power Supply PWR — I/O Driver Power Supply 53, 59, 64, 67, 69, VDD 172, 178, 184, 187, 189, 197 PWR — Power Supply 2, 5, 8, 11, 14, 17, VSS 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 65, 66, 79, 82, 85, 88, 91, 94, 97, 100, 103, 106, 109, 112, 115, 118, 121, 124, 127, 130, 133, 136, 139, 142, 145, 148, 151, 154, 157, 160, 163, 166, 169, 198, 201, 204, 207, 210, 213, 216, 219, 222, 225, 228, 231, 234, 237 GND — Ground Plane Parity bits Power Supplies 1 238 51, 56, 62, 72, 75, 78, 170, 175, 181, 191, 194 Rev. 1.21, 2007-03 09152006-J5FK-C565 12 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Ball No. Name Pin Type Buffer Type Function NC 19, 55, 68, 102, 137, 138, 173, 220, 221 NC — Not connected 195 ODT0 I SSTL 77 ODT1 I SSTL On-Die Termination Control 1:0 Note: 2-Ranks module NC NC — Other Pins Note: 1-Rank modules TABLE 7 Abbreviations for Buffer Type Abbreviation Description SSTL Serial Stub Terminated Logic (SSTL_18) CMOS CMOS Levels OD Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR. TABLE 8 Abbreviations for Pin Type Abbreviation Description I Standard input-only pin. Digital levels. O Output. Digital levels. I/O I/O is a bidirectional input/output signal. AI Input. Analog levels. PWR Power GND Ground NU Not Usable NC Not Connected Rev. 1.21, 2007-03 09152006-J5FK-C565 13 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules FIGURE 1 966 9'' 9'' %$ :( 9''4 1&2'7 966 '4 '46 966 '4 '4 966 '46 '4 966 '4 6$ 966 '46 '4 966 '4 '46 966 '4 6'$ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ Rev. 1.21, 2007-03 09152006-J5FK-C565 966 '4 '46 966 '4 '4 966 '46 5(6(7 966 '4 '4 966 '46 '4 966 '4 '46 966 '4 &% 966 '46 &% 966 &.( 1&%$ 9''4 $ $ 9''4 9'' 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 966 1& $$3 9''4 &$6 1&6 9''4 '4 966 '46 '4 966 '4 '46 966 '4 '4 966 1& '46 966 '4 '4 966 '46 '4 966 6&/ %$&.6,'( 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 95() '4 966 '46 '4 966 '4 '46 966 1& '4 966 '4 '46 966 '4 '4 966 '46 '4 966 &% '46 966 &% 9''4 9'' 1& $ 9'' $ $ )52176,'( Pin Configuration for RDIMM (240 pins) 14 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ '4 966 1&'46 '4 966 '4 '0'46 966 1& '4 966 '4 '0'46 966 '4 '4 966 1&'46 '4 966 &% '0'46 966 &% 9''4 9'' 1&$ $ 9'' $ $ 9'' 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ &. $ %$ 5$6 9''4 1&$ 966 '4 '0'46 966 '4 '4 966 1&'46 '4 966 '4 1& 966 1&'46 '4 966 '4 '0'46 966 '4 9''63' 6$ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 966 '4 '0'46 966 '4 '4 966 1&'46 1& 966 '4 '4 966 1&'46 '4 966 '4 '0'46 966 '4 &% 966 1&'46 &% 966 1&&.( 1&$ 9''4 $ $ 9''4 $ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ &. 9'' 9'' 9''4 6 2'7 9'' '4 966 1&'46 '4 966 '4 '0'46 966 '4 '4 966 1& '0'46 966 '4 '4 966 1&'46 '4 966 6$ 0337 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules 3 Electrical Characteristics This chapter lists the electrical characteristics. 3.1 Absolute Maximum Ratings Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 9 at any time. TABLE 9 Absolute Maximum Ratings Symbol VDD VDDQ VDDL VIN, VOUT TSTG Parameter Rating Unit Note Min. Max. Voltage on VDD pin relative to VSS –1.0 +2.3 V 1) Voltage on VDDQ pin relative to VSS –0.5 +2.3 V 1)2) Voltage on VDDL pin relative to VSS –0.5 +2.3 V 1)2) Voltage on any pin relative to VSS –0.5 +2.3 V 1) °C 1)2) Storage Temperature –55 +100 1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV. 2) Storage Temperature is the case surface temperature on the center/top side of the DRAM. Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. TABLE 10 DRAM Component Operating Temperature Range Symbol TOPER Parameter Rating Operating Temperature Min. Max. 0 95 Unit Note °C 1)2)3)4) 1) Operating Temperature is the case surface temperature on the center / top side of the DRAM. 2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case temperature must be maintained between 0 - 95 °C under all other specification parameters. 3) Above 85 °C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 µs 4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50 % Rev. 1.21, 2007-03 09152006-J5FK-C565 15 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules 3.2 DC Operating Conditions This chapter contains the DC operating conditions tables. TABLE 11 Operating Conditions Parameter Symbol Operating temperature (ambient) DRAM Case Temperature Storage Temperature Barometric Pressure (operating & storage) Operating Humidity (relative) TOPR TCASE TSTG PBar HOPR Values Unit Note Min. Max. 0 +65 °C — 0 +95 °C 1)2)3)4) – 50 +100 °C — +69 +105 kPa 5) 10 90 % — 1) 2) 3) 4) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. Within the DRAM Component Case Temperature Range all DRAM specifications will be supported Above 85 °C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50 %. 5) Up to 3000 m. TABLE 12 Supply Voltage Levels and DC Operating Conditions Parameter Device Supply Voltage Output Supply Voltage Input Reference Voltage SPD Supply Voltage DC Input Logic High DC Input Logic Low Symbol VDD VDDQ VREF VDDSPD VIH(DC) VIL (DC) IL Values Unit Note Min. Typ. Max. 1.7 1.8 1.9 V — 1.7 1.8 1.9 V 1) 0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ V 2) 1.7 — 3.6 V — VREF + 0.125 — V — – 0.30 — VDDQ + 0.3 VREF – 0.125 V — In / Output Leakage Current –5 — 5 µA 1) Under all conditions, VDDQ must be less than or equal to VDD 2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise in VDDQ. 3) Input voltage for any connector pin under test of 0 V ≤ VIN ≤ VDDQ + 0.3 V; all other pins at 0 V. Current is per pin Rev. 1.21, 2007-03 09152006-J5FK-C565 16 3) Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules 3.3 AC Characteristics This chapter describes the AC characteristics. 3.3.1 Speed Grades Definitions This chapter contains the Speed Grades Definitions tables. TABLE 13 Speed Grade Definition Speed Bins for DDR2–800E Speed Grade DDR2–800E QAG Sort Name –2.5 CAS-RCD-RP latencies 6–6–6 Parameter Clock Frequency @ CL = 3 @ CL = 4 @ CL = 5 @ CL = 6 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Unit Note tCK Symbol Min. Max. — tCK tCK tCK tCK tRAS tRC tRCD tRP 5 8 ns 1)2)3)4) 3.75 8 ns 1)2)3)4) 3 8 ns 1)2)3)4) 2.5 8 ns 1)2)3)4) 45 70000 ns 1)2)3)4)5) 60 — ns 1)2)3)4) 15 — ns 1)2)3)4) 15 — ns 1)2)3)4) 1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI. Rev. 1.21, 2007-03 09152006-J5FK-C565 17 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules TABLE 14 Speed Grade Definition Speed Bins for DDR2–667 Speed Grade DDR2–667C DDR2–667D QAG Sort Name –3 –3S CAS-RCD-RP latencies 4–4–4 5–5–5 Parameter Clock Frequency @ CL = 3 @ CL = 4 @ CL = 5 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Unit Note tCK Symbol Min. Max. Min. Max. — tCK tCK tCK tRAS tRC tRCD tRP 5 8 5 8 ns 1)2)3)4) 3 8 3.75 8 ns 1)2)3)4) 3 8 3 8 ns 1)2)3)4) 45 70000 45 70000 ns 1)2)3)4)5) 57 — 60 — ns 1)2)3)4) 12 — 15 — ns 1)2)3)4) 12 — 15 — ns 1)2)3)4) 1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) . 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI. TABLE 15 Speed Grade Definition Speed Bins for DDR2-533 and DDR2-400 Speed Grade DDR2–533C QAG Sort Name –3.7 CAS-RCD-RP latencies @ CL = 3 @ CL = 4 @ CL = 5 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Unit Note –5 4–4–4 Parameter Clock Frequency DDR2–400B tCK 3–3–3 Symbol Min. Max. Min. Max. — tCK tCK tCK tRAS tRC tRCD tRP 5 8 5 8 ns 1)2)3)4) 3.75 8 5 8 ns 1)2)3)4) 3.75 8 5 8 ns 1)2)3)4) 45 70000 40 70000 ns 1)2)3)4)5) 60 — 55 — ns 1)2)3)4) 15 — 15 — ns 1)2)3)4) 15 — 15 — ns 1)2)3)4) 1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) . 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI. Rev. 1.21, 2007-03 09152006-J5FK-C565 18 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules 3.3.2 AC Timing Parameters This chapter contains the AC Timing Parameters. TABLE 16 Timing Parameter by Speed Grade - DDR2–800 Parameter Symbol DDR2–800 Unit Note1)2)3)4)5)6)7) 8) tAC DQS output access time from CK / CK tDQSCK Average clock high pulse width tCH.AVG Average clock low pulse width tCL.AVG Average clock period tCK.AVG DQ and DM input setup time tDS.BASE DQ and DM input hold time tDH.BASE Control & address input pulse width for each input tIPW tDIPW DQ and DM input pulse width for each input Data-out high-impedance time from CK / CK tHZ DQS/DQS low-impedance time from CK / CK tLZ.DQS DQ low impedance time from CK/CK tLZ.DQ DQS-DQ skew for DQS & associated DQ signals tDQSQ CK half pulse width tHP DQ output access time from CK / CK Min. Max. –400 +400 ps –350 +350 ps 9) 10)11) 9) 0.48 0.52 0.48 0.52 tCK.AVG tCK.AVG 2500 8000 ps 10)11) 50 — ps 12)13)14) 125 — ps 12)13)15) 0.6 — 0.35 — tCK.AVG — tCK.AVG — — tAC.MAX tAC.MAX ps 9)16) ps 9)16) tAC.MAX ps 9)16) — 200 ps 17) Min (tCH.ABS, tCL.ABS) __ ps 18) — 300 ps 19) DQ/DQS output hold time from DQS tQHS tQH tHP – tQHS — ps 20) Write command to DQS associated clock edges WL RL – 1 DQ hold skew factor tAC.MIN 2 x tAC.MIN nCK — – 0.25 + 0.25 tCK.AVG 21) tDQSH tDQSL tDSS tDSH tWPST tWPRE tLS.BASE tLH.BASE tRPRE tRPST tRAS tRRD 0.35 — — 0.35 — tRRD DQS latching rising transition to associated clock tDQSS edges DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Write postamble Write preamble Address and control input setup time Address and control input hold time Read preamble Read postamble Active to precharge command Active to active command period for 1KB page size products Active to active command period for 2KB page size products Rev. 1.21, 2007-03 09152006-J5FK-C565 10)11) 19 0.2 — 0.2 — 0.4 0.6 0.35 — tCK.AVG tCK.AVG tCK.AVG tCK.AVG tCK.AVG tCK.AVG 175 — ps 22)23) 250 — ps 23)24) 0.9 1.1 25)26) 0.4 0.6 tCK.AVG tCK.AVG 45 70000 ns 28) 7.5 — ns 28) 10 — ns 28) — 21) 21) — — 25)27) Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Parameter Symbol DDR2–800 Unit Note1)2)3)4)5)6)7) 8) Min. Max. Four Activate Window for 1KB page size products tFAW 35 — ns 28) Four Activate Window for 2KB page size products tFAW 45 — ns 28) tCCD tWR Write recovery time Auto-Precharge write recovery + precharge time tDAL Internal write to read command delay tWTR Internal Read to Precharge command delay tRTP Exit self-refresh to a non-read command tXSNR Exit self-refresh to read command tXSRD Exit precharge power-down to any valid tXP 2 — nCK — 15 — ns 28) WR + tnRP — nCK 29)30) 7.5 — ns 28)31) 7.5 — ns 28) tRFC +10 — ns 28) 200 — nCK — 2 — nCK — tXARD tXARDS 2 — nCK — 8 – AL — nCK — CKE minimum pulse width ( high and low pulse width) tCKE 3 — nCK 32) ODT turn-on delay tAOND tAON tAONPD 2 2 nCK — tAC.MIN tAC.MIN + 2 tAC.MAX + 0.7 2 x tCK.AVG + tAC.MAX + 1 ns 9)33) ns — tAOFD tAOF tAOFPD 2.5 2.5 nCK — tAC.MIN tAC.MIN + 2 tAC.MAX + 0.6 ns 2.5 x tCK.AVG + ns tAC.MAX + 1 — tANPD tAXPD tMRD tMOD tOIT tDELAY 3 –– — CAS to CAS command delay command (other than NOP or Deselect) Exit power down to read command Exit active power-down mode to read command (slow exit, lower power) ODT turn-on ODT turn-on (Power down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power down mode) ODT to power down entry latency ODT to power down exit latency Mode register set command cycle time MRS command to ODT update delay OCD drive mode output delay Minimum time clocks remain ON after CKE asynchronously drops LOW 8 nCK 34)35) nCK — 2 — nCK — 0 12 ns 28) 0 12 ns 28) tLS + tCK .AVG + –– tLH ns — 1) For details and notes see the relevant Qimonda component data sheet 2) VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V. See notes 5)6)7)8) 3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 7) The output timing reference voltage level is VTT. Rev. 1.21, 2007-03 09152006-J5FK-C565 20 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules 8) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min). 9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272 ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and tDQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED) = - 900 ps – 293 ps = – 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!) 10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution. 11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations). 12) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See Figure 2. 13) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. 14) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal ((L/U/R)DQS / DQS) crossing. 15) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and VIH.DC.MIN. See Figure 2. 16) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) . 17) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between DQS / DQS and associated DQ in any given cycle. 18) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the minimum of the actual instantaneous clock low time. 19) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation of the output drivers. 20) tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.} Examples: 1) If the system provides tHP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system provides tHP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum. 21) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. 22) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied to the device under test. See Figure 3. 23) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. 24) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied to the device under test. See Figure 3. 25) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). Figure 1 shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. 26) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.PER.MIN = – 72 ps and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX + tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!). Rev. 1.21, 2007-03 09152006-J5FK-C565 21 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules 27) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX + tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!). 28) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which tRP = 15 ns, the device will support tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter. 29) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For DDR2–533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 30) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR. 31) tWTR is at lease two clocks (2 x tCK) independent of operation frequency. 32) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH. 33) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND. 34) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. 35) When the device is operated with input clock jitter, this parameter needs to be derated by {–tJIT.DUTY.MAX – tERR(6-10PER).MAX} and {–tJIT.DUTY.MIN – tERR(6-10PER).MIN } of the actual input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272 ps, tERR(6- 10PER).MAX = + 293 ps, tJIT.DUTY.MIN = – 106 ps and tJIT.DUTY.MAX = + 94 ps, then tAOF.MIN(DERATED) = tAOF.MIN + {– tJIT.DUTY.MAX – tERR(6-10PER).MAX} = – 450 ps + {– 94 ps – 293 ps} = – 837 ps and tAOF.MAX(DERATED) = tAOF.MAX + {– tJIT.DUTY.MIN – tERR(6-10PER).MIN} = 1050 ps + {106 ps + 272 ps} = + 1428 ps. (Caution on the MIN/MAX usage!) TABLE 17 Timing Parameter by Speed Grade - DDR2–667 Parameter Symbol DDR2–667 Unit Note1)2)3)4)5)6)7) 8) tAC DQS output access time from CK / CK tDQSCK Average clock high pulse width tCH.AVG Average clock low pulse width tCL.AVG Average clock period tCK.AVG DQ and DM input setup time tDS.BASE DQ and DM input hold time tDH.BASE Control & address input pulse width for each input tIPW DQ and DM input pulse width for each input tDIPW tHZ Data-out high-impedance time from CK / CK DQS/DQS low-impedance time from CK / CK tLZ.DQS DQ low impedance time from CK/CK tLZ.DQ DQS-DQ skew for DQS & associated DQ signals tDQSQ CK half pulse width tHP DQ output access time from CK / CK Min. Max. –450 +450 ps –400 +400 ps 9) 10)11) 9) 0.48 0.52 0.48 0.52 tCK.AVG tCK.AVG 3000 8000 ps — 100 — ps 12)13)14) 175 — ps 13)14)15) 0.6 — 0.35 — tCK.AVG — tCK.AVG — — ps 9)16) tAC.MIN 2 x tAC.MIN tAC.MAX tAC.MAX tAC.MAX ps 9)16) ps 9)16) — 240 ps 17) Min (tCH.ABS, tCL.ABS) __ ps 18) — 340 ps 19) DQ/DQS output hold time from DQS tQHS tQH tHP – tQHS — ps 20) Write command to DQS associated clock edges WL RL–1 nCK — DQ hold skew factor Rev. 1.21, 2007-03 09152006-J5FK-C565 22 10)11) Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Parameter Symbol DDR2–667 Unit Note1)2)3)4)5)6)7) 8) Min. Max. – 0.25 + 0.25 tCK.AVG 21) tDQSH tDQSL tDSS tDSH tWPST tWPRE tLS.BASE tLH.BASE tRPRE tRPST tRAS tRRD 0.35 — — 0.35 — tRRD DQS latching rising transition to associated clock tDQSS edges 0.35 — tCK.AVG tCK.AVG tCK.AVG tCK.AVG tCK.AVG tCK.AVG 200 — ps 22)23) 275 — ps 23)24) 0.9 1.1 25)26) 0.4 0.6 tCK.AVG tCK.AVG 45 70000 ns 28) 7.5 — ns 28) 10 — ns 28) Four Activate Window for 1KB page size products tFAW 37.5 — ns 28) Four Activate Window for 2KB page size products tFAW 50 — ns 28) CAS to CAS command delay tCCD tWR Auto-Precharge write recovery + precharge time tDAL Internal write to read command delay tWTR Internal Read to Precharge command delay tRTP Exit self-refresh to a non-read command tXSNR Exit self-refresh to read command tXSRD Exit precharge power-down to any valid tXP 2 — nCK — Write recovery time 15 — ns 28) WR + tnRP — nCK 29)30) 7.5 — ns 28)31) 7.5 — ns 28) tRFC +10 — ns 28) 200 — nCK — 2 — nCK — tXARD tXARDS 2 — nCK — 7 – AL — nCK — CKE minimum pulse width ( high and low pulse width) tCKE 3 — nCK 32) ODT turn-on delay tAOND tAON tAONPD 2 2 nCK — tAC.MIN tAC.MIN + 2 tAC.MAX + 0.7 2 x tCK.AVG + tAC.MAX + 1 ns 9)33) ns — tAOFD tAOF tAOFPD 2.5 2.5 nCK — tAC.MIN tAC.MIN + 2 tAC.MAX + 0.6 ns 2.5 x tCK.AVG + ns tAC.MAX + 1 DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Write postamble Write preamble Address and control input setup time Address and control input hold time Read preamble Read postamble Active to precharge command Active to active command period for 1KB page size products Active to active command period for 2KB page size products 0.2 — 0.2 — 0.4 0.6 — 21) 21) — — 25)27) command (other than NOP or Deselect) Exit power down to read command Exit active power-down mode to read command (slow exit, lower power) ODT turn-on ODT turn-on (Power down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power down mode) Rev. 1.21, 2007-03 09152006-J5FK-C565 23 34)35) — Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Parameter Symbol DDR2–667 Unit Note1)2)3)4)5)6)7) 8) ODT to power down entry latency ODT to power down exit latency Mode register set command cycle time MRS command to ODT update delay OCD drive mode output delay Minimum time clocks remain ON after CKE asynchronously drops LOW tANPD tAXPD tMRD tMOD tOIT tDELAY Min. Max. 3 –– 8 nCK — nCK — 2 — nCK — 0 12 ns 28) 0 12 ns 28) tLS + tCK .AVG + –– tLH ns — 1) For details and notes see the relevant Qimonda component data sheet 2) VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V. See notes 5)6)7)8) 3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 7) The output timing reference voltage level is VTT. 8) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min). 9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272 ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and tDQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED) = - 900 ps – 293 ps = – 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!) 10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution. 11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations). 12) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See Figure 2. 13) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. 14) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal ((L/U/R)DQS / DQS) crossing. 15) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and VIH.DC.MIN. See Figure 2. 16) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) . 17) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between DQS / DQS and associated DQ in any given cycle. 18) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the minimum of the actual instantaneous clock low time. Rev. 1.21, 2007-03 09152006-J5FK-C565 24 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules 19) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation of the output drivers. 20) tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.} Examples: 1) If the system provides tHP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system provides tHP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum. 21) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. 22) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied to the device under test. See Figure 3. 23) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. 24) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied to the device under test. See Figure 3. 25) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). Figure 1 shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. 26) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.PER.MIN = – 72 ps and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX + tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!). 27) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX + tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!). 28) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which tRP = 15 ns, the device will support tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter. 29) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For DDR2–533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 30) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR. 31) tWTR is at lease two clocks (2 x tCK) independent of operation frequency. 32) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH. 33) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND. 34) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. 35) When the device is operated with input clock jitter, this parameter needs to be derated by {–tJIT.DUTY.MAX – tERR(6-10PER).MAX} and {–tJIT.DUTY.MIN – tERR(6-10PER).MIN } of the actual input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272 ps, tERR(6- 10PER).MAX = + 293 ps, tJIT.DUTY.MIN = – 106 ps and tJIT.DUTY.MAX = + 94 ps, then tAOF.MIN(DERATED) = tAOF.MIN + {– tJIT.DUTY.MAX – tERR(6-10PER).MAX} = – 450 ps + {– 94 ps – 293 ps} = – 837 ps and tAOF.MAX(DERATED) = tAOF.MAX + {– tJIT.DUTY.MIN – tERR(6-10PER).MIN} = 1050 ps + {106 ps + 272 ps} = + 1428 ps. (Caution on the MIN/MAX usage!) Rev. 1.21, 2007-03 09152006-J5FK-C565 25 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules FIGURE 2 Method for calculating transitions and endpoint 92+[P9 977[P9 92+[P9 977[P9 W/= W+= W535(EHJLQSRLQW W5367 H QGSRLQW 92/[P9 977[P9 92/[P9 977[P9 7 7 7 7 W+=W5367 HQGSRLQW 77 W/=W535( E HJLQSRLQW 7 7 FIGURE 3 Differential input waveform timing - tDS and tDS '46 '46 W'6 W'+ W'6 W'+ 9''4 9,+DFPLQ 9,+GFPLQ 95()GF 9,/GF PD[ 9,/DF PD[ 966 FIGURE 4 Differential input waveform timing - tlS and tlH &. &. W,6 W,6 W,+ W,+ 9''4 9,+DFPLQ 9,+GFPLQ 95()GF 9,/GFPD[ 9,/DFPD[ 966 Rev. 1.21, 2007-03 09152006-J5FK-C565 26 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules TABLE 18 Timing Parameter by Speed Grade - DDR2–533 Parameter Symbol DDR2–533 Unit Note1)2)3)4)5) 6)7) Min. Max. tAC tCCD tCH tCKE tCL tDAL –500 +500 ps — 2 — — 0.45 0.55 3 — 0.45 0.55 WR + tRP — tCK tCK tCK tCK tCK Minimum time clocks remain ON after CKE asynchronously drops LOW tDELAY tIS + tCK + tIH — ns 9) DQ and DM input hold time (differential data strobe) tDH(base) 225 — ps 10) –25 — ps 11) tDIPW tDQSCK tDQSL,H tDQSQ 0.35 — tCK — –450 +450 ps — 0.35 — tCK — — 300 ps 11) tDQSS tDS(base) – 0.25 + 0.25 tCK — 100 — ps 11) –25 — ps 11) tDSH 0.2 — tCK — DQS falling edge to CK setup time (write cycle) tDSS 0.2 — tCK — 37.5 — ns — 50 — ns 13) DQ output access time from CK / CK CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time DQ and DM input hold time (single ended data tDH1(base) strobe) DQ and DM input pulse width (each input) DQS output access time from CK / CK DQS input low (high) pulse width (write cycle) DQS-DQ skew (for DQS & associated DQ signals) Write command to 1st DQS latching transition DQ and DM input setup time (differential data strobe) DQ and DM input setup time (single ended data tDS1(base) strobe) DQS falling edge hold time from CK (write cycle) Four Activate Window period Clock half period Data-out high-impedance time from CK / CK Address and control input hold time Address and control input pulse width (each input) Address and control input setup time DQ low-impedance time from CK / CK DQS low-impedance from CK / CK Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS Rev. 1.21, 2007-03 09152006-J5FK-C565 tFAW tHP tHZ tIH(base) tIPW 27 — — 8)18) 12) MIN. (tCL, tCH) tIS(base) tLZ(DQ) tLZ(DQS) tMRD tOIT tQH — — tAC.MAX ps 13) 375 — ps 11) 0.6 — tCK — 250 — ps 11) 2 × tAC.MIN ps 14) tAC.MIN tAC.MAX tAC.MAX ps 14) 2 — tCK — 0 12 ns — tHP –tQHS — — — Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Parameter Symbol DDR2–533 Unit Note1)2)3)4)5) 6)7) Data hold skew factor Average periodic refresh Interval tQHS tREFI Min. Max. — 400 ps — — 7.8 µs 14)15) — 3.9 µs 16)18) Auto-Refresh to Active/Auto-Refresh command period tRFC 75 — ns 17) Precharge-All (4 banks) command period tRP tRP tRPRE tRPST tRRD tRP + 1tCK 15 + 1tCK — ns — — ns — 0.9 1.1 14) 0.40 0.60 tCK tCK 7.5 — ns 14)18) 10 — ns 16)20) tRTP tWPRE tWPST tWR 7.5 — ns — 0.25 x tCK — — 0.40 0.60 tCK tCK 15 — ns — Write recovery time for write with AutoPrecharge WR tWR/tCK tCK 20) Internal Write to Read command delay tWTR tXARD 7.5 — ns 21) 2 — tCK 22) Exit active power-down mode to Read command (slow exit, lower power) tXARDS 6 – AL — tCK 22) Exit precharge power-down to any valid command (other than NOP or Deselect) tXP 2 — tCK — Exit Self-Refresh to non-Read command tXSNR tXSRD tRFC +10 — ns — 200 — tCK — Precharge-All (8 banks) command period Read preamble Read postamble Active bank A to Active bank B command period Internal Read to Precharge command delay Write preamble Write postamble Write recovery time for write without AutoPrecharge Exit power down to any valid command (other than NOP or Deselect) Exit Self-Refresh to Read command 14) 19) 1) For details and notes see the relevant Qimonda component data sheet 2) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V. See notes 5)6)7)8) 3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode. 6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 7) The output timing reference voltage level is VTT. 8) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MR. 9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 10) For timing definition, refer to the Component data sheet. 11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle. 12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). Rev. 1.21, 2007-03 09152006-J5FK-C565 28 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules 13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These parameters are verified by design and characterization, but not subject to production test. 14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C and 95 °C. 15) 0 °C≤ TCASE ≤ 85 °C 16) 85 °C < TCASE ≤ 95 °C 17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 18) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 3 “Ordering Information for RoHS Compliant Products” on Page 5. 19) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 20) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MRS. 21) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz. 22) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active powerdown mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow power-down exit timing tXARDS has to be satisfied. TABLE 19 Timing Parameter by Speed Grade - DDR2-400 Parameter Symbol DDR2–400 Unit Note1)2)3)4)5) 6)7) Min. Max. tAC tCCD tCH tCKE tCL tDAL –600 +600 ps — 2 — — 0.45 0.55 3 — 0.45 0.55 WR + tRP — tCK tCK tCK tCK tCK Minimum time clocks remain ON after CKE asynchronously drops LOW tDELAY tIS + tCK + tIH –– ns 9) DQ and DM input hold time (differential data strobe) tDH(base) 275 –– ps 10) –25 — ps 11) tDIPW tDQSCK tDQSL,H tDQSQ 0.35 — tCK — –500 +500 ps — 0.35 — tCK — — 350 ps 11) tDQSS tDS(base) – 0.25 + 0.25 tCK — 150 — ps 11) tDS1(base) –25 — ps 11) DQ output access time from CK / CK CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time DQ and DM input hold time (single ended data tDH1(base) strobe) DQ and DM input pulse width (each input) DQS output access time from CK / CK DQS input low (high) pulse width (write cycle) DQS-DQ skew (for DQS & associated DQ signals) Write command to 1st DQS latching transition DQ and DM input setup time (differential data strobe) DQ and DM input setup time (single ended data strobe) Rev. 1.21, 2007-03 09152006-J5FK-C565 29 — — — 8)22) Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Parameter Symbol DDR2–400 Unit Note1)2)3)4)5) 6)7) Min. Max. tDSH 0.2 — DQS falling edge to CK setup time (write cycle) tDSS 0.2 — tCK — 37.5 — ns — 50 — ns 13) DQS falling edge hold time from CK (write cycle) Four Activate Window period Clock half period Data-out high-impedance time from CK / CK Address and control input hold time Address and control input pulse width (each input) Address and control input setup time DQ low-impedance time from CK / CK DQS low-impedance from CK / CK Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS Data hold skew factor Average periodic refresh Interval tFAW tHP tHZ tIH(base) tIPW tCK 12) MIN. (tCL, tCH) tIS(base) tLZ(DQ) tLZ(DQS) tMRD tOIT tQH tQHS tREFI — — tAC.MAX ps 13) 475 — ps 11) 0.6 — tCK — 350 — ps 11) 2 × tAC.MIN ps 14) tAC.MIN tAC.MAX tAC.MAX ps 14) 2 — tCK — 0 12 ns — tHP –tQHS — — — — 450 ps — — 7.8 µs 14)15) — 3.9 µs 16)18) Auto-Refresh to Active/Auto-Refresh command period tRFC 75 — ns 17) Precharge-All (4 banks) command period tRP tRP tRPRE tRPST tRRD tRP + 1tCK 15 + 1tCK — ns — — ns — 0.9 1.1 14) 0.40 0.60 tCK tCK 7.5 — ns 14)18) 10 — ns 16)20) tRTP tWPRE tWPST tWR 7.5 — ns — 0.25 x tCK — — 0.40 0.60 tCK tCK 15 — ns — Write recovery time for write with AutoPrecharge WR tWR/tCK tCK 20) Internal Write to Read command delay tWTR tXARD 10 — ns 21) 2 — tCK 22) Exit active power-down mode to Read command (slow exit, lower power) tXARDS 6 – AL — tCK 22) Exit precharge power-down to any valid command (other than NOP or Deselect) tXP 2 — tCK — Precharge-All (8 banks) command period Read preamble Read postamble Active bank A to Active bank B command period Internal Read to Precharge command delay Write preamble Write postamble Write recovery time for write without AutoPrecharge Exit power down to any valid command (other than NOP or Deselect) Rev. 1.21, 2007-03 09152006-J5FK-C565 30 14) 19) Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Parameter Symbol DDR2–400 Unit Note1)2)3)4)5) 6)7) Exit Self-Refresh to non-Read command Exit Self-Refresh to Read command tXSNR tXSRD Min. Max. tRFC +10 — ns — 200 — tCK — 1) For details and notes see the relevant Qimonda component data sheet 2) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V. See notes 5)6)7)8) 3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode. 6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 7) The output timing reference voltage level is VTT. 8) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MR. 9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 10) For timing definition, refer to the Component data sheet. 11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle. 12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). 13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These parameters are verified by design and characterization, but not subject to production test. 14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C and 95 °C. 15) 0 °C≤ TCASE ≤ 85 °C 16) 85 °C < TCASE ≤ 95 °C 17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 18) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 3 “Ordering Information for RoHS Compliant Products” on Page 5. 19) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 20) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MRS. 21) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz. 22) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active powerdown mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow power-down exit timing tXARDS has to be satisfied. Rev. 1.21, 2007-03 09152006-J5FK-C565 31 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules 3.3.3 ODT AC Electrical Characteristics This chapter contains the ODT AC electrical characteristics tables. TABLE 20 ODT AC Characteristics and Operating Conditions for DDR2-667 & DDR2-800 Symbol tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD Parameter / Condition Values Unit Note Min. Max. ODT turn-on delay 2 2 tCK — ODT turn-on tAC.MIN tAC.MIN + 2 ns tAC.MAX + 0.7 ns 2 tCK + tAC.MAX + 1 ns ns 1) ns — ODT turn-on (Power-Down Modes) ODT turn-off delay 2.5 2.5 tCK — ODT turn-off tAC.MAX + 0.6 ns 2.5 tCK + tAC.MAX + 1 ns ns 2) ODT turn-off (Power-Down Modes) tAC.MIN tAC.MIN + 2 ns ns — ODT to Power Down Mode Entry Latency 3 — 8 — tCK tCK — ODT Power Down Exit Latency — 1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measure from tAOND. 2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. TABLE 21 ODT AC Characteristics and Operating Conditions for DDR2-533/DDR2-400 Symbol tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD Parameter / Condition Values Unit Note Min. Max. ODT turn-on delay 2 2 tCK — ODT turn-on tAC.MIN tAC.MIN + 2 ns tAC.MAX + 1 ns 2 tCK + tAC.MAX + 1 ns ns 1) ns — ODT turn-on (Power-Down Modes) ODT turn-off delay 2.5 2.5 tCK — ODT turn-off tAC.MAX + 0.6 ns 2.5 tCK + tAC.MAX + 1 ns ns 2) ODT turn-off (Power-Down Modes) tAC.MIN tAC.MIN + 2 ns ns — ODT to Power Down Mode Entry Latency 3 — 8 — tCK tCK — ODT Power Down Exit Latency — 1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measure from tAOND. 2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. Rev. 1.21, 2007-03 09152006-J5FK-C565 32 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules 3.4 IDD Specifications and Conditions This chapter describes the IDD Specifications and Conditions. TABLE 22 IDD Measurement Conditions Parameter Symbol Note1)2) 3)4)5)6) Operating Current 0 One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. IDD0 Operating Current 1 IDD1 One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, tRCD = tRCD.MIN, AL = 0, CL = CL.MIN; CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Precharge Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING IDD2N Precharge Power-Down Current Other control and address inputs are STABLE, Data bus inputs are FLOATING. IDD2P Precharge Quiet Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE, Data bus inputs are FLOATING. IDD2Q Active Power-Down Current All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit); IDD3P(0) Active Power-Down Current All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit); IDD3P(1) Active Standby Current Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA. IDD3N Operating Current Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX., tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA. IDD4R Operating Current IDD4W Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; Burst Refresh Current IDD5B tCK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Distributed Refresh Current IDD5D tCK = tCK.MIN, Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Rev. 1.21, 2007-03 09152006-J5FK-C565 33 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Parameter Symbol Note1)2) 3)4)5)6) Self-Refresh Current CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data bus inputs are FLOATING. RESET is LOW. IDD6 current values are guaranteed up to TCASE of 85 °C max. IDD6 All Bank Interleave Read Current IDD7 All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address bus inputs are STABLE during DESELECTS. IOUT = 0 mA. 1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V 2) Definitions for IDD see Table 23 3) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P 4) RESET signal is HIGH for all currents, except for IDD6 (Self Refresh) 5) All current measurements includes Register and PLL current consumption 6) For details and notes see the relevant QIMONDA component data sheet TABLE 23 Definitions for IDD Parameter Description LOW VIN ≤ VIL(ac).MAX, HIGH is defined as VIN ≥ VIH(ac).MIN STABLE inputs are stable at a HIGH or LOW level FLOATING inputs are VREF = VDDQ /2 SWITCHING inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ signals not including mask or strobes. Rev. 1.21, 2007-03 09152006-J5FK-C565 34 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules TABLE 24 Product Type HYS72T32000HR–2.5–A HYS72T64001HR–2.5–A HYS72T64020HR–2.5–A IDD Specification HYS72T[32000/64001/64020]HR–2.5–A Organization 256MB 512MB 512MB ×72 ×72 ×72 1 Rank 1 Rank 2 Ranks –2.5 –2.5 –2.5 Symbol Max. Max. Max. IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3N IDD3P(MRS= 0) IDD3P(MRS= 1) IDD4R IDD4W IDD5B IDD5D IDD6 IDD7 1110 1780 1200 Unit Note1) 1150 mA 2) 1960 1240 mA 2) 880 1330 1330 mA 3) 480 520 520 mA 3) 750 1060 1060 mA 3) 880 1330 1330 mA 3) 630 830 830 mA 3) 480 520 520 mA 3) 1560 2680 1600 mA 2) 1650 2860 1690 mA 2) 1290 2140 1330 mA 2) 480 540 540 mA 3)4) 35 70 70 mA 3)4) 2) 3220 1870 mA 1) Module IDD is calculated on the basis of component IDD and currents includes Registers and PLL. ODT disabled. IDD1, IDD4R and IDD7 are 1830 defined with the outputs disabled. 2) The other rank is in IDD2P Precharge Power-Down Standby Current mode 3) Both ranks are in the same IDD mode 4) Values for 0 °C < TCASE ≤ 85 °C Rev. 1.21, 2007-03 09152006-J5FK-C565 35 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules TABLE 25 IDD Specification HYS72T[32000/64001/64020]HR–3–A Unit Note1) 1010 mA 2) 1950 1100 mA 2) 790 1410 1200 mA 3) 430 680 470 mA 3) 660 1140 930 mA 3) 790 1410 1200 mA 3) 560 940 730 mA 3) 430 690 480 mA 3) 1380 2580 1420 mA 2) 1420 2670 1460 mA 2) 1240 2310 1280 mA 2) 440 700 490 mA 3)4) 35 70 70 mA 3)4) Product Type HYS72T32000HR–3–A HYS72T64001HR–3–A HYS72T64020HR–3–A Organization 256MB 512MB 512MB ×72 ×72 ×72 1 Rank 1 Rank 2 Ranks –3 –3 –3 Symbol Max. Max. Max. IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3N IDD3P(MRS= 0) IDD3P(MRS= 1) IDD4R IDD4W IDD5B IDD5D IDD6 IDD7 970 1770 1060 2) 3210 1730 mA 1) Module IDD is calculated on the basis of component IDD and currents includes Registers and PLL. ODT disabled. IDD1, IDD4R and IDD7 are 1690 defined with the outputs disabled. 2) The other rank is in IDD2P Precharge Power-Down Standby Current mode 3) Both ranks are in the same IDD mode 4) Values for 0 °C ≤ TCASE ≤ 85 °C Rev. 1.21, 2007-03 09152006-J5FK-C565 36 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules TABLE 26 IDD Specification HYS72T[32000/64001/64020]HR–3S–A Unit Note1) 980 mA 2) 1870 1060 mA 2) 790 1410 1200 mA 3) 430 680 470 mA 3) 660 1140 930 mA 3) 790 1410 1200 mA 3) 560 940 730 mA 3) 430 690 480 mA 3) 1380 2580 1420 mA 2) 1420 2670 1460 mA 2) 1240 2310 1280 mA 2) 440 700 490 mA 3)4) 35 70 70 mA 3)4) Product Type HYS72T32000HR–3S–A HYS72T64001HR–3S–A HYS72T64020HR–3S–A Organization 256MB 512MB 512MB ×72 ×72 ×72 1 Rank 1 Rank 2 Ranks –3S –3S –3S Symbol Max. Max. Max. IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3N IDD3P(MRS= 0) IDD3P(MRS= 1) IDD4R IDD4W IDD5B IDD5D IDD6 IDD7 940 1710 1020 2) 3080 1670 mA 1) Module IDD is calculated on the basis of component IDD and currents includes Registers and PLL. ODT disabled. IDD1, IDD4R and IDD7 are 1630 defined with the outputs disabled. 2) The other rank is in IDD2P Precharge Power-Down Standby Current mode 3) Both ranks are in the same IDD mode 4) Values for 0 °C ≤ TCASE ≤ 85 °C Rev. 1.21, 2007-03 09152006-J5FK-C565 37 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules TABLE 27 IDD Specification for HYS72T[32000/64001/64020]HR–3.7–A Unit Note1) 860 mA 2) 1580 910 mA 2) 650 1130 960 mA 3) 370 570 400 mA 3) 560 950 780 mA 3) 650 1130 960 mA 3) 470 790 620 mA 3) 370 570 400 mA 3) 1140 2120 1180 mA 2) 1190 2210 1220 mA 2) 1140 2120 1180 mA 2) 380 610 440 mA 3)4) 35 70 70 mA 3)4) Product Type HYS72T32000HR–3.7–A HYS72T64001HR–3.7–A HYS72T64020HR–3.7–A Organization 256MB 512MB 512MB ×72 ×72 ×72 1 Rank 1 Rank 2 Ranks –3.7 –3.7 –3.7 Symbol Max. Max. Max. IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3N IDD3P(MRS= 0) IDD3P(MRS= 1) IDD4R IDD4W IDD5B IDD5D IDD6 IDD7 830 1490 870 2) 2930 1580 mA 1) Module IDD is calculated on the basis of component IDD and currents includes Registers and PLL. ODT disabled. IDD1, IDD4R and IDD7 are 1550 defined with the outputs disabled. 2) The other rank is in IDD2P Precharge Power-Down Standby Current mode 3) Both ranks are in the same IDD mode 4) Values for 0 °C ≤ TCASE ≤ 85 °C Rev. 1.21, 2007-03 09152006-J5FK-C565 38 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules TABLE 28 IDD Specification for HYS72T[32000/64001/64020]HR-5-A Unit Note1) 760 mA 2) 1400 810 mA 2) 530 910 780 mA 3) 310 480 350 mA 3) 460 770 640 mA 3) 550 950 820 mA 3) 390 640 510 mA 3) 310 480 350 mA 3) 910 1670 940 mA 2) 950 1760 990 mA 2) 1040 1940 1080 mA 2) 330 510 380 mA 3)4) 35 70 70 mA 3)4) Product Type HYS72T32000HR–5–A HYS72T64001HR–5–A HYS72T64020HR–5–A Organization 256MB 512MB 512MB ×72 ×72 ×72 1 Rank 1 Rank 2 Ranks –5 –5 –5 Symbol Max. Max. Max. IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3N IDD3P(MRS= 0) IDD3P(MRS= 1) IDD4R IDD4W IDD5B IDD5D IDD6 IDD7 730 1310 770 2) 2660 1440 mA 1) Module IDD is calculated on the basis of component IDD and currents includes Registers and PLL. ODT disabled. IDD1, IDD4R and IDD7 are 1400 defined with the outputs disabled. 2) The other rank is in IDD2P Precharge Power-Down Standby Current mode 3) Both ranks are in the same IDD mode 4) Values for 0 °C ≤ TCASE ≤ 85 °C Rev. 1.21, 2007-03 09152006-J5FK-C565 39 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules 4 SPD Codes This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands for serial presence detect. All values with XX in the table are module specific bytes which are defined during production. List of SPD Code Tables • • • • • Table 29 “SPD Codes for PC2–6400R–666” on Page 40 Table 30 “SPD Codes for PC2–5300R–444” on Page 45 Table 31 “SPD Codes for PC2–5300R–555” on Page 49 Table 32 “SPD Codes for PC2–4200R–444” on Page 53 Table 33 “SPD Codes for PC2–3200R–333” on Page 57 TABLE 29 Product Type HYS72T32000HR–2.5–A HYS72T64001HR–2.5–A HYS72T64020HR–2.5–A SPD Codes for PC2–6400R–666 Organization 256MB 512MB 512MB ×72 ×72 ×72 1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) Label Code PC2–6400R–666 PC2–6400R–666 PC2–6400R–666 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX 0 Programmed SPD Bytes in EEPROM 80 80 80 1 Total number of Bytes in EEPROM 08 08 08 2 Memory Type (DDR2) 08 08 08 3 Number of Row Addresses 0D 0D 0D 4 Number of Column Addresses 0A 0B 0A 5 DIMM Rank and Stacking Information 60 60 61 6 Data Width 48 48 48 7 Not used 00 00 00 8 Interface Voltage Level 05 05 05 9 25 25 25 10 tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns] 40 40 40 11 Error Correction Support (non-ECC, ECC) 02 02 02 Rev. 1.21, 2007-03 09152006-J5FK-C565 40 Internet Data Sheet Product Type HYS72T32000HR–2.5–A HYS72T64001HR–2.5–A HYS72T64020HR–2.5–A HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Organization 256MB 512MB 512MB ×72 ×72 ×72 1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) Label Code PC2–6400R–666 PC2–6400R–666 PC2–6400R–666 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX 12 Refresh Rate and Type 82 82 82 13 Primary SDRAM Width 08 04 08 14 Error Checking SDRAM Width 08 04 08 15 Not used 00 00 00 16 Burst Length Supported 0C 0C 0C 17 Number of Banks on SDRAM Device 04 04 04 18 Supported CAS Latencies 70 70 70 19 DIMM Mechanical Characteristics 01 01 01 20 DIMM Type Information 01 01 01 21 DIMM Attributes 04 05 05 22 Component Attributes 03 03 03 23 30 30 30 45 45 45 30 tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns] 2D 2D 2D 31 Module Density per Rank 40 80 40 32 tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns] 17 17 17 24 25 26 27 28 29 33 34 35 36 37 38 Rev. 1.21, 2007-03 09152006-J5FK-C565 41 3D 3D 3D 50 50 50 3C 3C 3C 1E 1E 1E 3C 3C 3C 25 25 25 05 05 05 12 12 12 3C 3C 3C 1E 1E 1E 1E 1E 1E Internet Data Sheet Product Type HYS72T32000HR–2.5–A HYS72T64001HR–2.5–A HYS72T64020HR–2.5–A HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Organization 256MB 512MB 512MB ×72 ×72 ×72 1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) Label Code PC2–6400R–666 PC2–6400R–666 PC2–6400R–666 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX 39 Analysis Characteristics 00 00 00 40 tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns] 00 00 00 41 42 43 44 45 3C 3C 3C 4B 4B 4B 80 80 80 14 14 14 1E 1E 1E 46 PLL Relock Time 0F 0F 0F 47 TCASE.MAX Delta / ∆T4R4W Delta 53 53 53 48 Psi(T-A) DRAM 82 82 82 49 ∆T0 (DT0) 5B 5B 5B 50 ∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM) 2B 2B 2B 51 ∆T2P (DT2P) 29 29 29 52 ∆T3N (DT3N) 29 29 29 53 ∆T3P.fast (DT3P fast) 36 36 36 54 ∆T3P.slow (DT3P slow) 19 19 19 55 ∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W) 4E 4E 4E 56 ∆T5B (DT5B) 17 17 17 57 ∆T7 (DT7) 26 26 26 58 Psi(ca) PLL C4 C4 C4 59 Psi(ca) REG 8C 8C 8C 60 ∆TPLL (DTPLL) 70 70 70 61 ∆TREG (DTREG) / Toggle Rate B0 B0 B0 62 SPD Revision 12 12 12 63 Checksum of Bytes 0-62 F7 31 F9 64 Manufacturer’s JEDEC ID Code (1) 7F 7F 7F 65 Manufacturer’s JEDEC ID Code (2) 7F 7F 7F Rev. 1.21, 2007-03 09152006-J5FK-C565 42 Internet Data Sheet Product Type HYS72T32000HR–2.5–A HYS72T64001HR–2.5–A HYS72T64020HR–2.5–A HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Organization 256MB 512MB 512MB ×72 ×72 ×72 1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) Label Code PC2–6400R–666 PC2–6400R–666 PC2–6400R–666 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX 66 Manufacturer’s JEDEC ID Code (3) 7F 7F 7F 67 Manufacturer’s JEDEC ID Code (4) 7F 7F 7F 68 Manufacturer’s JEDEC ID Code (5) 7F 7F 7F 69 Manufacturer’s JEDEC ID Code (6) 51 51 51 70 Manufacturer’s JEDEC ID Code (7) 00 00 00 71 Manufacturer’s JEDEC ID Code (8) 00 00 00 72 Module Manufacturer Location xx xx xx 73 Product Type, Char 1 37 37 37 74 Product Type, Char 2 32 32 32 75 Product Type, Char 3 54 54 54 76 Product Type, Char 4 33 36 36 77 Product Type, Char 5 32 34 34 78 Product Type, Char 6 30 30 30 79 Product Type, Char 7 30 30 32 80 Product Type, Char 8 30 31 30 81 Product Type, Char 9 48 48 48 82 Product Type, Char 10 52 52 52 83 Product Type, Char 11 32 32 32 84 Product Type, Char 12 2E 2E 2E 85 Product Type, Char 13 35 35 35 86 Product Type, Char 14 41 41 41 87 Product Type, Char 15 20 20 20 88 Product Type, Char 16 20 20 20 89 Product Type, Char 17 20 20 20 90 Product Type, Char 18 20 20 20 91 Module Revision Code 3x 3x 3x 92 Test Program Revision Code xx xx xx Rev. 1.21, 2007-03 09152006-J5FK-C565 43 Internet Data Sheet Product Type HYS72T32000HR–2.5–A HYS72T64001HR–2.5–A HYS72T64020HR–2.5–A HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Organization 256MB 512MB 512MB ×72 ×72 ×72 1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) Label Code PC2–6400R–666 PC2–6400R–666 PC2–6400R–666 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX 93 Module Manufacturing Date Year xx xx xx 94 Module Manufacturing Date Week xx xx xx 95 - 98 Module Serial Number 99 - 127 Not used 128 255 Blank for customer use Rev. 1.21, 2007-03 09152006-J5FK-C565 44 xx xx xx 00 00 00 FF FF FF Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules TABLE 30 Product Type HYS72T32000HR–3–A HYS72T64001HR–3–A HYS72T64020HR–3–A SPD Codes for PC2–5300R–444 Organization 256MB 512MB 512MB ×72 ×72 ×72 1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) Label Code PC2–5300R–444 PC2–5300R–444 PC2–5300R–444 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX 0 Programmed SPD Bytes in EEPROM 80 80 80 1 Total number of Bytes in EEPROM 08 08 08 2 Memory Type (DDR2) 08 08 08 3 Number of Row Addresses 0D 0D 0D 4 Number of Column Addresses 0A 0B 0A 5 DIMM Rank and Stacking Information 60 60 61 6 Data Width 48 48 48 7 Not used 00 00 00 8 Interface Voltage Level 05 05 05 9 tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns] 30 30 30 10 45 45 45 11 Error Correction Support (non-ECC, ECC) 02 02 02 12 Refresh Rate and Type 82 82 82 13 Primary SDRAM Width 08 04 08 14 Error Checking SDRAM Width 08 04 08 15 Not used 00 00 00 16 Burst Length Supported 0C 0C 0C 17 Number of Banks on SDRAM Device 04 04 04 18 Supported CAS Latencies 38 38 38 19 DIMM Mechanical Characteristics 01 01 01 20 DIMM Type Information 01 01 01 21 DIMM Attributes 04 05 05 22 Component Attributes 03 03 03 23 tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] 30 30 30 45 45 45 24 Rev. 1.21, 2007-03 09152006-J5FK-C565 45 Internet Data Sheet Product Type HYS72T32000HR–3–A HYS72T64001HR–3–A HYS72T64020HR–3–A HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Organization 256MB 512MB 512MB ×72 ×72 ×72 1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) Label Code PC2–5300R–444 PC2–5300R–444 PC2–5300R–444 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX 25 30 tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns] 2D 2D 2D 31 Module Density per Rank 40 80 40 32 20 20 20 38 tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns] 1E 1E 1E 39 Analysis Characteristics 00 00 00 40 tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns] 00 00 00 26 27 28 29 33 34 35 36 37 41 42 43 44 45 50 50 50 60 60 60 30 30 30 1E 1E 1E 30 30 30 27 27 27 10 10 10 17 17 17 3C 3C 3C 1E 1E 1E 39 39 39 4B 4B 4B 80 80 80 18 18 18 22 22 22 46 PLL Relock Time 0F 0F 0F 47 TCASE.MAX Delta / ∆T4R4W Delta 52 52 52 48 Psi(T-A) DRAM 82 82 82 49 ∆T0 (DT0) 47 47 47 50 ∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM) 25 25 25 51 ∆T2P (DT2P) 29 29 29 Rev. 1.21, 2007-03 09152006-J5FK-C565 46 Internet Data Sheet Product Type HYS72T32000HR–3–A HYS72T64001HR–3–A HYS72T64020HR–3–A HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Organization 256MB 512MB 512MB ×72 ×72 ×72 1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) Label Code PC2–5300R–444 PC2–5300R–444 PC2–5300R–444 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX 52 ∆T3N (DT3N) 25 25 25 53 ∆T3P.fast (DT3P fast) 2F 2F 2F 54 ∆T3P.slow (DT3P slow) 19 19 19 55 ∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W) 44 44 44 56 ∆T5B (DT5B) 17 17 17 57 ∆T7 (DT7) 24 24 24 58 Psi(ca) PLL C4 C4 C4 59 Psi(ca) REG 8C 8C 8C 60 ∆TPLL (DTPLL) 68 68 68 61 ∆TREG (DTREG) / Toggle Rate 94 94 94 62 SPD Revision 12 12 12 63 Checksum of Bytes 0-62 A4 DE A6 64 Manufacturer’s JEDEC ID Code (1) 7F 7F 7F 65 Manufacturer’s JEDEC ID Code (2) 7F 7F 7F 66 Manufacturer’s JEDEC ID Code (3) 7F 7F 7F 67 Manufacturer’s JEDEC ID Code (4) 7F 7F 7F 68 Manufacturer’s JEDEC ID Code (5) 7F 7F 7F 69 Manufacturer’s JEDEC ID Code (6) 51 51 51 70 Manufacturer’s JEDEC ID Code (7) 00 00 00 71 Manufacturer’s JEDEC ID Code (8) 00 00 00 72 Module Manufacturer Location xx xx xx 73 Product Type, Char 1 37 37 37 74 Product Type, Char 2 32 32 32 75 Product Type, Char 3 54 54 54 76 Product Type, Char 4 33 36 36 77 Product Type, Char 5 32 34 34 78 Product Type, Char 6 30 30 30 Rev. 1.21, 2007-03 09152006-J5FK-C565 47 Internet Data Sheet Product Type HYS72T32000HR–3–A HYS72T64001HR–3–A HYS72T64020HR–3–A HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Organization 256MB 512MB 512MB ×72 ×72 ×72 1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) Label Code PC2–5300R–444 PC2–5300R–444 PC2–5300R–444 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX 79 Product Type, Char 7 30 30 32 80 Product Type, Char 8 30 31 30 81 Product Type, Char 9 48 48 48 82 Product Type, Char 10 52 52 52 83 Product Type, Char 11 33 33 33 84 Product Type, Char 12 41 41 41 85 Product Type, Char 13 20 20 20 86 Product Type, Char 14 20 20 20 87 Product Type, Char 15 20 20 20 88 Product Type, Char 16 20 20 20 89 Product Type, Char 17 20 20 20 90 Product Type, Char 18 20 20 20 91 Module Revision Code 6x 6x 6x 92 Test Program Revision Code xx xx xx 93 Module Manufacturing Date Year xx xx xx 94 Module Manufacturing Date Week xx xx xx 95 - 98 Module Serial Number xx xx xx 99 - 127 Not used 00 00 00 128 255 FF FF FF Blank for customer use Rev. 1.21, 2007-03 09152006-J5FK-C565 48 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules TABLE 31 Product Type HYS72T32000HR–3S–A HYS72T64001HR–3S–A HYS72T64020HR–3S–A SPD Codes for PC2–5300R–555 Organization 256MB 512MB 512MB ×72 ×72 ×72 1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) Label Code PC2–5300R–555 PC2–5300R–555 PC2–5300R–555 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX 0 Programmed SPD Bytes in EEPROM 80 80 80 1 Total number of Bytes in EEPROM 08 08 08 2 Memory Type (DDR2) 08 08 08 3 Number of Row Addresses 0D 0D 0D 4 Number of Column Addresses 0A 0B 0A 5 DIMM Rank and Stacking Information 60 60 61 6 Data Width 48 48 48 7 Not used 00 00 00 8 Interface Voltage Level 05 05 05 9 30 30 30 10 tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns] 45 45 45 11 Error Correction Support (non-ECC, ECC) 02 02 02 12 Refresh Rate and Type 82 82 82 13 Primary SDRAM Width 08 04 08 14 Error Checking SDRAM Width 08 04 08 15 Not used 00 00 00 16 Burst Length Supported 0C 0C 0C 17 Number of Banks on SDRAM Device 04 04 04 18 Supported CAS Latencies 38 38 38 19 DIMM Mechanical Characteristics 01 01 01 20 DIMM Type Information 01 01 01 21 DIMM Attributes 04 05 05 22 Component Attributes 03 03 03 23 tCK @ CLMAX -1 (Byte 18) [ns] 3D 3D 3D Rev. 1.21, 2007-03 09152006-J5FK-C565 49 Internet Data Sheet Product Type HYS72T32000HR–3S–A HYS72T64001HR–3S–A HYS72T64020HR–3S–A HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Organization 256MB 512MB 512MB ×72 ×72 ×72 1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) Label Code PC2–5300R–555 PC2–5300R–555 PC2–5300R–555 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX 24 tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns] 50 50 50 50 50 50 60 60 60 3C 3C 3C 1E 1E 1E 3C 3C 3C 2D 2D 2D 31 Module Density per Rank 40 80 40 32 tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns] 20 20 20 25 26 27 28 29 30 33 34 35 36 37 38 27 27 27 10 10 10 17 17 17 3C 3C 3C 1E 1E 1E 1E 1E 1E 39 Analysis Characteristics 00 00 00 40 00 00 00 45 tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns] 46 41 3C 3C 3C 4B 4B 4B 80 80 80 18 18 18 22 22 22 PLL Relock Time 0F 0F 0F 47 TCASE.MAX Delta / ∆T4R4W Delta 52 52 52 48 Psi(T-A) DRAM 82 82 82 42 43 44 49 ∆T0 (DT0) 43 43 43 50 ∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM) 25 25 25 Rev. 1.21, 2007-03 09152006-J5FK-C565 50 Internet Data Sheet Product Type HYS72T32000HR–3S–A HYS72T64001HR–3S–A HYS72T64020HR–3S–A HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Organization 256MB 512MB 512MB ×72 ×72 ×72 1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) Label Code PC2–5300R–555 PC2–5300R–555 PC2–5300R–555 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX 51 ∆T2P (DT2P) 29 29 29 52 ∆T3N (DT3N) 25 25 25 53 ∆T3P.fast (DT3P fast) 2F 2F 2F 54 ∆T3P.slow (DT3P slow) 19 19 19 55 ∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W) 44 44 44 56 ∆T5B (DT5B) 17 17 17 57 ∆T7 (DT7) 22 22 22 58 Psi(ca) PLL C4 C4 C4 59 Psi(ca) REG 8C 8C 8C 60 ∆TPLL (DTPLL) 68 68 68 61 ∆TREG (DTREG) / Toggle Rate 94 94 94 62 SPD Revision 12 12 12 63 Checksum of Bytes 0-62 D1 0B D3 64 Manufacturer’s JEDEC ID Code (1) 7F 7F 7F 65 Manufacturer’s JEDEC ID Code (2) 7F 7F 7F 66 Manufacturer’s JEDEC ID Code (3) 7F 7F 7F 67 Manufacturer’s JEDEC ID Code (4) 7F 7F 7F 68 Manufacturer’s JEDEC ID Code (5) 7F 7F 7F 69 Manufacturer’s JEDEC ID Code (6) 51 51 51 70 Manufacturer’s JEDEC ID Code (7) 00 00 00 71 Manufacturer’s JEDEC ID Code (8) 00 00 00 72 Module Manufacturer Location xx xx xx 73 Product Type, Char 1 37 37 37 74 Product Type, Char 2 32 32 32 75 Product Type, Char 3 54 54 54 76 Product Type, Char 4 33 36 36 77 Product Type, Char 5 32 34 34 Rev. 1.21, 2007-03 09152006-J5FK-C565 51 Internet Data Sheet Product Type HYS72T32000HR–3S–A HYS72T64001HR–3S–A HYS72T64020HR–3S–A HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Organization 256MB 512MB 512MB ×72 ×72 ×72 1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) Label Code PC2–5300R–555 PC2–5300R–555 PC2–5300R–555 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX 78 Product Type, Char 6 30 30 30 79 Product Type, Char 7 30 30 32 80 Product Type, Char 8 30 31 30 81 Product Type, Char 9 48 48 48 82 Product Type, Char 10 52 52 52 83 Product Type, Char 11 33 33 33 84 Product Type, Char 12 53 53 53 85 Product Type, Char 13 41 41 41 86 Product Type, Char 14 20 20 20 87 Product Type, Char 15 20 20 20 88 Product Type, Char 16 20 20 20 89 Product Type, Char 17 20 20 20 90 Product Type, Char 18 20 20 20 91 Module Revision Code 3x 3x 3x 92 Test Program Revision Code xx xx xx 93 Module Manufacturing Date Year xx xx xx 94 Module Manufacturing Date Week xx xx xx 95 - 98 Module Serial Number xx xx xx 99 - 127 Not used 00 00 00 128 255 FF FF FF Blank for customer use Rev. 1.21, 2007-03 09152006-J5FK-C565 52 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules TABLE 32 Product Type HYS72T32000HR–3.7–A HYS72T64001HR–3.7–A HYS72T64020HR–3.7–A SPD Codes for PC2–4200R–444 Organization 256MB 512MB 512MB ×72 ×72 ×72 1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) Label Code PC2–4200R–444 PC2–4200R–444 PC2–4200R–444 JEDEC SPD Revision Rev. 1.1 Rev. 1.1 Rev. 1.1 Byte# Description HEX HEX HEX 0 Programmed SPD Bytes in EEPROM 80 80 80 1 Total number of Bytes in EEPROM 08 08 08 2 Memory Type (DDR2) 08 08 08 3 Number of Row Addresses 0D 0D 0D 4 Number of Column Addresses 0A 0B 0A 5 DIMM Rank and Stacking Information 60 60 61 6 Data Width 48 48 48 7 Not used 00 00 00 8 Interface Voltage Level 05 05 05 9 tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns] 3D 3D 3D 50 50 50 11 Error Correction Support (non-ECC, ECC) 02 02 02 12 Refresh Rate and Type 82 82 82 13 Primary SDRAM Width 08 04 08 10 14 Error Checking SDRAM Width 08 04 08 15 Not used 00 00 00 16 Burst Length Supported 0C 0C 0C 17 Number of Banks on SDRAM Device 04 04 04 18 Supported CAS Latencies 38 38 38 19 DIMM Mechanical Characteristics 00 00 00 20 DIMM Type Information 01 01 01 21 DIMM Attributes 04 05 05 22 Component Attributes 01 01 01 23 tCK @ CLMAX -1 (Byte 18) [ns] 3D 3D 3D Rev. 1.21, 2007-03 09152006-J5FK-C565 53 Internet Data Sheet Product Type HYS72T32000HR–3.7–A HYS72T64001HR–3.7–A HYS72T64020HR–3.7–A HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Organization 256MB 512MB 512MB ×72 ×72 ×72 1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) Label Code PC2–4200R–444 PC2–4200R–444 PC2–4200R–444 JEDEC SPD Revision Rev. 1.1 Rev. 1.1 Rev. 1.1 Byte# Description HEX HEX HEX 24 tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns] 50 50 50 50 50 50 60 60 60 3C 3C 3C 1E 1E 1E 3C 3C 3C 2D 2D 2D 31 Module Density per Rank 40 80 40 32 tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns] 25 25 25 37 37 37 10 10 10 22 22 22 3C 3C 3C 1E 1E 1E 1E 1E 1E 25 26 27 28 29 30 33 34 35 36 37 38 39 Analysis Characteristics 00 00 00 40 00 00 00 3C 3C 3C 45 tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns] 28 28 28 46 PLL Relock Time 0F 0F 0F 47 TCASE.MAX Delta / ∆T4R4W Delta 55 55 55 48 Psi(T-A) DRAM 82 82 82 49 ∆T0 (DT0) 37 37 37 50 ∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM) 1F 1F 1F 41 42 43 44 Rev. 1.21, 2007-03 09152006-J5FK-C565 54 4B 4B 4B 80 80 80 1E 1E 1E Internet Data Sheet Product Type HYS72T32000HR–3.7–A HYS72T64001HR–3.7–A HYS72T64020HR–3.7–A HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Organization 256MB 512MB 512MB ×72 ×72 ×72 1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) Label Code PC2–4200R–444 PC2–4200R–444 PC2–4200R–444 JEDEC SPD Revision Rev. 1.1 Rev. 1.1 Rev. 1.1 Byte# Description HEX HEX HEX 51 ∆T2P (DT2P) 21 21 21 52 ∆T3N (DT3N) 1D 1D 1D 53 ∆T3P.fast (DT3P fast) 28 28 28 54 ∆T3P.slow (DT3P slow) 14 14 14 55 ∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W) 2C 2C 2C 56 ∆T5B (DT5B) 15 15 15 57 ∆T7 (DT7) 21 21 21 58 Psi(ca) PLL C4 C4 C4 59 Psi(ca) REG 8C 8C 8C 60 ∆TPLL (DTPLL) 61 61 61 61 ∆TREG (DTREG) / Toggle Rate 78 78 78 62 SPD Revision 11 11 11 63 Checksum of Bytes 0-62 A8 E2 AA 64 Manufacturer’s JEDEC ID Code (1) 7F 7F 7F 65 Manufacturer’s JEDEC ID Code (2) 7F 7F 7F 66 Manufacturer’s JEDEC ID Code (3) 7F 7F 7F 67 Manufacturer’s JEDEC ID Code (4) 7F 7F 7F 68 Manufacturer’s JEDEC ID Code (5) 7F 7F 7F 69 Manufacturer’s JEDEC ID Code (6) 51 51 51 70 Manufacturer’s JEDEC ID Code (7) 00 00 00 71 Manufacturer’s JEDEC ID Code (8) 00 00 00 72 Module Manufacturer Location xx xx xx 73 Product Type, Char 1 37 37 37 74 Product Type, Char 2 32 32 32 75 Product Type, Char 3 54 54 54 76 Product Type, Char 4 33 36 36 77 Product Type, Char 5 32 34 34 Rev. 1.21, 2007-03 09152006-J5FK-C565 55 Internet Data Sheet Product Type HYS72T32000HR–3.7–A HYS72T64001HR–3.7–A HYS72T64020HR–3.7–A HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Organization 256MB 512MB 512MB ×72 ×72 ×72 1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) Label Code PC2–4200R–444 PC2–4200R–444 PC2–4200R–444 JEDEC SPD Revision Rev. 1.1 Rev. 1.1 Rev. 1.1 Byte# Description HEX HEX HEX 78 Product Type, Char 6 30 30 30 79 Product Type, Char 7 30 30 32 80 Product Type, Char 8 30 31 30 81 Product Type, Char 9 48 48 48 82 Product Type, Char 10 52 52 52 83 Product Type, Char 11 33 33 33 84 Product Type, Char 12 2E 2E 2E 85 Product Type, Char 13 37 37 37 86 Product Type, Char 14 41 41 41 87 Product Type, Char 15 20 20 20 88 Product Type, Char 16 20 20 20 89 Product Type, Char 17 20 20 20 90 Product Type, Char 18 20 20 20 91 Module Revision Code 4x 4x 4x 92 Test Program Revision Code xx xx xx 93 Module Manufacturing Date Year xx xx xx 94 Module Manufacturing Date Week xx xx xx 95 - 98 Module Serial Number xx xx xx 99 - 127 Not used 00 00 00 128 255 FF FF FF Blank for customer use Rev. 1.21, 2007-03 09152006-J5FK-C565 56 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules TABLE 33 Product Type HYS72T32000HR–5–A HYS72T64001HR–5–A HYS72T64020HR–5–A SPD Codes for PC2–3200R–333 Organization 256MB 512MB 512MB ×72 ×72 ×72 1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) Label Code PC2–3200R–333 PC2–3200R–333 PC2–3200R–333 JEDEC SPD Revision Rev. 1.1 Rev. 1.1 Rev. 1.1 Byte# Description HEX HEX HEX 0 Programmed SPD Bytes in EEPROM 80 80 80 1 Total number of Bytes in EEPROM 08 08 08 2 Memory Type (DDR2) 08 08 08 3 Number of Row Addresses 0D 0D 0D 4 Number of Column Addresses 0A 0B 0A 5 DIMM Rank and Stacking Information 60 60 61 6 Data Width 48 48 48 7 Not used 00 00 00 8 Interface Voltage Level 05 05 05 9 tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns] 50 50 50 10 60 60 60 11 Error Correction Support (non-ECC, ECC) 02 02 02 12 Refresh Rate and Type 82 82 82 13 Primary SDRAM Width 08 04 08 14 Error Checking SDRAM Width 08 04 08 15 Not used 00 00 00 16 Burst Length Supported 0C 0C 0C 17 Number of Banks on SDRAM Device 04 04 04 18 Supported CAS Latencies 38 38 38 19 DIMM Mechanical Characteristics 00 00 00 20 DIMM Type Information 01 01 01 21 DIMM Attributes 04 05 05 22 Component Attributes 01 01 01 23 tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] 50 50 50 60 60 60 24 Rev. 1.21, 2007-03 09152006-J5FK-C565 57 Internet Data Sheet Product Type HYS72T32000HR–5–A HYS72T64001HR–5–A HYS72T64020HR–5–A HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Organization 256MB 512MB 512MB ×72 ×72 ×72 1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) Label Code PC2–3200R–333 PC2–3200R–333 PC2–3200R–333 JEDEC SPD Revision Rev. 1.1 Rev. 1.1 Rev. 1.1 Byte# Description HEX HEX HEX 25 30 tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns] 28 28 28 31 Module Density per Rank 40 80 40 32 35 35 35 38 tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns] 1E 1E 1E 39 Analysis Characteristics 00 00 00 40 tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns] 00 00 00 26 27 28 29 33 34 35 36 37 41 42 43 44 45 50 50 50 60 60 60 3C 3C 3C 1E 1E 1E 3C 3C 3C 47 47 47 15 15 15 27 27 27 3C 3C 3C 28 28 28 37 37 37 4B 4B 4B 80 80 80 23 23 23 2D 2D 2D 46 PLL Relock Time 0F 0F 0F 47 TCASE.MAX Delta / ∆T4R4W Delta 53 53 53 48 Psi(T-A) DRAM 82 82 82 49 ∆T0 (DT0) 2F 2F 2F 50 ∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM) 19 19 19 51 ∆T2P (DT2P) 21 21 21 Rev. 1.21, 2007-03 09152006-J5FK-C565 58 Internet Data Sheet Product Type HYS72T32000HR–5–A HYS72T64001HR–5–A HYS72T64020HR–5–A HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Organization 256MB 512MB 512MB ×72 ×72 ×72 1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) Label Code PC2–3200R–333 PC2–3200R–333 PC2–3200R–333 JEDEC SPD Revision Rev. 1.1 Rev. 1.1 Rev. 1.1 Byte# Description HEX HEX HEX 52 ∆T3N (DT3N) 19 19 19 53 ∆T3P.fast (DT3P fast) 20 20 20 54 ∆T3P.slow (DT3P slow) 14 14 14 55 ∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W) 26 26 26 56 ∆T5B (DT5B) 14 14 14 57 ∆T7 (DT7) 1F 1F 1F 58 Psi(ca) PLL C4 C4 C4 59 Psi(ca) REG 8C 8C 8C 60 ∆TPLL (DTPLL) 59 59 59 61 ∆TREG (DTREG) / Toggle Rate 5C 5C 5C 62 SPD Revision 11 11 11 63 Checksum of Bytes 0-62 D9 13 DB 64 Manufacturer’s JEDEC ID Code (1) 7F 7F 7F 65 Manufacturer’s JEDEC ID Code (2) 7F 7F 7F 66 Manufacturer’s JEDEC ID Code (3) 7F 7F 7F 67 Manufacturer’s JEDEC ID Code (4) 7F 7F 7F 68 Manufacturer’s JEDEC ID Code (5) 7F 7F 7F 69 Manufacturer’s JEDEC ID Code (6) 51 51 51 70 Manufacturer’s JEDEC ID Code (7) 00 00 00 71 Manufacturer’s JEDEC ID Code (8) 00 00 00 72 Module Manufacturer Location xx xx xx 73 Product Type, Char 1 37 37 37 74 Product Type, Char 2 32 32 32 75 Product Type, Char 3 54 54 54 76 Product Type, Char 4 33 36 36 77 Product Type, Char 5 32 34 34 78 Product Type, Char 6 30 30 30 Rev. 1.21, 2007-03 09152006-J5FK-C565 59 Internet Data Sheet Product Type HYS72T32000HR–5–A HYS72T64001HR–5–A HYS72T64020HR–5–A HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Organization 256MB 512MB 512MB ×72 ×72 ×72 1 Rank (×8) 1 Rank (×4) 2 Ranks (×8) Label Code PC2–3200R–333 PC2–3200R–333 PC2–3200R–333 JEDEC SPD Revision Rev. 1.1 Rev. 1.1 Rev. 1.1 Byte# Description HEX HEX HEX 79 Product Type, Char 7 30 30 32 80 Product Type, Char 8 30 31 30 81 Product Type, Char 9 48 48 48 82 Product Type, Char 10 52 52 52 83 Product Type, Char 11 35 35 35 84 Product Type, Char 12 41 41 41 85 Product Type, Char 13 20 20 20 86 Product Type, Char 14 20 20 20 87 Product Type, Char 15 20 20 20 88 Product Type, Char 16 20 20 20 89 Product Type, Char 17 20 20 20 90 Product Type, Char 18 20 20 20 91 Module Revision Code 4x 4x 4x 92 Test Program Revision Code xx xx xx 93 Module Manufacturing Date Year xx xx xx 94 Module Manufacturing Date Week xx xx xx 95 - 98 Module Serial Number xx xx xx 99 - 127 Not used 00 00 00 128 255 FF FF FF Blank for customer use Rev. 1.21, 2007-03 09152006-J5FK-C565 60 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules 5 Package Outlines This chapter contains the package outlines of the products. FIGURE 5 Package Outline Raw Card A L-DIM-240-11 $ % & 0$ ; [ & $ % 'HWD LOR IF RQWD FWV $ % & %XUUPD [ DOORZ H G Rev. 1.21, 2007-03 09152006-J5FK-C565 */' 61 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules FIGURE 6 Package Outline Raw Card B-G L-DIM-240-12 $ % & 0$ ; [ & $ % 'HWD LORIFR QWD FWV $ % & %XUUPD [ DOORZ H G Rev. 1.21, 2007-03 09152006-J5FK-C565 */' 62 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules FIGURE 7 Package Outline Raw Card C L-DIM-240-13 $ % & 0 $; [ & $ % 'HWDLOR IF RQWD FWV $ % & %XUUP D[ D OORZH G Rev. 1.21, 2007-03 09152006-J5FK-C565 */' 63 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules 6 Product Type Nomenclature field number. The detailed field description together with possible values and coding explanation is listed for modules in Table 35 and for components in Table 36. Qimonda’s nomenclature uses simple coding combined with some propriatory coding. Table 34 provides examples for module and component product type number as well as the TABLE 34 Nomenclature Fields and Examples Example for Field Number 1 2 3 4 5 6 7 8 9 10 11 Micro-DIMM HYS 64 T 64 0 2 0 K M –5 –A DDR2 DRAM HYB 18 T 512 16 0 A C –5 — TABLE 35 DDR2 DIMM Nomenclature Field Description Values Coding 1 QIMONDA Modul Prefix HYS Constant 2 Module Data Width [bit] 64 Non-ECC 72 ECC 3 DRAM Technology T DDR2 4 Memory Density per I/O [Mbit]; Module Density1) 32 256 MByte 64 512 MByte 128 1 GByte 256 2 GByte 512 4 GByte 5 Raw Card Generation 0 .. 9 Look up table 6 Number of Module Ranks 0, 2, 4 1, 2, 4 7 Product Variations 0 .. 9 Look up table 8 Package, Lead-Free Status A .. Z Look up table 9 Module Type D SO-DIMM M Micro-DIMM R Registered U Unbuffered F Fully Buffered Rev. 1.21, 2007-03 09152006-J5FK-C565 64 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Field Description Values Coding 10 Speed Grade –2.5 PC2–6400 6–6–6 –3 PC2–5300 4–4–4 –3S PC2–5300 5–5–5 –3.7 PC2–4200 4–4–4 11 Die Revision –5 PC2–3200 3–3–3 –A First –B Second 1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes as listed in column “Coding”. TABLE 36 DDR2 DRAM Nomenclature Field Description Values Coding 1 QIMONDA Component Prefix HYB Constant 2 Interface Voltage [V] 18 SSTL_18 3 DRAM Technology T DDR2 4 Component Density [Mbit] 256 256 Mbit 512 512 Mbit 1G 1 Gbit 5+6 Number of I/Os 2G 2 Gbit 40 ×4 80 ×8 16 ×16 7 Product Variations 0 .. 9 Look up table 8 Die Revision A First B Second C FBGA, lead-containing F FBGA, lead-free –2.5 DDR2-800 6-6-6 –3 DDR2-667 4-4-4 –3S DDR2-667 5-5-5 –3.7 DDR2-533 4-4-4 –5 DDR2-400 3-3-3 9 10 Package, Lead-Free Status Speed Grade Rev. 1.21, 2007-03 09152006-J5FK-C565 65 Internet Data Sheet HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules Table of Contents 1 1.1 1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Speed Grades Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 16 17 17 19 32 33 4 SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6 Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Rev. 1.21, 2007-03 09152006-J5FK-C565 66 Internet Data Sheet Edition 2007-03 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 München, Germany © Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com