DAC8806 DA C 880 6 SBAS385A – APRIL 2006 – REVISED JUNE 2006 14-Bit, Parallel Input Multiplying Digital-to-Analog Converter FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • ±0.5LSB DNL ±1LSB INL 14-Bit Monotonic Low Noise: 10nV/√Hz Low Power: IDD = 2µA Analog Power Supply: +2.7V to +5.5V 1.66mA Full-Scale Current, with VREF = 10V Settling Time: 0.5µs 4-Quadrant Multiplying Reference Reference Bandwidth: 8MHz Reference Input: ±15V Reference Dynamics: –105THD SSOP-28 Package Industry-Standard Pin Configuration Automatic Test Equipment Instrumentation Digitally Controlled Calibration Industrial Control PLCs DESCRIPTION The DAC8806, a multiplying digital-to-analog converter (DAC), is designed to operate from a single 2.7V to 5.5V supply. The applied external reference input voltage VREF determines the full-scale output current. An internal feedback resistor (RFB) provides temperature tracking for the full-scale output when combined with an external, current-to-voltage (I/V) precision amplifier. A parallel interface offers high-speed communications. The DAC8806 is packaged in a space-saving SSOP-28 package and has an industry-standard pinout. VDD R1 RCOM R1 DAC8806 REF R2 ROFS RFB ROFS RFB D0 ¼ D13 DAC Parallel Bus Input Register AGND WR RST LDAC IOUT DAC Register Control Logic DGND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated DAC8806 www.ti.com SBAS385A – APRIL 2006 – REVISED JUNE 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT MINIMUM RELATIVE ACCURACY (LSB) DIFFERENTIAL NONLINEARITY (LSB) PACKAGELEAD (DESIGNATOR) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING DAC8806I ±1 ±1 DB-28 (SSOP) –40°C to +85°C DAC8806 (1) ORDERING NUMBER TRANSPORT MEDIA, QUANTITY DAC8806IDB Tubes, 48 DAC8806IDBR Tape and Reel, 2000 For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VDD to GND DAC8806 UNIT –0.3 to +7 V Digital input voltage to GND –0.3 to +VDD + 0.3 V V (IOUT) to GND –0.3 to +VDD + 0.3 V –40 to +85 °C Operating temperature range REF, ROFS, RFB, R1, RCOM to AGND, and DGND Storage temperature range Junction temperature range (TJ max) Power dissipation ±25 V –65 to +150 °C +125 °C (TJ max – TA)/RθJA W 55 °C/W Human body model (HBM) 4000 V Charged device model (CDM) 1000 V Thermal impedance, RθJA ESD rating: (1) 2 Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. Submit Documentation Feedback DAC8806 www.ti.com SBAS385A – APRIL 2006 – REVISED JUNE 2006 ELECTRICAL CHARACTERISTICS All specifications at –40°C to +85°C, VDD = +2.7V to +5.5V, IOUT = virtual GND, GND = 0V, VREF = 10V, and TA = full operating temperature, unless otherwise noted. DAC8806 PARAMETER CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution 14 Relative accuracy Bits DAC8806 ±0.5 Differential nonlinearity ±1 LSB ±1 LSB 5 nA Output leakage current Data = 0000h, TA = +25°C Output leakage current Data = 0000h, TA = TMAX 10 nA Full-scale gain error Unipolar, data = 3FFFh 1 ±4 LSB Bipolar, data = 3FFFh 1 ±4 LSB ppm/°C Full-scale temperature coefficient 1 2 Bipolar zero scale error ±1 ±3 LSB ±0.1 ±1 LSB/V Power-supply rejection ratio; VDD = 5V ±10% PSRR OUTPUT CHARACTERISTICS (1) Output current Output capacitance Code dependent 1.66 mA 50 pF REFERENCE INPUT VREF range –15 RREF Input resistance (unipolar) 4.5 Input capacitance 6 15 V 7.5 kΩ 5 pF R1/R2 R1/R2 resistance (bipolar) 9 12 15 kΩ ROFS, RFB Feedback and offset resistance 9 12 15 kΩ 0.6 V 0.8 V LOGIC INPUTS AND OUTPUT (1) Input low voltage VIL VDD = +2.7V Input high voltage VIH VDD = +2.7V 2.1 V VIH VDD = +5V 2.4 V VIL VDD = +5V Input leakage current Input capacitance IIL 0.001 CIL 1 µA 8 pF INTERFACE TIMING, VDD = +5.0V (1) (See Figure 40 and Table 1) tDS Data to WR setup time 20 ns tDH Data to WR hold time 0 ns tWR WR pulse width 20 ns tLDAC LDAC pulse width 20 ns Data setup time tRST RST pulse width 20 ns Data hold time tLWD WR to LDAC delay time 0 ns INTERFACE TIMING, VDD = +5.0V (1) (See Figure 40 and Table 1) tDS Data to WR setup time 35 ns tDH Data to WR hold time 0 ns tWR WR pulse width 35 ns tLDAC LDAC pulse width 35 ns Data setup time tRST RST pulse width 35 ns Data hold time tLWD WR to LDAC delay time 0 ns (1) Specified by design and characterization; not production tested. Submit Documentation Feedback 3 DAC8806 www.ti.com SBAS385A – APRIL 2006 – REVISED JUNE 2006 ELECTRICAL CHARACTERISTICS (continued) All specifications at –40°C to +85°C, VDD = +2.7V to +5.5V, IOUT = virtual GND, GND = 0V, VREF = 10V, and TA = full operating temperature, unless otherwise noted. DAC8806 PARAMETER CONDITIONS MIN TYP MAX UNITS POWER REQUIREMENTS VDD 2.7 IDD (normal operation) Logic inputs = 0V VDD = +4.5V to +5.5V VIH = VDD and VIL = GND VDD = +2.7V to +3.6V VIH = VDD and VIL = GND 5.5 V 5 µA 3 5 µA 1 2.5 µA AC CHARACTERISTICS (2) Output current settling time µs Reference multiplying BW VREF = 5VPP, Data = 3FFFh 8 MHz DAC glitch impulse VREF = 0V to 10V, Data = 1FFFh to 2000h to 1FFFh 2 nV–s Feedthrough error VOUT/VREF Data = 0000h, VREF = 10kHz; ±10VPP –70 dB Digital feedthrough LDAC = logic low, VREF = –10V to +10V Any code change 2 nV–s Total harmonic distortion VREF = 6VRMS, Data = 3FFF, f = 1kHz –105 dB 10 nV/√Hz Output spot noise voltage (2) Specified by design and characterization; not production tested. TERMINAL FUNCTIONS PIN ASSIGNMENTS PIN # NAME REF DESCRIPTION Reference input and 4-quadrant Resistor (R2). RCOM Center tap of two 4-quadrant resistors (R1 and R2). REF 1 28 RST 1 RCOM 2 27 NC 2 R1 3 26 NC 3 R1 4 ROFS Bipolar offset resistor 5 RFB Internal matching feedback resistor DAC current output 4-quadrant resistor (R1). ROFS 4 25 D0 RFB 5 24 D1 6 IOUT AGND Analog ground IOUT 6 23 VDD 7 AGND 7 22 DGND 8 LDAC LDAC 8 21 D2 Digital input load DAC control. When LDAC is high, data is loaded from input register into a DAC register, updating the DAC output. WR 9 20 D3 9 WR Write control digital input. Active low. When WR is taken to logic low, data is loaded from the digital input pins (D0–D13) into a14-bit input register. D13 10 19 D4 10–21 D13–D2 D12 11 18 D5 22 DGND D6 23 VDD 24, 25 D1, D0 26, 27 NC No connection 28 RST Reset. Active low. When RST is taken to logic low, the DAC output and all internal registers are set to zero code for the DAC8806. DAC8806 D11 4 0.5 12 17 D10 13 16 D7 D9 14 15 D8 Submit Documentation Feedback Digital input data bits. D13 is MSB. Digital ground Positive power supply Digital Input data bits. D0 is LSB. DAC8806 www.ti.com SBAS385A – APRIL 2006 – REVISED JUNE 2006 TYPICAL CHARACTERISTICS: VDD = +5V At TA = +25°C, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 1.0 TA = +25°C VREF = 10V 0.8 0.6 0.6 0.4 0.4 0.2 0 -0.2 0 -0.2 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 0 1.0 2048 4096 6144 8192 10240 12288 14336 16383 Code 0 2048 4096 6144 8192 10240 12288 14336 16383 Code Figure 1. Figure 2. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 TA = -40° C VREF =10V 0.8 TA = -40° C VREF = 10V 0.8 0.6 0.6 0.4 0.4 DNL (LSB) INL (LSB) 0.2 -0.4 -1.0 0.2 0 -0.2 0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 1.0 2048 4096 6144 8192 10240 12288 14336 16383 Code 0 2048 4096 6144 8192 10240 12288 14336 16383 Code Figure 3. Figure 4. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 TA = +85°C VREF = 10V 0.8 TA = +85°C VREF = 10V 0.8 0.6 0.6 0.4 0.4 DNL (LSB) INL (LSB) TA = +25°C VREF = 10V 0.8 DNL (LSB) INL (LSB) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 0.2 0 -0.2 0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Code 0 Figure 5. 2048 4096 6144 8192 10240 12288 14336 16383 Code Figure 6. Submit Documentation Feedback 5 DAC8806 www.ti.com SBAS385A – APRIL 2006 – REVISED JUNE 2006 TYPICAL CHARACTERISTICS: VDD = +5V (continued) At TA = +25°C, unless otherwise noted. REFERENCE MULTIPLYING BANDWIDTH UNIPOLAR MODE 6 0 -6 -12 -18 -24 -30 -36 -42 -48 -54 -60 -66 -72 -78 -84 -90 -96 -102 -108 -114 180 VDD = +5.0V 140 0x3FFF 0x2000 0x1000 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040 0x0020 0x0010 0x0008 0x0004 0x0002 0x0001 Attenuation (dB) Supply Current, IDD (mA) 160 120 100 80 60 40 VDD = +2.7V 20 0 0x0000 10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Digital Code SUPPLY CURRENT vs LOGIC INPUT VOLTAGE 100 1k 10k 5.0 100k 1M 10M 100M Bandwidth (Hz) Logic Input Voltage (V) Figure 8. REFERENCE MULTIPLYING BANDWIDTH BIPOLAR MODE REFERENCE MULTIPLYING BANDWIDTH BIPOLAR MODE Codes from Full-scale to Midscale 10 100 1k 10k 100k 1M 10M 0x3FFF 0x3000 0x2800 0x2400 0x2200 0x2100 0x2080 0x2040 0x2020 0x2010 0x2008 0x2004 0x2002 0x2001 0x2000 100M 6 0 -6 -12 -18 -24 -30 -36 -42 -48 -54 -60 -66 -72 -78 -84 -90 -96 -102 -108 -114 Attenuation (dB) Attenuation (dB) 6 0 -6 -12 -18 -24 -30 -36 -42 -48 -54 -60 -66 -72 -78 -84 -90 -96 -102 -108 -114 Digital Code Figure 7. Codes from Midscale to Zero Scale 10 Bandwidth (Hz) 0x0000 0x1000 0x1800 0x1400 0x1200 0x1100 0x1080 0x1040 0x1020 0x1010 0x1008 0x1004 0x1002 0x1001 0x2000 100 1k 10k 100k 1M 10M 100M Bandwidth (Hz) Figure 9. Figure 10. MIDSCALE DAC GLITCH MIDSCALE DAC GLITCH VREF = 10V Code: 1FFFh to 2000h LDAC Pulse Output Voltage (20mV) Output Voltage (20mV) VREF = 10V LDAC Pulse Time (0.5ms) Time (0.5ms) Figure 11. 6 Code: 2000h to 1FFFh Figure 12. Submit Documentation Feedback DAC8806 www.ti.com SBAS385A – APRIL 2006 – REVISED JUNE 2006 TYPICAL CHARACTERISTICS: VDD = +5V (continued) At TA = +25°C, unless otherwise noted. FULL-SCALE ERROR vs TEMPERATURE 4.8 3.8 BIPOLAR-ZERO ERROR vs TEMPERATURE 1.5 VREF = 10V Bipolar-Zero Error (mV) 2.8 Full-Scale Error (mV) VREF = 10V 1.0 1.8 0.8 0 -0.8 -1.8 -2.8 0.5 0 -0.5 -1.0 -3.8 -1.5 -4.8 -60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 Temperature (°C) Temperature (°C) Figure 13. Figure 14. Submit Documentation Feedback 60 80 100 7 DAC8806 www.ti.com SBAS385A – APRIL 2006 – REVISED JUNE 2006 TYPICAL CHARACTERISTICS: VDD = +2.7V At TA = +25°C, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 1.0 TA = +25°C VREF = 10V 0.8 0.6 0.6 0.4 0.4 0.2 0 -0.2 0 -0.2 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 0 1.0 2048 4096 6144 8192 10240 12288 14336 16383 Code 0 2048 6144 8192 10240 12288 14336 16383 Code Figure 16. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 TA = -40°C VREF = 10V 0.8 0.6 0.4 0.4 DNL (LSB) 0.6 0.2 0 -0.2 0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 1.0 2048 4096 6144 8192 10240 12288 14336 16383 Code 0 2048 4096 6144 8192 10240 12288 14336 16383 Code Figure 17. Figure 18. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 TA = +85°C VREF = 10V 0.8 TA = +85°C VREF = 10V 0.8 0.6 0.4 0.4 INL (LSB) 0.6 0.2 0 -0.2 0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 2048 4096 6144 8192 10240 12288 14336 16383 Code 0 Figure 19. 8 4096 Figure 15. TA = -40°C VREF = 10V 0.8 INL (LSB) 0.2 -0.4 -1.0 DNL (LSB) TA = +25°C 0.8 DNL (LSB) INL (LSB) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 2048 4096 6144 8192 10240 12288 14336 16383 Code Figure 20. Submit Documentation Feedback DAC8806 www.ti.com SBAS385A – APRIL 2006 – REVISED JUNE 2006 TYPICAL CHARACTERISTICS: VDD = +2.7V (continued) At TA = +25°C, unless otherwise noted. DAC GLITCH DAC GLITCH Output Voltage (20mV) VREF = 10V Output Voltage (20mV) VREF = 10V Code: 2000h to 1FFFh LDAC Pulse Code: 1FFFh to 2000h LDAC Pulse Time (0.5ms) Time (0.5ms) Figure 21. Figure 22. FULL-SCALE ERROR vs TEMPERATURE 4.8 3.8 BIPOLAR-ZERO ERROR vs TEMPERATURE 1.5 VREF = 10V 1.0 Bipolar-Zero Error (mV) 2.8 Full-Scale Error (mV) VREF = 10V 1.8 0.8 0 -0.8 -1.8 -2.8 0.5 0 -0.5 -1.0 -3.8 -4.8 -60 -40 -20 0 20 40 60 80 100 -1.5 -60 -40 -20 0 20 40 Temperature (°C) Temperature (°C) Figure 23. Figure 24. Submit Documentation Feedback 60 80 100 9 DAC8806 www.ti.com SBAS385A – APRIL 2006 – REVISED JUNE 2006 TYPICAL CHARACTERISTICS At TA = +25°C, unless otherwise noted. IDD vs TEMPERATURE DAC SETTLING TIME 5.0 4.5 Output Voltage (5V/div) 4.0 IDD (m A) 3.5 3.0 5.0V 2.5 2.0 1.5 Unipolar Mode Voltage Output Settling 1.0 Trigger Pulse 2.7V 0.5 0 - 40 - 20 0 20 40 60 80 Time (0.5ms/div) 100 Temperature (°C) 1.0 Figure 26. INTEGRAL NONLINEARITY vs VREF UNIPOLAR MODE INTEGRAL NONLINEARITY vs VREF BIPOLAR MODE 0.6 0.4 0.4 INL (LSB) 0.6 0.2 0 -0.2 -0.4 -0.6 -0.8 -0.8 1.0 0 5 -1.0 10 -10 0 5 VREF (V) Figure 27. Figure 28. DIFFERENTIAL NONLINEARITY vs VREF UNIPOLAR MODE DIFFERENTIAL NONLINEARITY vs VREF BIPOLAR MODE 1.0 0.6 0.4 0.4 DNL (LSB) 0.6 0.2 0 -0.2 0 -0.2 -0.4 -0.6 -0.6 -0.8 -0.8 -5 0 5 10 VDD = 2.7V 0.2 -0.4 -1.0 10 VDD = 5V 0.8 VDD = 2.7V -10 -5 VREF (V) VDD = 5V 0.8 DNL (LSB) 0 -0.2 -0.6 -5 VDD = 2.7V 0.2 -0.4 -10 VDD = 5V 0.8 VDD = 2.7V -1.0 10 1.0 VDD = 5V 0.8 INL (LSB) Figure 25. -1.0 -10 -5 0 VREF (V) VREF (V) Figure 29. Figure 30. Submit Documentation Feedback 5 10 DAC8806 www.ti.com SBAS385A – APRIL 2006 – REVISED JUNE 2006 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. INTEGRAL NONLINEARITY vs VDD UNIPOLAR MODE 1.0 0.4 INL (LSB) 0.4 0.2 0 -0.2 0 -0.2 -0.4 -0.6 -0.6 -0.8 -0.8 1.0 2.3 2.8 3.3 3.8 4.3 4.8 -1.0 5.3 5.5 4.3 4.8 DIFFERENTIAL NONLINEARITY vs VDD BIPOLAR MODE 1.0 DNL (LSB) 0.4 0 -0.2 0 -0.2 -0.4 -0.6 -0.6 -0.8 -0.8 2.8 3.3 3.8 4.3 4.8 -1.0 5.3 5.5 VREF = 2.5V 0.2 -0.4 2.3 5.3 5.5 VREF = 10V 0.8 0.2 -65 3.8 DIFFERENTIAL NONLINEARITY vs VDD UNIPOLAR MODE 0.4 -55 3.3 Figure 32. 0.6 -45 2.8 Figure 31. VREF = 2.5V 1.8 2.3 VDD (V) 0.6 -1.0 1.8 VDD (V) VREF = 10V 0.8 VREF = 2.5V 0.2 -0.4 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.5 VDD (V) VDD (V) Figure 33. Figure 34. BIPOLAR MULTIPLYING MODE THD vs FREQUENCY BIPOLAR MULTIPLYING MODE THD vs FREQUENCY 500kHz Filter 80kHz Filter 30kHz Filter Code 3FFFh VREF = 6VRMS VDD = +5V Two OPA627s C1 = 20pF -75 -85 -95 -105 -115 -45 Total Harmonic Distortion (dB) INL (LSB) 0.6 1.8 VREF = 10V 0.8 VREF = 2.5V 0.6 -1.0 DNL (LSB) 1.0 VREF = 10V 0.8 Total Harmonic Distortion (dB) INTEGRAL NONLINEARITY vs VDD BIPOLAR MODE -55 -65 500kHz Filter 80kHz Filter 30kHz Filter Code 0000h VREF = 6VRMS VDD = +5V Two OPA627s C1 = 20pF -75 -85 -95 -105 -115 10 100 1000 10k 20k 30k 10 Frequency (Hz) 100 1000 10k 20k 30k Frequency (Hz) Figure 35. Figure 36. Submit Documentation Feedback 11 DAC8806 www.ti.com SBAS385A – APRIL 2006 – REVISED JUNE 2006 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. UNIPOLAR MULTIPLYING MODE THD vs FREQUENCY Total Harmonic Distortion (dB) -45 500kHz Filter 80kHz Filter 30kHz Filter Code 3FFFh VREF = 6VRMS VDD = +5V One OPA627 C1 = 20pF -55 -65 -75 -85 -95 -105 -115 10 100 1000 10k 20k 30k Frequency (Hz) Figure 37. THEORY OF OPERATION The DAC8806 is a multiplying, single-channel current output, 14-bit DAC. The architecture, illustrated in Figure 38, is an R-2R ladder configuration with the three MSBs segmented. Each 2R leg of the ladder is either switched to GND or to the IOUT terminal. The IOUT terminal of the DAC is held at a virtual GND potential by the use of an external I/V converter op amp. The R-2R ladder is connected to an external reference input (VREF) that determines the DAC full-scale current. The R-2R ladder presents a code independent load impedance to the external reference of 6kΩ ± 25%. The external reference voltage can vary in a range of –10V to +10V, thus providing bipolar IOUT current operation. By using an external I/V converter op amp and the RFB resistor in the DAC8806, an output voltage range of –VREF to +VREF can be generated. R R R RFB VREF 2R 2R 2R 2R 2R 2R 2R 2R 2R 2R 2R 2R RFB IOUT GND Figure 38. Equivalent R-2R DAC Circuit The DAC output voltage is determined by VREF and the digital data (D) according to Equation 1: D V OUT + −VREF 16384 (1) Each DAC code determines the 2R-leg switch position to either GND or IOUT. The external I/V converter op amp noise gain will also change because the DAC output impedance (as seen looking into the IOUT terminal) changes versus code. Because of this, the external I/V converter op amp must have a sufficiently low offset voltage such that the amplifier offset is not modulated by the DAC IOUT terminal impedance change. External op amps with large offset voltages can produce INL errors in the transfer function of the DAC8806 because of offset modulation versus DAC code. For best linearity performance of the DAC8806, an op amp (OPA277) is recommended; see Figure 39. This circuit allows VREF to swing from –10V to +10V. 12 Submit Documentation Feedback DAC8806 www.ti.com SBAS385A – APRIL 2006 – REVISED JUNE 2006 THEORY OF OPERATION (continued) VDD U1 VDD ROFS RFB +15V U2 VREF V+ IOUT DAC8806 VOUT OPA277 VGND -15V Figure 39. Voltage Output Configuration tWR WR DATA tDS tDH tLWD LDAC tLDAC tRST RST Figure 40. DAC8806 Timing Diagram Table 1. Function of Control Inputs CONTROL INPUTS RST WR LDAC 0 X X Asynchronous operation. Reset the input and DAC register to a predetermined value. The DAC8806 is reset to all 0s. 1 0 0 Load the input register with all 14 data bits. 1 1 1 Load the DAC register with the contents of the input register. 1 0 1 The input and DAC register are transparent. LDAC and WR are tied together and programmed as a pulse. The 14 data bits are loaded into the input register on the falling edge of the pulse and then loaded into the DAC register on the rising edge of the pulse. 1 1 REGISTER OPERATION 1 0 No register operation. Submit Documentation Feedback 13 DAC8806 www.ti.com SBAS385A – APRIL 2006 – REVISED JUNE 2006 APPLICATION INFORMATION Multiplying Mode THD versus Frequency Figure 35 and Figure 36 show the DAC8806 bipolar 4-quadrant multiplying mode total harmonic distortion (THD) versus frequency. Figure 35 shows the bipolar mode THD with the DAC8806 set to a full-scale code of 3FFFh. Figure 36 shows the bipolar multiplying mode THD with the DAC8806 set to a minus full-scale code of 0000h. In both graphs, two OPA627s are used for both the DAC output op amp and the reference inverting amplifier. A 6VRMS sine wave is used for the reference input VREF and is swept in frequency from 10Hz to 30kHz. The THD levels versus frequency are illustrated at various DAC output filtering levels using an external ac-coupled low-pass filter. Figure 37 illustrates the DAC8806 unipolar 2-quadrant multiplying mode THD versus frequency. The DAC8806 is set to a full-scale code of 3FFFh. A single OPA627 is used for the DAC output op amp. Stability Circuit For a current-to-voltage (I/V) design, as shown in Figure 41, the DAC8806 current output (IOUT) and the connection with the inverting node of the op amp should be as short as possible and laid out according to correct printed circuit board (PCB) layout design. For each code change there is a step function. If the gain bandwidth product (GBP) of the op amp is limited and parasitic capacitance is excessive at the inverting node, then gain peaking is possible. Therefore, a compensation capacitor C1 (4pF to 20pF, typ) can be added to the design for circuit stability, as shown in Figure 41. VDD U1 VDD ROFS RFB C1 VREF VREF DAC8806 IOUT OPA277 GND VOUT U2 Figure 41. Gain Peaking Prevention Circuit with Compensation Capacitor Bipolar Output Circuit The DAC8806, as a 4-quadrant multiplying DAC, can be used to generate a bipolar output. The polarity of the full-scale output (IOUT) is the inverse of the input reference voltage at VREF. Using a dual op amp, such as the OPA2277, full 4-quadrant operation can be achieved with minimal components. Figure 42 demonstrates a ±10VOUT circuit with a fixed +10V reference. V OUT + 14 D * 1Ǔ ǒ8192 VREF (2) Submit Documentation Feedback DAC8806 www.ti.com SBAS385A – APRIL 2006 – REVISED JUNE 2006 APPLICATION INFORMATION (continued) VREF U1 OPA2277 VDD RCOM R1 R1 DAC8806 REF R2 ROFS RFB ROFS RFB C1 D0 ¼ D13 DAC Parallel Bus Input Register IOUT DAC Register U2 OPA2277 VOUT AGND WR RST LDAC Control Logic DGND Figure 42. Bipolar Output Circuit Programmable Current Source Circuit A DAC8806 can be integrated into the circuit in Figure 43 to implement an improved Howland current pump for precise V/I conversions. Bidirectional current flow and high-voltage compliance are two features of the circuit. With a matched resistor network, the load current of the circuit is shown by Equation 3: (R2 ) R3)ńR1 IL + VREF D R3 (3) The value of R3 in the previous equation can be reduced to increase the output current drive of U3. U3 can drive ±20mA in both directions with voltage compliance limited up to 15V by the U3 voltage supply. Elimination of the circuit compensation capacitor (C1) in the circuit is not suggested as a result of the change in the output impedance (ZO), according to Equation 4: R1ȀR3(R1 ) R2) ZO + R1(R2Ȁ ) R3Ȁ) * R1Ȁ(R2 ) R3) (4) As shown in Equation 4, ZO with matched resistors is infinite and the circuit is optimum for use as a current source. However, if unmatched resistors are used, ZO is positive or negative with negative output impedance being a potential cause of oscillation. Therefore, by incorporating C1 into the circuit, possible oscillation problems are eliminated. The value of C1 can be determined for critical applications; for most applications, however, a value of several pF is suggested. Submit Documentation Feedback 15 DAC8806 www.ti.com SBAS385A – APRIL 2006 – REVISED JUNE 2006 APPLICATION INFORMATION (continued) R2¢ 15kW C1 10pF VDD R1¢ 150kW U3 R3¢ 50kW U1 U2 VREF VREF VOUT OPA277 VDD ROFS RFB DAC8806 IOUT R1 150kW R2 15kW R3 50W IL OPA277 LOAD GND Figure 43. Programmable Bidirectional Current Source Circuit Cross-Reference The DAC8806 has an industry-standard pinout. Table 2 provides the cross-reference information. Table 2. Cross-Reference 16 PRODUCT BIT INL (LSB) DAC8806IDB 14 ±1 DNL (LSB) SPECIFIED TEMPERATURE RANGE PACKAGE DESCRIPTION PACKAGE OPTION CROSSREFERENCE PART ±1 –40°C to +85°C SSOP-28 SSOP-28 LTC1591AIG Submit Documentation Feedback DAC8806 www.ti.com SBAS385A – APRIL 2006 – REVISED JUNE 2006 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (April, 2006) to A Revision ....................................................................................................... Page • • Changed to "current-to-voltage" from "voltage-to-current" ................................................................................................... 1 Changed to (I/V) from (V/I) ................................................................................................................................................. 14 Submit Documentation Feedback 17 PACKAGE OPTION ADDENDUM www.ti.com 24-Sep-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) DAC8806IDB ACTIVE SSOP DB 28 50 TBD Call TI Call TI DAC8806IDBG4 ACTIVE SSOP DB 28 50 TBD Call TI Call TI DAC8806IDBR ACTIVE SSOP DB 28 2000 TBD Call TI Call TI DAC8806IDBRG4 ACTIVE SSOP DB 28 2000 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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