RDC® R2886 RISC DSP Communication FAST ETHERNET RISC PROCESSOR R2886 Brief Sheet FAST ETHERNET RISC PROCESSOR Specifications subject to change without notice, contact your sales representatives for the most update information. Page 1 of 5 REV 1.0 Aug.25 2006 RDC® R2886 RISC DSP Communication FAST ETHERNET RISC PROCESSOR 1. Features - The character options are programmable for 1 start l CPU Core bit; 1, 1.5 or 2 stop bits; even, odd or no parity, 5~8 - RDC’s proprietary RISC architecture data bits - Five-stage pipeline architecture - Operation frequency: 150MHz l RDC Debug Tool Support - Supports a 16K-byte uniform cache - RDC debug tool with a JTAG-like interface l ROM/RAM/SDRAM Controller and Addressing l General Programmable I/O - 64 programmable I/O ports Space - Supports 16-bit data bus width - Pins individually configurable to input or output - Flash ROM/SRAM control interface mode - SDRAM control interface l Two 10/100M Fast Ethernet MAC Ports - 16M addressing space - IEEE 802.3u MII interface - 64K-byte I/O space - IEEE 802.3x flow control in full-duplex mode l Two Independent DMA Controllers - Internal loop-back self-test circuit support - Supports high-speed DMA transfers - Descriptor architecture for packet TX/RX l Interrupt Controller l PCI Control Interface Support - Provides 8 maskable external interrupt channels - Supports up to 3 PCI masters - Speed up to 33MHz l Counter/Timers - Three independent programmable 16-bit timers l Two Card Bus Interface Support - One programmable watchdog timer which can l Two USB 2.0 Host Port Support generate NMI or reset - Supports HS, FS and LS l High Performance UART Ports l Package Type - Supports 2 high performance UARTs with - With 128-pin PQFP & LFBGA-225 package type send/receive 16-byte FIFOs - Programmable baud rate generator l A Green Product - The data rates are programmable from 50 to 460.8K baud (max. to 1Mbps) Specifications subject to change without notice, contact your sales representatives for the most update information. Page 2 of 5 REV 1.0 Aug.25 2006 RDC® R2886 RISC DSP Communication FAST ETHERNET RISC PROCESSOR VCC GND X1 INT0 INT1 INT2 INT3 INTB_n X2 INTA_n SD_CLK PCICLK CLKOUTA 2. Block Diagram DRQ0/INT5 DRQ1/INT6 Interrupt Controller Unit Clock & Power Management Uuit Timer Controller Unit DMA Controller Unit RST_n Reset Unit MAC 0 MII 0 MAC 1 MII 1 PCIRST_n UCS_n MCS_n PCS0_n PCS1_n PCS2_n PCS3_n PCS5_n PCS6_n RDC RISC CPU Chip Select Unit 16K-B yte L1 Cache P CI Target RAS_n WE_n DQMH SDRAM/B us Interface Unit P CI Configuration Register PCI Bus Interface P CI Master Refresh Control Unit CAS_n 16550 UART Serial Port 0 UART0 16550 UART Serial Port 1 UART1 ARDY IOR_n IOW_n WR_n RD_n D[15:0] BA[1:0] A[22:0] Port 0 DP0, DM0 Port 1 DP1, DM1 USB 2.0 Host P CI Arbiter DQML PIO[63:0] PIO Unit PCIBus OVRCUR_n Specifications subject to change without notice, contact your sales representatives for the most update information. Page 3 of 5 REV 1.0 Aug.25 2006 RDC® R2886 RISC DSP Communication FAST ETHERNET RISC PROCESSOR 3. Package Information PQFP 208 pins 31.20mm 28.00mm PIN 1 IDENTIFIER 1.60mm (REF) e 0.5mm (BSC) b 0.17~0.27mm A2 = 3.20~3.60mm A2 A A = 4.10mm (Max.) A1 0.11~0.23mm A1 = 0.25mm (Min.) 4.10mm (Max.) 3.20~3.60mm DETAIL A 1.60mm 0.25mm 0.88 ± 0.15mm DETAIL A Specifications subject to change without notice, contact your sales representatives for the most update information. Page 4 of 5 REV 1.0 Aug.25 2006 RDC® R2886 RISC DSP Communication FAST ETHERNET RISC PROCESSOR LFBGA 225 balls Package Drawing Specifications subject to change without notice, contact your sales representatives for the most update information. Page 5 of 5 REV 1.0 Aug.25 2006