Preliminary Technical Data Hot Swap Controller and Digital Power Monitor with AlertB Output ADM1178 FEATURES Allows Safe Board Insertion and Removal from a Live Backplane Controls Supply Voltages from 3.15 V to14 V Precision Current Sense Amplifier Precision Voltage Input 12-Bit ADC for Current and Voltage Readback Charge Pumped Gate Drive for External N-FET Switch Adjustable Analog Current Limit with Circuit Breaker Fast Response Limits Peak Fault Current Automatic Retry or Latch-Off On Current Fault Programmable hot swap timing via TIMER pin Active-high ON pin AlertB pin for overcurrent interrupt I2C Fast Mode compliant interface (400 KHz max) 10-lead MSOP package FUNCTIONAL BLOCK DIAGRAM ADM1178 + I A 0 12-Bit ADC SDA I2C SCL 1 ADR - SENSE Current Sense Amplifier ALERTB Alert FET Drive Controller + ON 1.3V GATE - UV Comparator TIMER GND Figure 1. APPLICATIONS DIAGRAM APPLICATIONS Power Monitoring/Power Budgeting Central office Equipment Telecommunication and Datacommunication Equipment PC/Servers Mux V VCC R SENSE 3.15V - 14V Vcc N-Channel FET SENSE CONTROLLER GATE GENERAL DESCRIPTION The ADM1178 is an integrated hotswap controller and current sense amplifier that offers digital current and voltage monitoring via an on-chip 12-bit ADC, communicated through an I2C interface. An internal current sense amplifier senses voltage across the sense resistor in the power path via the VCC and SENSE pins. The ADM1178 limits the current through this resistor by controlling the gate voltage of an external N-channel FET in the power path, via the GATE pin. The sense voltage (and hence the inrush current) is kept below a preset maximum. The ADM1178 protects the external FET by limiting the time that it spends with the maximum current running in it. This current limit period is set by the choice of capacitor attached to the TIMER pin. Additionally, the device provides protection from overcurrent events at times after the hot-swap event is complete. In the case of a short-circuit event the current in the sense resistor will exceed an overcurrent trip threshold, and the FET will be switched off immediately by pulling down the GATE pin. ADM1178 ON TIMER SDA SDA SCL SCL ALERTB GND P=VI INTERRUPT ADR Figure 2. A 12-bit ADC can measure the current seen in the sense resistor, and also the supply voltage on the VCC pin. An industry standard I2C interface allows a controller to read current and voltage data from the ADC. Measurements can be initiated by an I2C command. Alternatively the ADC can run continuously and the user can read the latest conversion data whenever it is required. Up to 4 unique I2C addresses can be created by the way the ADR pin is connected. The ADM1178 is packaged in a 10-lead MSOP package. Rev. PrD May 2006 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2006 Analog Devices, Inc. All rights reserved. ADM1178 Preliminary Technical Data TABLE OF CONTENTS REVISION HISTORY May 06—Revision PrD: Preliminary Version Rev. PrD | Page 2 of 16 Preliminary Technical Data ADM1178 ADM1178—SPECIFICATIONS VVCC = 3.15V to 14V, TA = −40°C to +85°C, Typical Values at TA = +25°C unless otherwise noted. Table 1. Parameter VCC Pin Operating Voltage Range, VVCC Supply Current, ICC Undervoltage Lockout, VUVLO Undervoltage Lockout Hysteresis, VUVLOHYST ON Pin Input Current, IINON Trip Threshold, VONTH Trip Threshold Hysteresis, VONHYST Glitch Filter Time ALERTB Pin Output low voltage, VALERTOL Maximum sink current, IALERTMAX Input Current, IALERT SENSE Pin Input Leakage, ISENSE Overcurrent Fault Timing Threshold, VOCTIM Overcurrent Limit Threshold, VLIM Min Typ 3.15 1.6 2.8 25 −100 0 1.3 80 3 0.05 Pull-Down Current, ITIMERDN Trip Threshold High, VTIMERH Trip Threshold Low, VTIMERL ADR Pin Set address to 00, VADRLOWV Set address to 01, RADRLOWZ Units 14 3 V mA V mV +100 V mA 1 µA -1 −1 85 90 100 nA V mV µs 0.2 -2 Fast Overcurrent Trip Threshold, VOCFAST GATE Pin Drive Voltage, VGATE Drive Voltage, VGATE Drive Voltage, VGATE Pullup Current Pulldown Current Pulldown Current TIMER Pin Pull-Up Current (Power On Reset), ITIMERUPPOR Pull-Up Current (Fault Mode), ITIMERUPFAULT Pull-Down Current (Retry Mode), ITIMERDNRETRY Max +1 µA mV 110 mV 115 mV Conditions VVCC Rising ON rising IALERT = -100µA Maximum sink current allowed to flow in ALERT pin 0 output state VALERT = VCC; in Alert Condition VSENSE = VVCC VOCTRIM = (VVCC − VSENSE), Fault timing starts on the TIMER pin VLIM = (VVCC − VSENSE), Closed loop regulation to a current limit VOCFAST = (VVCC − VSENSE), Gate pulldown current turned on 5 6 5 10 7 8 7 12 2 25 10 12 10 14 V V V µA mA mA VGATE − VVCC, VVCC = 3.15 V VGATE − VVCC, VVCC = 5 V VGATE − VVCC, VVCC = 13.2 V VGATE = 0 V VGATE = 3 V, VVCC > UVLO VGATE = 3 V, VVCC < UVLO −4 −48 −5 −60 2 −6 −72 2.5 µA µA µA 1.235 0.18 100 1.3 0.2 1.365 0.22 µA V V Initial Cycle, VTIMER = 1 V During Current Fault, VTIMER = 1 V After current fault and during a cool-down period on a retry device, VTIMER = 1 V Normal Operation, VTIMER = 1 V TIMER rising TIMER falling 0 135 150 0.8 165 V kΩ +1 µA 5.5 5 V µA µA Set address to 10, IADRHIGHZ −1 Set address to 11, VADRHIGHV Input current for 11 decode, IADRLOW Input current for 00 decode, IADRHIGH 2 −40 3 −22 Rev. PrD | Page 3 of 16 Low state Resistor to ground state, load pin with specified resistance for 01 decode Open state, maximum load allowed on ADR pin for 10 decode High state VADR = 2.0 V to 5.5 V VADR = 0 V to 0.8 V ADM1178 Parameter MONITORING ACCURACY1 Current Sense Absolute Accuracy Current Sense Accuracy, TC VSENSE for ADC full-scale Voltage Sense Accuracy Preliminary Technical Data Min Typ Units Conditions TBD TBD % VSENSE = 75 mV −2.3 +2.2 % VSENSE = 75 mV, @ 0°C to +70°C TBD TBD % VSENSE = 50mV −2.5 +2.5 % VSENSE = 50 mV, @ 0°C to +70°C TBD TBD % VSENSE = 25mV −2.8 +2.8 % VSENSE = 25mV, @ 0°C to +70°C −3.5 +3.5 % VSENSE = 12.5 mV, @ 25°C +1.5 +1.5 %/°C mV % % V V VVCC = 3.0 V to 5.5V(VRANGE = 1) VVCC = 10.8 V to 13.2V(VRANGE = 0) VRANGE = 1 VRANGE = 0 ±0.01 105 0 0 6.656 26.6282 −1.5 −1.5 VCC for ADC full-scale, low range VCC for ADC full-scale, high range I2C Timing3 Low level input voltage, VIL High level input voltage, VIH Low level output voltage on SDA, VOL Output fall time on SDA from VIHMIN to VILMAX Maximum width of spikes suppressed by input filtering on SDA and SCL pins Input current, II, on SDA/SCL when not driving out a logic low Input capacitance on SDA/SCL SCL clock frequency, fSCL LOW period of the SCL clock HIGH period of the SCL clock Setup time for a repeated START condition, tSU;STA SDA output data hold time, tHD;DAT Set-up time for a stop condition, tSU;STO Bus free time between a STOP and a START condition, tBUF Capacitive load for each bus line Max 0.99 20+0.1CB 50 0.4 250 250 V V V ns ns −10 +10 µA 2.31 5 400 600 1300 600 100 600 1300 400 1 IOL = 3mA CB = bus capacitance from SDA to GND pF kHz ns ns ns ns ns ns pF Monitoring accuracy is a measure of the error in a code that is read back for a particular voltage/current. This is a combination of amplifier error, reference error and ADC error. 2 The maximum operating voltage is limited to VVCC =14 V which corresponds to an ADC code of 871. 3 The following conditions apply to all timing specifications: VBUS =3.3V, TA =25°C. All timings refer to VIHMIN and VILMAX. Rev. PrD | Page 4 of 16 Preliminary Technical Data ADM1178 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VCC Pin SENSE Pin TIMER Pin ON Pin ALERTB Pin GATE Pin SDA, SCL Pins ADR Pin Power Dissipation Storage Temperature Operating Temperature Range Lead Temperature Range (Soldering 10 sec) Junction Temperature Rating 20 V 20 V −0.3 V to +6 V −0.3 V to +20 V TBD 30 V −0.3 V to +6 V −0.3 V to +6 V TBD −65°C to +125°C −40°C to +85°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Ambient temperature = 25°C, unless otherwise noted. 300°C 150°C ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrD | Page 5 of 16 ADM1178 Preliminary Technical Data PIN CONFIGURATIONS Vcc 1 SENSE 2 ON 3 GND 4 TIMER 5 ADM1178 TOP VIEW 10 ALERTB 9 GATE 8 ADR (NOT TO SCALE) 7 SDA 6 SCL Figure 3. Pin Configurations PIN FUNCTIONAL DESCRIPTIONS Table 3. Pin No. 1 Name VCC 2 SENSE 3 ON 4 5 GND TIMER 6 7 8 SCL SDA ADR 9 GATE 10 ALERTB Description Positive supply input pin. The operating supply voltage range is between 3.15 V to 14 V. An undervoltage lockout (UVLO) circuit resets the ADM1178 when a low supply voltage is detected. Current sense input pin. A sense resistor between the VCC and SENSE pins sets the analog current limit. The hotswap operation of the ADM1178 controls the external FET gate to maintain the (VVCC-VSENSE) voltage at 100 mV or below. Undervoltage input pin. Aactive high pin. An internal ON comparator has a trip threshold of 1.3 V and the output of this comparator is used as an enable for the hotswap operation. With an external resistor divider from VCC to GND, this pin can be used to enable the hotswap operation one a specific voltage on VCC, giving an undervoltage function. Chip Ground Pin Timer pin. An external capacitor CTIMER sets a 270 ms/µF initial timing cycle delay and a 21.7 ms/µF fault delay. The GATE pin turns off whenever the TIMER pin is pulled beyond the upper threshold. An overvoltage detection with an external zener can be used to force this pin high. I2C Clock Pin. Open-drain output requires an external resistive pull-up. I2C Data I/O Pin. Open-drain output requires an external resistive pull-up. I2C Address Pin. This pin can be tied low, tied high, left floating or tied low through a resistor to set four different I2C addresses. GATE Output Pin. This pin is the high side gate drive of an external N-channel FET. This pin is driven by the FET drive controller which utilises a charge pump to provide a 12 µA pull-up current to charge the FET gate pin. The FET drive controller regulates to a maximum load current (100 mV through the sense resistor) by modulating the GATE pin. Alert Output Pin. Active low, open drain configuration. This pin asserts when an overcurrent condition is present. Rev. PrD | Page 6 of 16 Preliminary Technical Data ADM1178 OVERVIEW OF THE HOTSWAP FUNCTION When circuit boards are inserted into a live backplane, discharged supply bypass capacitors would draw large transient currents from the backplane power bus as they charge. Such transient currents can cause permanent damage to connector pins, and dips on the backplane supply which could reset other boards in the system. The ADM1178 is designed to turn a circuit board’s supply voltage on and off in a controlled manner, allowing the circuit board to be safely inserted into or removed from a live backplane. The ADM1178 can reside either on the backplane or on the circuit board itself. The ADM1178 controls the “inrush” current to a fixed maximum level by modulating the gate of an external Nchannel FET placed between the live supply rail and the load. This “hotswap” function protects the card connectors and the FET itself from damage and also limits any problems which could be caused by the high current loads on the live supply rail. The ADM1178 holds the GATE pin down (and thus the FET is held off) until a number of conditions are met. An undervoltage lockout circuit ensures that the device is being provided with an adequate input supply voltage. Once this has been successfully detected, the device goes through an initial timing cycle to provide a delay before it will attempt to hotswap. This delay ensures that the board is fully seated in the backplane before the board is powered up. Once the initial timing cycle is complete, the hotswap function is switched on under control of the ON pin. When asserted high the hotswap operation starts. The ADM1178 charges up the gate of the FET to turn on the load. It will continue to charge up the GATE pin until the linear current limit (set to 100 mV/RSENSE) is reached. For some combinations of low load capacitance and high current limit, this limit may not be reached before the load is fully charged up. If current limit is reached, the ADM1178 will regulate the GATE pin to keep the current at this limit. For currents above the overcurrent fault timing threshold, nominally 100 mV/ RSENSE, the current fault is timed by sourcing a current out to the TIMER pin. If the load becomes fully charged before the fault current limit time is reached (when the TIMER pin reaches 1.3 V), the current will drop below the overcurrent fault timing threshold, the ADM1178 will then charge the GATE pin higher to fully enhance the FET for lowest RON, and the TIMER pin will be pulled down again. using the TIMER pin to time a cool-down period in between hotswap attempts. The current and voltage threshold combinations on the TIMER pin set the retry duty cycle to 3.8%. The ADM1178 is designed to operate over a range of supplies from 3.15 V to 14 V. UNDERVOLTAGE LOCKOUT An internal undervoltage lockout (UVLO) circuit resets the ADM1178 if the VCC supply is too low for normal operation. The UVLO has a low-to-high threshold of 2.8 V, with 25 mV hysteresis. Above 2.8 V supply voltage, the ADM1178 will start the initial timing cycle. ON FUNCTION The ADM1178 has an active-high ON pin. The ON pin is the input to a comparator which has a low-to-high threshold of 1.3 V, an 80 mV hysteresis and a glitch filter of 3 μs. A low input on the ON pin turns off the hotswap operation by pulling the GATE pin to ground, turning off the external FET. The TIMER pin is also reset by turning on a pull-down current on this pin. A low-to-high transition on the ON pin starts the hotswap operation. A 10 kΩ pull-up resistor connecting the ON pin to the supply is recommended. Alternatively, an external resistor divider at the ON pin can be used to program an undervoltage lockout value higher than the internal UVLO circuit, thereby setting a voltage level at the VCC supply where the hotswap operation is to start. An RC filter can be added at the ON pin to increase the delay time at card insertion if the initial timing cycle delay is insufficient. TIMER FUNCTION The TIMER pin handles several timing functions with an external capacitor, CTIMER. There are two comparator thresholds: VTIMERH (0.2 V) and VTIMERL (1.3 V). The four timing current sources are a 5 µA and a 60 µA pull-up, and a 2 µA and a 100 µA pull-down. The 100 µA is a non-ideal current source approximating a 7 kΩ resistor below 0.4 V. These current and voltage levels, together with the value of CTIMER that the user chooses, determine the initial timing cycle time, the fault current limit time, and the hotswap retry duty cycle. If the fault current limit time is reached before the load drops below the current limit, a fault has been detected, and the hotswap operation is aborted by pulling down on the GATE pin to turn off the FET. The ADM1178-2 is latched off at that point and will only attempt to hotswap again when the ON pin is deasserted then asserted again. The ADM1178-1 will retry the hotswap operation indefinitely, keeping the FET in SOA by Rev. PrD | Page 7 of 16 ADM1178 Preliminary Technical Data GATE AND TIMER FUNCTIONS DURING A HOTSWAP CALCULATING CURRENT LIMITS AND FAULT CURRENT LIMIT TIME During hot insertion of a board onto a live supply rail at VCC, the abrupt application of supply voltage charges the external FET drain/gate capacitance, which could cause an unwanted gate voltage spike. An internal circuit holds GATE low before the internal circuitry wakes up. This reduces the FET current surges substantially at insertion. The GATE pin is also held low during the initial timing cycle, and until the ON pin has been taken high to start the hotswap operation. The nominal linear current limit is determined by a sense resistor connected between the VCC and SENSE pins as given by the equation below: ILIMIT(NOM) = VLIM(NOM)/RSENSE = 100 mV/RSENSE The minimum linear fault current is given by Equation 2: ILIMIT(MIN) = VLIM(MIN)/RSENSE(MAX) = 90 mV/RSENSE(MAX) During hotswap operation the GATE pin is first pulled up by a 12 μA current source. If the current through the sense resistor reaches the overcurrent fault timing threshold, Voctim, then a pull-up current of 60 µA on the TIMER pin is turned on, and this pin starts charging up. At a slightly higher voltage in the sense resistor, the error amplifier servos the GATE pin to maintain a constant current to the load by controlling the voltage across the sense resistor to the linear current limit, VLIM. The maximum linear fault current is given by Equation 3: A normal hotswap will complete when the board supply capacitors near full charge and the current through the sense resistor drops, to eventually reach the level of the board load current. As soon as the current drops below the overcurrent fault timing threshold, the current into the TIMER pin will switch from being a 60 μA pull-up to a 100 μA pull-down. The ADM1178 will then drive the GATE voltage as high as it can to fully enhance the FET and reduce RON losses to a minimum. IOCTIM(MIN) = VOCTIM(MIN)/RSENSE(MAX) = 85 mV/RSENSE(MAX) A hotswap will fail if the load current fails to drop below the overcurrent fault timing threshold, VOCTIM, before the TIMER pin has charged up to 1.3 V. In this case the GATE pin is then pulled down with a 2 mA current sink. The GATE pull-down will stay on until a hotswap retry starts, which can be forced by de-asserting then re-asserting the ON pin, or the device will retry automatically after a cool-down period, on the ADM11781. The ADM1178 also features a method of protection from sudden load current surges, such as a low impedance fault, when the current seen across the sense resistor may go well beyond the linear current limit. If the fast overcurrent trip threshold, VOCFAST, is exceeded, the 2 mA GATE pull-down is turned on immediately. This pulls the GATE voltage down quickly to enable the ADM1178 to limit the length of the current spike that gets through, and also to bring the current through the sense resistor back into linear regulation as quickly as possible. This protects the backplane supply from sustained overcurrent conditions, which may otherwise have caused problems with the backplane supply level dropping too low. (1) ILIMIT(MAX) = VLIM(MAX)/RSENSE(MIN) = 110 mV/RSENSE(MIN) (2) (3) The power rating of the sense resistor should be rated at the maximum linear fault current level. The minimum overcurrent fault timing threshold current is given by (4) The maximum fast overcurrent trip threshold current is given by IOCFAST(MAX) = VOCFAST(MAX)/RSENSE(MIN) = 115 mV/RSENSE(MIN) (5) The fault current limit time is the time that a device will spend timing an overcurrent fault, and is given by tFAULT ~= 21.7 × CTIMER ms/μF (6) INITIAL TIMING CYCLE When VCC is first connected to the backplane supply, there is an internal supply (time-point (1) in Figure 4) in the ADM1178 which needs to charge up. A very short time later (significantly less than 1 ms) the internal supply will be fully up and, since the undervoltage lockout voltage has been exceeded at VCC, the device will come out of reset. During this first short reset period the GATE pin is held down with a 25 mA pulldown current, and the TIMER pin is pulled down with a 100 μA current sink. The ADM1178 then goes through an initial timing cycle. At point (2) the TIMER pin is pulled high with 5 µA. At time point (3), the TIMER reaches the VTIMERL threshold and the first portion of the initial cycle ends. The 100 µA current source then pulls down the TIMER pin until it reaches 0.2 V at time point (4). The initial cycle delay (time point 2 to time point 4) is related to CTIMER by equation: tINITIAL ~= 270 × CTIMER ms/μF (7) When the initial timing cycle terminates, the device is ready to start a hotswap operation (assuming ON pin is asserted). In the example shown in Figure 4, the ON pin was asserted at the same time as VCC was applied, so the hotswap operation starts immediately after time-point (4). At this point the FET gate is Rev. PrD | Page 8 of 16 Preliminary Technical Data ADM1178 charged up with a 12 μA current source. At timepoint (5) the threshold voltage of the FET is reached and the load current begins to flow. The FET is controlled to keep the sense voltage at 100 mV (this corresponds to a maximum load current level defined by the value of RSENSE). At timepoint (6) VGATE and VOUT have reached their full potential and the load current has settled to its nominal level. Figure 5 illustrates the situation where the ON pin is asserted after VVCC is applied. (1) (2) (3) (4) (5) (6) V VCC HOTSWAP RETRY CYCLE ON ADM1178-1 With the ADM1178-1 the device will turn off the FET after an overcurrent fault, and will then use the TIMER pin to time a delay before automatically retrying to hotswap. As with all ADM1178 devices, on overcurrent fault is timed by charging the TIMER cap with a 60 μA pull-up current, and when the TIMER pin reaches 1.3 V the fault current limit time has been reached and the GATE pin is pulled down. On the ADM1178-1, the TIMER pin is then pulled down with a 2 μA current sink. When the TIMER pin reaches 0.2 V, it will automatically restart the hotswap operation. The cool down period is related to CTIMER by equation: V ON tCOOL ~ = 550 × CTIMER ms/μF (8) The retry duty cycle is thus given by V TIMER tFAULT/(tCOOL + tFAULT ) × 100% = 3.8% V GATE V SENSE V OUT INITIAL TIMING CYCLE Figure 4. Start-up (ON asserts as power is applied) (1) (2) (3)(4) (5)(6) (7) V VCC V ON V TIMER V GATE V SENSE V OUT INITIAL TIMING CYCLE Figure 5. Start-up (ON asserts after power is applied) Rev. PrD | Page 9 of 16 (9) ADM1178 Preliminary Technical Data data line SDA while the serial clock line SCL remains high. This indicates that a data stream will follow. All slave peripherals connected to the serial bus respond to the START condition, and shift in the next 8 bits, consisting of a 7-bit slave address (MSB first) plus a R/W bit, which determines the direction of the data transfer, i.e. whether data will be written to or read from the slave device (0 = write, 1 = read). VOLTAGE AND CURRENT READBACK In addition to providing hot swap functionality, the ADM1178 also contains the components to allow voltage and current readback over an I2C bus. The voltage output of the current sense amplifier and the voltage on the VCC pin are fed into a 12-bit ADC via a multiplexer. The device can be instructed to convert voltage and/or current at any time during operation via an I2C command. When all conversions are complete the voltage and/or current values can be read out to 12-bit accuracy in two or three bytes. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and holding it low during the high period of this clock pulse. All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, the master will write to the slave device. If the R/W bit is a 1, the master will read from the slave device. SERIAL BUS INTERFACE Control of the ADM1178 is carried out via the Inter-IC Bus (I2C). This interface is compatible with fastmode I2C (400 kHz max). The ADM1178 is connected to this bus as a slave device, under the control of a master device. 2. IDENTIFYING THE ADM1178 ON THE I2C BUS The ADM1178 has a 7-bit serial bus slave address. When the device is powered up, it will do so with a default serial bus address. The three MSBs of the address are set to 111 and the two MSBs are set to 10, to give an address 111xx10. Bits A2 and A3 are determined by the state of the ADR pin. There are four different configurations available on the ADR pin which correspond to four different I2C addresses for these bits. These are explained in Table 4 below. This scheme allows four ADM1178 devices to operation on a single I2C bus. If the operation is a write operation, the first data byte after the slave address is a command byte. This tells the slave device what to expect next. It may be an instruction such as telling the slave device to expect a block write, or it may simply be a register address that tells the slave where subsequent data is to be written. Table 4. Setting I2C Addresses via the ADR Pin ADR Configuration Low state Resistor to GND Floating (unconnected) High state Since data can flow in only one direction as defined by the R/W bit, it is not possible to send a command to a slave device during a read operation. Before doing a read operation, it may first be necessary to do a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read. Address 0xE4 0xEC 0xF4 0xFC 3. GENERAL I2C TIMING Figure 6 and Figure 7 show timing diagrams for general read and write operations using the I2C. The I2C specification defines specific conditions for different types of read and write operation, which are discussed later. The general I2C protocol operates as follows: 1. Data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an acknowledge bit from the slave device. Data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low to high transition when the clock is high may be interpreted as a STOP signal. The master initiates data transfer by establishing a START condition, defined as a high to low transition on the serial Rev. PrD | Page 10 of 16 When all data bytes have been read or written, stop conditions are established. In WRITE mode, the master will pull the data line high during the 10th clock pulse to assert a STOP condition. In READ mode, the master device will release the SDA line during the low period before the ninth clock pulse, but the slave device will not pull it low. This is known as No Acknowledge. The master will then take the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a STOP condition. Preliminary Technical Data ADM1178 9 1 9 1 SCL 0 SDA 0 1 1 A1 1 A0 D7 R/W D6 D5 ACK. BY SLAVE START BY MASTER FRAME 1 SLAVE ADDRESS 1 D4 D2 D3 D1 D0 ACK. BY SLAVE FRAME 2 COMMAND CODE 1 9 9 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D7 D0 D6 D5 D4 ACK. BY SLAVE FRAME 3 DATA BYTE D3 D2 D1 D0 STOP BY MASTER ACK. BY SLAVE FRAME N DATA BYTE Figure 6. General I2C Write Timing Diagram 1 1 9 9 SCL 0 SDA 1 0 1 1 A1 A0 D7 R/W D6 D4 D5 ACK. BY SLAVE START BY MASTER FRAME 1 SLAVE ADDRESS 1 D3 D2 D1 ACK. BY MASTER FRAME 2 DATA BYTE 9 D0 1 9 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 D6 D7 D5 D4 ACK. BY MASTER FRAME 3 DATA BYTE D3 D2 D1 D0 NO ACK. FRAME N DATA BYTE STOP BY MASTER Figure 7. General I2C Read Timing Diagram tLOW tR tHD;STA tF SCL tHD;STA tSU;STA tHIGH tHD;DAT tSU;DAT tSU;STO SDA tBUF P S S Figure 8. Serial Bus Timing Diagram Rev. PrD | Page 11 of 16 P ADM1178 Preliminary Technical Data WRITE COMMAND BYTE WRITE AND READ OPERATIONS 2 The I C specification defines several protocols for different types of read and write operations. The ones used in the ADM1178 are discussed below. The following abbreviations are used in the diagrams: In this operation the master device sends a command byte to the slave device, as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends the command byte. The command byte is identified by an MSB =0. (An MSB =1 indicates an Extended Register Write. See next section.) QUICK COMMAND 5. The slave asserts ACK on SDA. This operation allows the master check if the slave is present on the bus. This entails the following: 6. The master asserts a STOP condition on SDA to end the transaction. Table 5. I2C abbreviations S P R W A N START STOP READ WRITE ACKNOWLEDGE NO ACKNOWLEDGE 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 1 S 2 3 SLAVE WA ADDRESS 1 2 3 4 5 6 SLAVE COMMAND S WA A P ADDRESS BYTE Figure 10. Command Byte Write The seven LSBs of the command byte are used to configure and control the ADM1178. Details of the function of each bit are provided in Table 6. Figure 9. Quick Command Table 6. Command Byte Operations Bit Default Name Function C0 0 V_CONT Set to convert voltage continuously. If readback is attempted before the first conversion is complete, the ADM1178 will ACK and return all zeros in the returned data. C1 C2 0 0 V_ONCE I_CONT C3 C4 0 0 I_ONCE VRANGE C5 C6 0 0 N/A STATUS_RD Set to convert voltage once. Self-clears. I2C will NACK an attempted read until ADC conversion is complete. Set to convert voltage continuously. If readback is attempted before the first conversion is complete, the ADM1178 will ACK and return all zeros in the returned data. Set to convert current once. Self-clears. I2C will NACK an attempted read until ADC conversion is complete. Selects different internal attenuation resistor networks for voltage readback. A “0” in C4 selects a 14:1 voltage divider. A “1” in C4 selects a 7:2 voltage divider. With an ADC full-scale of 1.902 V, the voltage at the VCC pin for an ADC full-scale result is 26.63 V for VRANGE = 0 and 6.66 V for VRANGE = 1. Unused Status Read. When this bit is set the data byte read back from the ADM1178 will be the STATUS byte. This contains the status of the device alerts. See Table14 for full details of the status byte. Rev. PrD | Page 12 of 16 Preliminary Technical Data ADM1178 WRITE EXTENDED BYTE In this operation the master device writes to one of the three extended registers of the slave device, as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends the register address byte. The MSB of this byte is set to 1 to indicate an extended register write. The two LSBs indicate which of the three extended registers will be written to (see Table 7). All other bits should be set to 0. 8. The master asserts a STOP condition on SDA to end the transaction. 1 S 2 3 5 4 6 7 8 SLAVE REGISTER REGISTER R A A N P ADDRESS DATA ADDRESS Figure 11. Command Byte Write Table 8, Table 9, and give details of each extended register. Table 7. Extended Register Addresses 5. The slave asserts ACK on SDA. 6. The master sends the command byte. The command byte is identified by an MSB = 0. (An MSB = 1 indicates an Extended Register Write. See next section.) 7. The slave asserts ACK on SDA. A6 0 0 0 A5 0 0 0 A4 0 0 0 A3 0 0 0 A2 0 0 0 A1 0 1 1 A0 1 0 1 Extended Register ALERT_EN ALERT_TH CONTROL Table 8. ALERT_EN Register Operations Bit 0 Default 0 Name EN_ADC_OC1 1 0 EN_ADC_OC4 2 1 EN_HS_ALERT 3 0 EN_OFF_ALERT 4 0 CLEAR Function Enabled if a single ADC conversion on the I channel has exceeded the threshold set in the ALERT_TH register Enabled if four consecutive ADC conversions on the I channel have exceeded the threshold set in the ALERT_TH register Enabled if the hotswap has either latched off, or entered a cool down cycle, because of an overcurrent event Enable an ALERT if the HS operation is turned off by a transition which de-asserts the ON pin, or by an operation which writes the SWOFF bit high. Clears the ON_ALERT, HS_ALERT and ADC_ALERT status bits in the STATUS register. These may immediately reset if the source of the alert has not been cleared, or disabled with the other bits in this register. This bit self-clears to 0 after the STATUS register bits have been cleared. Table 9. ALERT_TH Register Operations Bit 7:0 Default FF Function The ALERT_TH register sets the current level at which an alert will occur. Defaults to ADC full-scale. ALERT_TH 8-bit number corresponds to the top 8-bits of the current channel data. Table 10. CONTROL Register Operations Bit 0 Default 0 Name SWOFF Function Force hotswap off. Equivalent to de-asserting the ON pin. Rev. PrD | Page 13 of 16 ADM1178 Preliminary Technical Data READ VOLTAGE AND/OR CURRENT DATA BYTES The ADM1178 can be set up to provide information in three different ways (see Write Command Byte section above). Depending on how the device is configured the following data can be read out of the device after a conversion (or conversions): 1. Voltage and Current Readback. The ADM1178 will digitize both voltage and current. Three bytes will be read out of the device in the following format: 5. The master asserts ACK on SDA. 6. The master receives the second data byte. 7. The master asserts ACK on SDA. 8. The master receives the third data byte. 9. The master asserts NO ACK on SDA. 10. The master asserts a STOP condition on SDA and the transaction ends. Table 11. Byte 1 2 3 Contents Voltage MSBs Current MSBs Voltage LSBs B7 V11 B6 V10 B5 V9 B4 V8 B3 V7 B2 V6 B1 V5 B0 V4 I11 I10 I9 I8 I7 I6 I5 I4 V3 V2 V1 V0 I3 I2 I1 I0 For the cases where the master is reading voltage only or current only, only two data bytes will be read and events 7 and 8 above will not be required. 1 2. Voltage Readback. 3 4 5 6 8 7 9 10 Figure 12. Three Byte Read fromADM1178 The ADM1178 will digitize voltage only. Two bytes will be read out of the device in the following format: 1 B7 B6 B5 B4 B3 B2 V11 V10 V9 V8 V7 V6 V3 V2 V1 V0 0 0 B1 V5 0 B0 V4 0 2 3 6 5 4 7 8 SLAVE REGISTER REGISTER S R A A N P ADDRESS DATA ADDRESS Table 12. Byte Contents 1 Voltage MSBs 2 Voltage LSBs 2 SLAVE R A DATA 1 A DATA 2 A DATA 3 N P S ADDRESS Figure 13. Two Byte Read fromADM1178 Read Status Register A single register of status data can also be read from the ADM1178. 3. Current Readback. 1. The master device asserts a START condition on SDA. 2. The master sends the 7-bit slave address followed by the read bit (high). B0 I4 0 3. The addressed slave device asserts ACK on SDA. 4. The master receives the status byte. The following series of events occur when the master receives three bytes (voltage and current data) from the slave device: 5. The master asserts ACK on SDA. The ADM1178 will digitize current only. Two bytes will be read out of the device in the following format: Table 13. Byte Contents 1 Current MSBs 2 Current LSBs B7 I11 I3 B6 I10 I2 B5 B4 B3 B2 I9 I8 I7 I6 I1 I0 0 0 B1 I5 0 1. The master device asserts a START condition on SDA. 2. The master sends the 7-bit slave address followed by the read bit (high). 3. The addressed slave device asserts ACK on SDA. 4. The master receives the first data byte. 1 2 3 4 5 SLAVE S R A DATA 1 A ADDRESS Figure 14. Status Read fromADM1178 Table 14 shows the ADM1178 status registers in detail. Note that bits 1, 3 and 5 are cleared by writing to bit 4 of the ALERT_EN register (CLEAR). Rev. PrD | Page 14 of 16 Preliminary Technical Data ADM1178 Table 14. Status Byte Operations Bit 0 1 Name ADC_OC ADC_ALERT 2 HS_OC 3 4 HS_ALERT OFF_STATUS 5 OFF_ALERT Function An ADC based overcurrent comparison has been detected on the last 3 conversions An ADC based overcurrent trip has happened, which has caused the ALERT. Cleared by writing to bit 4 of the ALERT_EN register. The hotswap is off due to an analog overcurrent event. On parts which latch off, this will be the same as the HS_ALERT status bit (if EN_HS_ALERT=1). On the retry parts this will indicate the current state—a 0 could indicate that the data was read during a period when the device is retrying, or that it has successfully hotswapped by retrying after at least one overcurrent timeout. The hotswapper has failed since the last time this was reset. Cleared by writing to bit 4 of the ALERT_EN register. The state of the ON pin. Set to 1 if the input pin is de-asserted. Can also be set to 1 by writing to the SWOFF bit of the CONTROL register. An alert has been caused either by the ON pin or the SWOFF bit. Cleared by writing to bit 4 of the ALERT_EN register. KELVIN SENSE RESISTOR CONNECTION When using a low-value sense resistor for high current measurement the problem of parasitic series resistance can arise. The lead resistance can be a substantial fraction of the rated resistance making the total resistance a function of lead length. This problem can be avoided by using a Kelvin sense connection. This type of connection separates the current path through the resistor and the voltage drop across the resistor. Figure 15 below shows the correct way to connect the sense resistor between the VCC and SENSE pins of the ADM1178. SENSE RESISTOR CURRENT FLOW FROM SUPPLY CURRENT FLOW TO LOAD KELVIN SENSE TRACES V CC SENSE ADM1178 Figure 15. Kelvin Sense Connections Rev. PrD | Page 15 of 16 ADM1178 Preliminary Technical Data OUTLINE DIMENSIONS 0.122 (3.10) 0.114 (2.90) 10 6 0.199 (5.05) 0.187 (4.75) 0.122 (3.10) 0.114 (2.90) 1 5 PIN 1 0.0197 (0.50) BSC 0.120 (3.05) 0.120 (3.05) 0.112 (2.85) 0.037 (0.94) 0.112 (2.85) 0.043 (1.10) MAX 0.031 (0.78) 0.006 (0.15) 0.012 (0.30) 0.002 (0.05) 0.006 (0.15) SEATING PLANE 0.009 (0.23) 6o o 0 0.005 (0.13) 0.028 (0.70) 0.016 (0.40) Figure 16. 10-Lead MSOP Package (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model ADM1178-1ARMZ-R7 ADM1178-2ARMZ-R7 1 Hotswap Retry Option Automatic Retry Version Latched Off Version Brand M62 M64 Temperature Range −40°C to +85°C −40°C to +85°C Z = Pb-free part. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06048-0-5/06(PrD) Rev. PrD | Page 16 of 16 Package Description MSOP-10 MSOP-10 Package Outline RM-10 RM-10