NUMONYX SMC512AF

SMCxxxAF
32 Mbyte, 64 Mbyte, 128 Mbyte, 256 Mbyte and
512 Mbyte 3.3 V / 5 V supply CompactFlash™ card
Features
■
Custom-designed, highly-integrated memory
controller
– Fully compliant with CompactFlashTM
specification 2.0
– Fully compatible with PCMCIA specification
– PC card ATA interface supported
– True IDE mode compatible
■
Small form factor
– 36.4 mm x 42.8 mm x 3.3 mm
■
Low-power CMOS technology
■
3.3 V / 5.0 V power supply
■
Power saving mode (with automatic wake-up)
■
■
High reliability
– MTBF > 3,000,000 hours
– Data reliability: < 1 non-recoverable error
per 1014 bits read
– Endurance: > 2,000,000 Erase/Program
cycles
– Number of card insertions/removals: >
10,000
High performance
– Up to 16.6 Mbit/s transfer rate
– Sustained write performance
(host to card: 7.2 Mbit/s)
■
Operating system support
– Standard software drivers operation
■
Available densities (formatted)
– 32 Mbytes to 512 Mbytes
■
Hot swappable
Table 1.
CompactFlashTM
Device summary
Reference
Part number
Package form factor
Operating voltage range
CF type I
3.3 V+-10%, 5 V+-10%
SMC032AF
SMC064AF(1)
SMCxxxAF
SMC128AF(1)
SMC256AF(1)
SMC512AF(1)
1. Obsolete part number.
January 2008
Rev 3
1/82
www.numonyx.com
1
Contents
SMCxxxAF
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2
Capacity specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
Card physical description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
Electrical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1
Electrical description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2
Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3
Current measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6
Card configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.1
6.2
6.3
6.4
6.5
2/82
Configuration Option register (base + 00h in attribute memory) . . . . . . . 31
6.1.1
LevlREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1.2
Conf5 - Conf0 (configuration index) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Card Configuration and Status register (base + 02h in attribute memory) 32
6.2.1
Changed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2.2
SigChg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2.3
IOis8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2.4
PwrDwn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2.5
Int . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Pin Replacement register (base + 04h in attribute memory) . . . . . . . . . . 33
6.3.1
CReady . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.3.2
CWProt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.3.3
RReady . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.3.4
WProt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.3.5
MReady . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.3.6
MWProt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Socket and Copy register (base + 06h in attribute memory) . . . . . . . . . . 34
6.4.1
Drive # . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.4.2
X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Attribute memory function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
SMCxxxAF
7
8
Contents
6.6
I/O transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.7
Common memory transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.8
True IDE mode I/O function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Software interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.1
CF-ATA Drive register set definition and protocol . . . . . . . . . . . . . . . . . . . 39
7.2
Memory mapped addressing (conf = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.3
Contiguous I/O mapped addressing (conf = 1) . . . . . . . . . . . . . . . . . . . . 41
7.4
I/O primary and secondary address configurations (conf = 2,3) . . . . . . . 42
7.5
True IDE mode addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
CF-ATA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.1
Data register (address 1F0h [170h]; offset 0, 8, 9) . . . . . . . . . . . . . . . . . . 44
8.2
Error register (address 1F1h [171h]; offset 1, 0Dh read only) . . . . . . . . . 44
8.2.1
Bit 7 (BBK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2.2
Bit 6 (UNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2.3
Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2.4
Bit 4 (IDNF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.2.5
Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.2.6
Bit 2 (abort) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.2.7
Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.2.8
Bit 0 (AMNF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.3
Feature register (address 1F1h [171h]; offset 1, 0Dh write only) . . . . . . . 45
8.4
Sector Count register (address 1F2h [172h]; offset 2) . . . . . . . . . . . . . . . 45
8.5
Sector Number (LBA 7-0) register (address 1F3h [173h]; offset 3) . . . . . 45
8.6
Cylinder Low (LBA 15-8) register (address 1F4h [174h]; offset 4) . . . . . . 46
8.7
Cylinder High (LBA 23-16) register (address 1F5h [175h]; offset 5) . . . . 46
8.8
Drive/Head (LBA 27-24) register (address 1F6h [176h]; offset 6) . . . . . . 46
8.8.1
Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.8.2
Bit 6 (LBA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.8.3
Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.8.4
Bit 4 (DRV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.8.5
Bit 3 (HS3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.8.6
Bit 2 (HS2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.8.7
Bit 1 (HS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3/82
Contents
SMCxxxAF
8.8.8
8.9
8.10
8.11
9
4/82
Bit 0 (HS0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Status & alternate status registers (address 1F7h [177h] & 3F6h [376h];
offsets 7 & Eh) 48
8.9.1
Bit 7 (BUSY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.9.2
Bit 6 (RDY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.9.3
Bit 5 (DWF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.9.4
Bit 4 (DSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.9.5
Bit 3 (DRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.9.6
Bit 2 (CORR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.9.7
Bit 1 (IDX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.9.8
Bit 0 (ERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Device control register (address 3F6h [376h]; offset Eh) . . . . . . . . . . . . . 49
8.10.1
Bit 7 to 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.10.2
Bit 2 (SW Rst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.10.3
Bit 1 (–IEn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.10.4
Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Card (drive) address register (address 3f7h [377h]; offset Fh) . . . . . . . . 50
8.11.1
Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.11.2
Bit 6 (–WTG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.11.3
Bit 5 (–HS3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.11.4
Bit 4 (–HS2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.11.5
Bit 3 (–HS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.11.6
Bit 2 (–HS0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.11.7
Bit 1 (–nDS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.11.8
Bit 0 (–nDS0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
CF-ATA command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.1
Check Power mode command (98h or E5h) . . . . . . . . . . . . . . . . . . . . . . 52
9.2
Execute Drive Diagnostic command (90h) . . . . . . . . . . . . . . . . . . . . . . . . 53
9.3
Erase Sector(s) command (C0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.4
Identify Drive command (ECh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.4.1
Word 0: general configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.4.2
Word 1: default number of cylinders . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.4.3
Word 3: default number of heads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.4.4
Word 6: default number of sectors per track . . . . . . . . . . . . . . . . . . . . . 54
9.4.5
Word 7-8: number of sectors per card . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.4.6
Word 10-19: memory card serial number . . . . . . . . . . . . . . . . . . . . . . . 55
SMCxxxAF
Contents
9.4.7
Word 23-26: firmware revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.4.8
Word 27-46: model number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.4.9
Word 47: read/write multiple sector count . . . . . . . . . . . . . . . . . . . . . . . 55
9.4.10
Word 49: capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.4.11
Word 51: PIO data transfer cycle timing mode . . . . . . . . . . . . . . . . . . . 55
9.4.12
Word 53: translation parameter valid . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.4.13
Word 54-56: current number of cylinders, heads, sectors/track . . . . . . . 55
9.4.14
Word 57-58: current capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.4.15
Word 59: multiple sector setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.4.16
Word 60-61: total sectors addressable in LBA mode . . . . . . . . . . . . . . . 56
9.4.17
Word 64: advanced PIO transfer modes supported . . . . . . . . . . . . . . . . 56
9.4.18
Word 67: minimum PIO transfer cycle time without flow control . . . . . . 56
9.4.19
Word 68: minimum PIO transfer cycle time with IORDY . . . . . . . . . . . . 56
9.5
Idle command (97h or E3h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9.6
Idle Immediate command (95h or E1h) . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.7
Initialize Drive Parameters command (91h) . . . . . . . . . . . . . . . . . . . . . . . 59
9.8
NOP command (00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.9
Read Buffer command (E4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.10
Read Multiple command (C4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.11
Read Sector(s) command (20h or 21h) . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.12
Read Verify Sector(s) command (40h or 41h) . . . . . . . . . . . . . . . . . . . . . 62
9.13
Recalibrate command (1Xh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.14
Request Sense command (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.15
Seek command (7Xh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.16
Set Features command (EFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.17
Set Multiple mode command (C6h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.18
Set Sleep mode command (99h or E6h) . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.19
Standby command (96h or E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.20
Standby Immediate command (94h or E0h) . . . . . . . . . . . . . . . . . . . . . . . 68
9.21
Translate Sector command (87h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
9.22
Wear Level command (F5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
9.23
Write Buffer command (E8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
9.24
Write Multiple command (C5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
9.25
Write Multiple without Erase command (CDh) . . . . . . . . . . . . . . . . . . . . . 72
5/82
Contents
SMCxxxAF
9.26
Write Sector(s) command (30h or 31h) . . . . . . . . . . . . . . . . . . . . . . . . . . 72
9.27
Write Sector(s) without Erase command (38h) . . . . . . . . . . . . . . . . . . . . 73
9.28
Write Verify command (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10
CIS information (typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
11
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
12
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6/82
SMCxxxAF
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
System performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Environmental specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CF capacity specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
System reliability and maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin assignment and pin type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Absolute maximum conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Input power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Input leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output drive type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output drive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Attribute memory Read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Configuration register (attribute memory) Write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Common memory Read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Common memory Write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
I/O Read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
I/O Write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
True IDE mode I/O Read/Write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
CompactFlash memory card registers and memory space decoding. . . . . . . . . . . . . . . . . 30
CompactFlash memory card configuration registers decoding. . . . . . . . . . . . . . . . . . . . . . 31
Configuration Option register (default value: 00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
CompactFlash memory card configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Card Configuration and Status register (default value: 00h). . . . . . . . . . . . . . . . . . . . . . . . 32
Pin Replacement register (default value: 0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Pin Replacement Changed bit/Mask bit values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Socket and Copy register (default value: 00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Attribute memory function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
I/O function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Common memory function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
True IDE mode I/O function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
I/O configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Memory mapped decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Contiguous I/O decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Primary and secondary I/O decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
True IDE mode I/O decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Data register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Drive/Head register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Status & alternate status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Device control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Card (drive) address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
CF-ATA command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Check Power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Execute Drive Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7/82
List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
8/82
SMCxxxAF
Diagnostic codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Erase Sector(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Identify drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Identify drive information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Idle Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Initialize Drive Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Read Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Read Multiple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Read Sector(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Read Verify Sector(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Recalibrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Request Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Extended Error codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Set Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Features supported. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Transfer mode values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Set Multiple mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Set Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Standby Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Translate Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Translate Sector information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Wear Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Write Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Write Multiple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Write Multiple without Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Write Sector(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Write Sector(s) without Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Write Verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
SMCxxxAF
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
CompactFlash memory card block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Attribute memory Read timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Configuration register (attribute memory) Write timing diagram . . . . . . . . . . . . . . . . . . . . . 23
Common memory Read timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Common memory Write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
I/O Read timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
I/O Write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
True IDE mode I/O timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Type I CompactFlash memory card dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9/82
Description
1
SMCxxxAF
Description
The CompactFlash is a small form factor non-volatile memory card which provides high
capacity data storage. Its aim is to capture, retain and transport data, audio and images,
facilitating the transfer of all types of digital information between a large variety of digital
systems.
The card operates in three basic modes,
●
PCMCIA I/O mode
●
PCMCIA memory mode
●
True IDE mode
It conforms to the PC card specification when operating in the PCMCIA I/O mode and
PCMCIA memory mode (Personal Computer Memory Card International Association
standard, JEIDA in Japan) and to the ATA specification when operating in True IDE mode.
CompactFlash cards can be used with passive adapters in a PC-card type II or type III
socket.
The card has an internal intelligent controller which manages interface protocols, data
storage and retrieval as well as error correcting code (ECC), defect handling, diagnostics
and clock control. Once the card has been configured by the host, it behaves as a standard
ATA (IDE) disk drive.
The card has a super cap on VCC and a powerful power-loss management feature to
prevent data corruption after power-down.
The specification has been realized and approved by the CompactFlash association (CFA).
This non-proprietary specification enables users to develop CF products that function
correctly and are compatible with future CF design.
The system highlights are shown in Table 2, Table 3, Table 4, Table 5, Table 6 and Table 7.
Related documentation
10/82
●
PCMCIA PC card standard, 1995
●
PCMCIA PC card ATA specification, 1995
●
AT attachment interface document, American National Standards Institute, X3.2211994
●
CF+ and CompactFlash specification revision 2.0.
SMCxxxAF
Description
Table 2.
System performance
System performance
Max
Unit
Sleep to write
2.2
ms
Sleep to read
2.4
ms
Power-up to ready
80
ms
16.6 (113X)(1)
Data transfer rate (burst)
Sustained Read
12.2 (83X)
Sustained Write
7.2 (49X)
Read
180
Write
40
Mbit/s
(1)
Mbit/s
(1)
Mbit/s
Command to DRQ
µs
1. 113X, 83X and 49X, speed grade markings where 1X = 150 Kbytes/s. All values refer to the 256-Mbyte
CompactFlash card in PIO mode 4, cycle time 120 ns.
Current consumption(1)
Table 3.
Current consumption (typ)
3.3 V
5V
Unit
Read
57
60
mA
Write
70
71
mA
Standby
0.4
1
mA
Sleep mode
0.4
1
mA
1. All values are typical at 25 °C and nominal supply voltage and refer to 256-Mbyte CompactFlash card.
Table 4.
Environmental specifications
Environmental specifications
Operating
Non-operating
Temperature
–40 to 85 °C
–50 to 100 °C
Humidity (non-condensing)
N/A
85% RH, at 85 °C
Salt water spray
N/A
3% NaCl at 35 °C(1)
Vibration (peak -to-peak)
N/A
30 Gmax
Shock
N/A
3,000 Gmax
1. MIL STD METHOD 1009.
Table 5.
Physical dimensions
Physical dimensions
Unit
Width
42.8
mm
Height
36.4
mm
Thickness
3.3
mm
Weight (typ)
10
g
11/82
Capacity specification
2
SMCxxxAF
Capacity specification
Table 6 shows the specific capacity for the various CF models and the default number of
heads, sector/tracks and cylinders.
Table 6.
CF capacity specification
Default_sectors_
Default_cylinders Default_heads
Sectors_card
track
Total
addressable
capacity
(byte)
Model No
Capacity
SMC032
32 Mbyte
492 (0x1EC)
8 (0x08)
16 (0x10)
62976
32243712
SMC064
64 Mbyte
496 (0x1F0)
8 (0x08)
32 (0x20)
126976
65011712
SMC128
128 Mbyte
498 (0x1F2)
16 (0x10)
32 (0x20)
254976
130547712
SMC256
256 Mbyte
998 (0x3E6)
16 (0x10)
32 (0x20)
510976
261619712
SMC512
512 Mbyte
1014 (0x3F6)
16 (0x10)
63 (0x3F)
1022112
523321344
Table 7.
System reliability and maintenance
MTBF (at 25 °C)
> 3,000,000 hours
Insertions/removals
> 10,000
Preventive maintenance
None
Data reliability
< 1 non-recoverable error per 1014 bits Read
0 + 70 C > 2,000,000 Erase/Program cycles(1)
Endurance
1. Dependent on final system qualification data.
12/82
-40 + 85 C > 600,000 Erase/Program cycles(1)
SMCxxxAF
3
Card physical description
Card physical description
The CompactFlash memory card contains a single chip controller and Flash memory
module(s). The controller interfaces with a host system allowing data to be written to and
read from the Flash memory module(s). Figure 1 shows the block diagram of the
CompactFlash memory card.
The card is offered in a type I package with a 50-pin connector consisting of two rows of 25
female contacts on 50 mil (1.27 mm) centers. Figure 9 shows type I card dimensions.
Figure 1.
CompactFlash memory card block diagram
Data
In/Out
Host
interface
Controller
Control
Flash
module(s)
CompactFlash storage card
AI04300
13/82
Electrical interface
SMCxxxAF
4
Electrical interface
4.1
Electrical description
The CompactFlash memory card operates in three basic modes:
●
PC card ATA using I/O mode,
●
PC card ATA using memory mode,
●
True IDE mode, which is compatible with most disk drives.
The signal/pin assignments are listed in Table 8 where Low active signals have a ‘–’ prefix.
Pin types are Input, Output or Input/Output.
The configuration of the card is controlled using the standard PCMCIA Configuration
registers starting at address 200h in the attribute memory space of the memory card. For
True IDE mode, pin 9 is grounded.
Table 9 describes the I/O signals. Inputs are signals sourced from the host while outputs are
signals sourced from the card. The signals are described for each of the three operating
modes.
All outputs from the card are totem pole except the data bus signals that are bi-directional
tri-state. Refer to Section 4.2: Electrical specification for definitions of Input and Output type.
Table 8.
Pin assignment and pin type
PC card memory mode
PC card I/O mode
True IDE mode
Pin
num
Signal
Pin
In, Out
Signal
Pin
In, Out
Signal
Pin
In, Out
name
type
type
name
type
type
name
type
type
Ground
GND
Ground
GND
1
GND
Ground
2
D03
I/O
I1Z,OZ3
D03
I/O
I1Z,OZ3
D03
I/O
I1Z,OZ3
3
D04
I/O
I1Z,OZ3
D04
I/O
I1Z,OZ3
D04
I/O
I1Z,OZ3
4
D05
I/O
I1Z,OZ3
D05
I/O
I1Z,OZ3
D05
I/O
I1Z,OZ3
5
D06
I/O
I1Z,OZ3
D06
I/O
I1Z,OZ3
D06
I/O
I1Z,OZ3
6
D07
I/O
I1Z,OZ3
D07
I/O
I1Z,OZ3
D07
I/O
I1Z,OZ3
7
–CE1
I
I3U
–CE1
I
I3U
–CS0
I
I3Z
8
A10
I
I1Z
A10
I
I1Z
A10(1)
I
I1Z
9
–OE
I
I3U
–OE
I
I3U
–ATASEL
I
I3U
I1Z
A09(1)
I
I1Z
I
I1Z
I
I1Z
10
A09
I
I1Z
A09
I
11
A08
I
I1Z
A08
I
I1Z
A08(1)
12
A07
I
I1Z
A07
I
I1Z
A07(1)
13
VCC
Power
VCC
Power
VCC
I1Z
A06(1)
I
I1Z
14
A06
I
I1Z
A06
I
Power
15
A05
I
I1Z
A05
I
I1Z
A05(1)
I
I1Z
16
A04
I
I1Z
A04
I
I1Z
A04(1)
I
I1Z
I
I1Z
17
A03
I
I1Z
A03
I
I1Z
A03(1)
18
A02
I
I1Z
A02
I
I1Z
A02
I
I1Z
19
A01
I
I1Z
A01
I
I1Z
A01
I
I1Z
14/82
SMCxxxAF
Table 8.
Electrical interface
Pin assignment and pin type (continued)
PC card memory mode
PC card I/O mode
True IDE mode
Pin
Signal
Pin
In, Out
Signal
Pin
In, Out
Signal
Pin
In, Out
name
type
type
name
type
type
name
type
type
20
A00
I
I1Z
A00
I
I1Z
A00
I
I1Z
21
D00
I/O
I1Z,OZ3
D00
I/O
I1Z,OZ3
D00
I/O
I1Z,OZ3
22
D01
I/O
I1Z,OZ3
D01
I/O
I1Z,OZ3
D01
I/O
I1Z,OZ3
23
D02
I/O
I1Z,OZ3
D02
I/O
I1Z,OZ3
D02
I/O
I1Z,OZ3
24
WP
O
OT3
–IOIS16
O
OT3
–IOIS16
O
ON3
25
–CD2
O
Ground
–CD2
O
Ground
–CD2
O
Ground
num
26
–CD1
O
Ground
–CD1
O
Ground
–CD1
O
Ground
27
D11(2)
I/O
I1Z,OZ3
D11(2)
I/O
I1Z,OZ3
D11(2)
I/O
I1Z,OZ3
28
D12(2)
I/O
I1Z,OZ3
D12(2)
I/O
I1Z,OZ3
D12(2)
I/O
I1Z,OZ3
29
D13(2)
I1Z,OZ3
D13(2)
I1Z,OZ3
D13(2)
I/O
I1Z,OZ3
30
D14(2)
I/O
I1Z,OZ3
D14(2)
I/O
I1Z,OZ3
D14(2)
I/O
I1Z,OZ3
31
D15(2)
I/O
I1Z,OZ3
D15(2)
I/O
I1Z,OZ3
D15(2)
I/O
I1Z,OZ3
32
–CE2(2)
I
I3U
–CE2(2)
I
I3U
–CS1(2)
I
I3Z
33
–VS1
O
Ground
–VS1
O
Ground
–VS1
O
Ground
I/O
I/O
34
–IORD
I
I3U
–IORD
I
I3U
–IORD
I
I3Z
35
–IOWR
I
I3U
–IOWR
I
I3U
–IOWR
I
I3Z
36
–WE
I
I3U
–WE
I
I3U
–WE(3)
I
I3U
37
READY
O
OT1
IREQ
O
OT1
INTRQ
O
OZ1
38
VCC
Power
VCC
Power
VCC
39
–CSEL(2)(4)
I
I2Z
–CSEL
I
I2Z
–CSEL
I
I2U
40
–VS2
O
OPEN
–VS2
O
OPEN
–VS2
O
OPEN
41
RESET
I
I2Z
RESET
I
I2Z
-RESET
I
I2Z
42
–WAIT
O
OT1
–WAIT
O
OT1
IORDY
O
ON1
Power
43
–INPACK
O
OT1
–INPACK
O
OT1
RFU
O
OZ1
44
–REG
I
I3U
–REG
I
I3U
RFU(5)
I
I3U
45
BVD2
I/O
I1U,OT1
–SPKR
I/O
I1U,OT1
–DASP
I/O
I1U,ON1
46
BVD1
I/O
I1U,OT1
–STSCHG
I/O
I1U,OT1
–PDIAG
I/O
I1U,ON1
47
D08(2)
I1Z,OZ3
D08(2)
I1Z,OZ3
D08(2)
I/O
I1Z,OZ3
48
D09(2)
I/O
I1Z,OZ3
D09
(2)
I/O
I1Z,OZ3
(2)
D09
I/O
I1Z,OZ3
49
D10(2)
I/O
I1Z,OZ3
D10(2)
I/O
I1Z,OZ3
D10(2)
I/O
I1Z,OZ3
50
GND
Ground
GND
Ground
GND
I/O
I/O
Ground
1. The signal should be grounded by the host.
2. These signals are required only for 16 bit accesses and not required when installed in 8 bit systems. Devices should allow
for 3-state signals not to consume current.
3. The signal should be tied to VCC by the host.
4. The -CSEL signal is ignored by the card in PC Card modes. However, because it is not pulled up on the card in these
modes it should not be left floating by the host in PC Card modes. In these modes, the pin is normally connected by the
host to PC Card A25 or grounded by the host.
5. The signal should be held High or tied to VCC by the host and RFU is Reserved for Future Use.
15/82
Electrical interface
Table 9.
SMCxxxAF
Signal description
Signal name
Direction
Pin
A10 to A0
(PC card memory mode)
A10 to A0
(PC card I/O mode)
I
8,10,11,12,
14,15,16,17,
18,19,20
Description
Used (with –REG) to select: the I/O Port Address
registers, the memory mapped Port Address registers, a
byte in the card's information structure and its
Configuration Control and Status registers.
Same as PC card memory mode.
A2 to A0
(True IDE mode)
Only A2 to A0 are used to select the one of eight registers
in the task file, the remaining lines should be grounded.
BVD1
(PC card memory mode)
The battery voltage status of the card, as no battery is
required it is asserted High.
–STSCHG
(PC card I/O mode)
I/O
46
Alerts the host to changes in the READY and Write
Protect states. Its use is controlled by the Card
Configuration and Status register.
–PDIAG
(True IDE mode)
The Pass Diagnostic signal in the master/slave handshake
protocol.
BVD2
(PC card memory mode)
The battery voltage status of the card, as no battery is
required it is asserted High.
–SPKR
(PC card I/O mode)
I/O
45
The binary audio output from the card. It is asserted High
as audio functions are not supported.
–DASP
(True IDE mode)
This input/output is the disk active/slave present signal in
the master/slave handshake protocol.
D15-D00
(PC card memory mode)
Carry the data, commands and status information
between the host and the controller. D00 is the LSB of the
even byte of the word. D08 is the LSB of the odd byte of
the word.
D15-D00
(PC card I/O mode)
I/O
31,30,29,28,
27,49,48,47,
6,5,4,3,2,
23,22,21
Same as PC card memory mode.
D15-D00
(True IDE mode)
All task file operations occur in byte mode on D00 to D07
while all data transfers are 16 bit using D00 to D15.
GND
(PC card memory mode)
Ground.
GND
(PC card I/O mode)
1,50
Same for all modes.
GND
(True IDE mode)
Same for all modes.
–INPACK
(PC card memory mode)
Not used, should not be connected to the host.
–INPACK
(PC card I/O mode)
The Input Acknowledge is asserted when the Card is
selected and responding to an I/O read cycle at the
current address on the bus. It is used by the host to control
the enable of any input data buffers between the Card and
CPU.
Reserved
(True IDE mode)
16/82
O
43
Not used, should not be connected to the host.
SMCxxxAF
Table 9.
Electrical interface
Signal description (continued)
Signal name
Direction
Pin
–IORD
(PC card memory mode)
–IORD
(PC card I/O mode)
Description
Not used.
I
34
I/O Read strobe generated by the host. It gates I/O data
onto the bus.
–IORD
(True IDE mode)
Same as PC card I/O mode.
–CD1, –CD2
(PC card memory mode)
These are connected to ground on the card. They are
used by the host to determine that the card is fully inserted
into its socket.
–CD1, –CD2
(PC card I/O mode)
O
26,25
Same for all modes.
–CD1, –CD2
(True IDE mode)
Same for all modes.
–CE1, –CE2
(PC card memory mode)
Used to select the card and to indicate whether a byte or a
word operation is being performed. –CE2 accesses the
odd byte, –CE1 accesses the even byte or the odd byte
depending on A0 and –CE2. A multiplexing scheme based
on A0, –CE1, –CE2 allows 8 bit hosts to access all data on
D0 to D7.
I
7,32
–CE1, –CE2
(PC card I/O mode)
Same as PC card memory mode.
–CS0, –CS1
(True IDE mode)
CS0 is the chip select for the task file registers, while CS1
selects the Alternate Status register and the Device
Control register.
–CSEL
(PC card memory mode)
Not used.
–CSEL
(PC card I/O mode)
I
39
Not used.
–CSEL
(True IDE mode)
This internally pulled up signal is used to configure the
card as a master or slave. When grounded it is configured
as a master, when open it is configured as a slave.
–IOWR
(PC card memory mode)
Not used.
–IOWR
(PC card I/O mode)
I
35
The I/O Write strobe pulse is used to clock I/O data on the
bus into the Card Controller registers. Clocking occurs on
the rising edge.
–IOWR
(True IDE mode)
Same as PC card I/O mode.
–OE
(PC card memory mode)
This is an Output Enable strobe generated by the host
interface. It reads data and the CIS and Configuration
registers.
–OE
(PC card I/O mode)
–ATASEL
(True IDE mode)
I
9
Reads the CIS and Configuration registers.
Grounded by the host.
17/82
Electrical interface
Table 9.
SMCxxxAF
Signal description (continued)
Signal name
Direction
Pin
READY
(PC card memory mode)
O
37
Description
Indicates whether the card is busy (Low), or ready to
accept a new data transfer operation (High). The Host
socket must provide a pull-up resistor. At power-up and
reset, the READY signal is held Low until the commands
are completed. No access should be made during this
time. The READY signal is held High whenever the card
has been powered up with RESET continuously
disconnected or asserted.
–IREQ
(PC card I/O mode)
Interrupt request. It is strobed Low to generate a pulse
mode interrupt or held Low for a level mode interrupt.
INTRQ
(True IDE mode)
Active High Interrupt request to the host.
–REG
(PC card memory mode)
Used to distinguish between common memory and
register (attribute) memory accesses. High for common
memory, Low for attribute memory.
–REG
(PC card I/O mode)
I
44
Must be Low during I/O cycles when the I/O address is on
the bus.
Reserved
(True IDE mode)
Not used, should be connected to VCC by the host.
RESET
(PC card memory mode)
Resets the card (active High). The card is reset at powerup only if this pin is left High or unconnected.
RESET
(PC card I/O mode)
I
41
Same as PC card memory mode.
–RESET
(True IDE mode)
Hardware Reset from the host (active Low).
VCC
(PC card memory mode)
+5 V, +3.3 V power.
VCC
(PC card I/O mode)
13,38
Same for all modes.
VCC
(True IDE mode)
Same for all modes.
–VS1, –VS2
(PC card memory mode)
Voltage sense signals.–VS1 is grounded so that the CIS
can be read at 3.3 volts and –VS2 is reserved by PCMCIA
for a secondary voltage.
–VS1, –VS2
(PC card I/O mode)
O
33,40
–VS1, –VS2
(True IDE mode)
Same for all modes.
Same for all modes.
–WAIT
(PC card memory mode)
–WAIT
(PC card I/O mode)
IORDY
(True IDE mode)
18/82
O
42
ST CF does not assert the WAIT (IORDY) signal.
SMCxxxAF
Table 9.
Electrical interface
Signal description (continued)
Signal name
Direction
Pin
–WE
(PC card memory mode)
–WE
(PC card I/O mode)
Description
Driven by the host to strobe memory write data to the
registers.
I
36
Used for writing to the configuration registers.
–WE
(True IDE mode)
Not used, should be connected to VCC by the host.
WP
(PC card memory mode)
No write protect switch available. It is held Low after the
completion of the reset initialization sequence.
–IOIS16
(PC card I/O mode)
–IOCS16
(True IDE mode)
O
24
Used for the 16 bit port (–IOIS16) function. Low indicates
that a 16 bit or odd byte only operation can be performed
at the addressed port.
Asserted Low when the card is expecting a word data
transfer cycle.
19/82
Electrical interface
4.2
SMCxxxAF
Electrical specification
Table 10 defines the DC characteristics for the CompactFlash memory card. Unless
otherwise stated, conditions are:
●
VCC = 5 V ± 10%
●
VCC = 3.3 V ± 10%
●
-40 °C to 85 °C
Table 11 shows that the card operates correctly in both the voltage ranges and that the
current requirements must not exceed the maximum limit shown.
Table 10.
Absolute maximum conditions
Parameter
Symbol
Conditions
Input power
VCC
–0.3 V to 6.5 V
Voltage on any pin except VCC with respect to GND
V
–0.5 V to VCC + 0.5 V
Table 11.
Input power
Voltage
Maximum average RMS current
Measurement conditions
3.3 V ± 10%
79 mA
-40 + 85 °C
5 V ± 10%
82 mA
-40 + 85 °C
4.3
Current measurement
The current is measured by connecting an amp meter in series with the VCC supply. The
meter should be set to the 2 A scale range, and have a fast current probe with an RC filter
with a time constant of 0.1 ms. Current measurements are taken while looping on a data
transfer command with a sector count of 128. Current consumption values for both read and
write commands are not to exceed the maximum average RMS current specified in
Table 11. Table 12 shows the Input leakage current, Table 13 the Input characteristics,
Table 14 the Output drive type and Table 15 the Output drive characteristics.
Table 12.
Input leakage current(1)
Type
Parameter
Symbol
IxZ
Input leakage current
IL
Conditions
VIH = VCC
Min
Typ
Max
Units
–1
1
µA
VIL = GND
IxU
Pull up resistor
RPU1
VCC = 5.0 V
50
500
kW
IxD
Pull down resistor
RPD1
VCC = 5.0 V
50
500
kW
1. x refers to the characteristics described in Table 13. For example, I1U indicates a pull up resistor with a type 1 input
characteristic.
20/82
SMCxxxAF
Table 13.
Electrical interface
Input characteristics
Min
Type
Parameter
Typ
Max
Min
2
3
Table 14.
Max
Units
VCC = 3.3 V
1
Typ
Symbol
VCC = 5.0 V
Input voltage
CMOS
VIH
Input voltage
CMOS
VIH
Input voltage CMOS
Schmitt Trigger
VTH
1.8
2.8
VTL
1.0
2.0
2.4
2.4
V
0.6
VIL
1.5
0.8
2.0
V
0.6
VIL
0.8
V
Output drive type(1)
Type
Output type
Valid conditions
OTx
Totem pole
IOH & IOL
OZx
Tri-state N-P channel
IOH & IOL
OPx
P-channel only
IOH only
ONx
N-channel only
IOL only
1. x refers to the characteristics described in Table 15. For example, OT3 refers to totem pole output with a type 3 output
drive characteristic.
Table 15.
Output drive characteristics
Type
Parameter
1
Output voltage
2
3
X
Output voltage
Output voltage
Tri-state
leakage current
Symbol
Conditions
Min
VOH
IOH = –4 mA
VCC – 0.8 V
VOL
IOL = 4 mA
VOH
IOH = –8 mA
VOL
IOL = 8 mA
VOH
IOH = –8 mA
VOL
IOL = 8 mA
IOZ
VOL = Gnd
Typ
Max
Units
V
Gnd + 0.4 V
VCC – 0.8 V
V
Gnd + 0.4 V
VCC – 0.8 V
V
Gnd + 0.4 V
–10
10
µA
VOH = VCC
21/82
Command interface
5
SMCxxxAF
Command interface
There are two types of bus cycles and timing sequences that occur in the PCMCIA type
interface, direct mapped I/O transfer and memory access. Table 16, Table 17, Table 18,
Table 19, Table 20, Table 21 and Table 22 show the read and write timing parameters.
Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7 and Figure 8 show the read and
write timing diagrams.
Note, the wait width time is intentionally less than the PCMCIA specification of 12 µs. Its
maximum value can be determined from the card information structure.
Figure 2.
Attribute memory Read timing diagram
tc(R)
Address Inputs
VALID
ta(A)
tv(A)
–REG
tsu(A)
ta(CE)
–CE2/–CE1
tdis(CE)
ta(OE)
ten(CE)
–OE
tdis(OE)
ten(OE)
D0 to D15 (DOUT)
VALID
AI10080
1. DOUT signifies data provided by the CompactFlash memory card to the system. The -CE signal or both the -OE signal and
the -WE signal must be de-asserted between consecutive cycle operations.
Table 16.
Attribute memory Read timing
Speed version
Symbol
IEEE symbol
300 ns
Parameter
Min
Max
tc(R)
tAVAV
Read Cycle time
ta(A)
tAVQV
Address Access time
300
ns
ta(CE)
tELQV
CE Access time
300
ns
ta(OE)
tGLQV
OE Access time
150
ns
tdis(CE)
tEHQZ
Output Disable time from CE
100
ns
tdis(OE)
tGHQZ
Output Disable time from OE
100
ns
ten(CE)
tELQNZ
Output Enable time from CE
5
ns
ten(OE)
tGLQNZ
Output Enable time from OE
5
ns
tv(A)
tAXQX
Data Valid from Address Change
0
ns
tsu(A)
tAVGL
Address Setup time
30
ns
22/82
300
Unit
ns
SMCxxxAF
Command interface
Figure 3.
Configuration register (attribute memory) Write timing diagram
tc(W)
–REG
VALID
Address Inputs
tsu(A)
tw(WE)
trec(WE)
–WE
tsu(D-WEH)
th(D)
–CE2/–CE1
–OE
D0 to D15 (DIN)
DATA IN VALID
AI10081
1. DIN signifies data provided by the system to the CompactFlash card.
Table 17.
Configuration register (attribute memory) Write timing
Speed version
Symbol
IEEE symbol
250 ns
Parameter
Min
Max
Unit
tc(W)
tAVAV
Write Cycle time
250
ns
tw(WE)
tWLWH
Write Pulse width
150
ns
tsu(A)
tAVWL
Address Setup time
30
ns
tsu(D-WEH)
tDVWH
Data Setup time from WE
80
ns
th(D)
tWMDX
Data Hold time
30
ns
trec(WE)
tWMAX
Write Recovery time
30
ns
23/82
Command interface
Figure 4.
SMCxxxAF
Common memory Read timing diagram
Address Inputs
VALID
tsu(A)
th(A)
–REG
th(CE)
–CE2/–CE1
tsu(CE)
ta(OE)
–OE
tdis(OE)
tv(WT)
D0 to D15 (DOUT)
VALID
AI10083b
1. DOUT means data provided by the CompactFlash memory card to the system.
Table 18.
Common memory Read timing(1)
Cycle time mode
Symbol
IEEE symbol
250 ns
Parameter
Min
Max
Unit
ta(OE)
tGLQV
Output Enable Access time
125
ns
tdis(OE)
tGHQZ
Output Disable time from OE
100
ns
tsu(A)
tAVGL
Address Setup time
30
ns
th(A)
tGHAX
Address Hold time
20
ns
tsu(CE)
tELGL
CE Setup time
0
ns
th(CE)
tGHEH
CE Hold time
20
ns
1. ST CF does not assert the WAIT signal.
24/82
SMCxxxAF
Figure 5.
Command interface
Common memory Write timing diagram
Address Inputs
VALID
tsu(A)
th(A)
–REG
tsu(CE)
trec(WE)
–CE2/–CE1
th(CE)
tw(WE)
–WE
tsu(D-WEH)
D0 to D15 (DIN)
th(D)
DATA IN VALID
AI10082b
1. DIN signifies data provided by the system to the CompactFlash memory card.
Table 19.
Common memory Write timing(1)
Cycle time mode
Symbol
IEEE symbol
250 ns
Parameter
Min
Max
Unit
tsu(D-WEH)
tDVWH
Data setup time from WE
80
ns
th(D)
tWMDX
Data hold time
30
ns
tw(WE)
tWLWH
WE pulse width
150
ns
tsu(A)
tAVGL
Address setup time
30
ns
tsu(CE)
tELWL
CE setup time before WE
0
ns
trec(WE)
tWMAX
Write recovery time
30
ns
th(A)
tGHAX
Address hold time
20
ns
th(CE)
tGHEH
CE hold following WE
20
ns
1. ST CF does not assert the WAIT signal.
25/82
Command interface
Figure 6.
SMCxxxAF
I/O Read timing diagram
Address Inputs
VALID
tsuREG(IORD)
thA(IORD)
–REG
thREG(IORD)
tsuCE(IORD)
–CE2/–CE1
tsuA(IORD)
tw(IORD)
thCE(IORD)
–IORD
td(IORD)
tdrINPACK(IORD)
–INPACK
tdfINPACK(IORD)
tdfIOIS16(ADR)
tdrIOIS16(ADR)
–IOIS16
th(IORD)
D0 to D15
VALID
AI10084b
1. DOUT signifies data provided by the CompactFlash memory card or to the system.
Table 20.
I/O Read timing(1)
Cycle time mode
Symbol
IEEE symbol
250 ns
Parameter
td(IORD)
tIGLQV
Data Delay after IORD
th(IORD)
tIGHQX
Data Hold following IORD
tw(IORD)
tIGLIGH
tsuA(IORD)
Min
Max
Unit
100
ns
0
ns
IORD Width time
165
ns
tAVIGL
Address Setup before IORD
70
ns
thA(IORD)
tIGHAX
Address Hold following IORD
20
ns
tsuCE(IORD)
tELIGL
CE Setup before IORD
5
ns
thCE(IORD)
tIGHEH
CE Hold following IORD
20
ns
tsuREG(IORD)
tRGLIGL
REG Setup before IORD
5
ns
thREG(IORD)
tIGHRGH
REG Hold following IORD
0
ns
tdfINPACK(IORD)
tIGLIAL
INPACK Delay Falling from IORD
0
tdrINPACK(IORD)
tIGHIAH
tdfIOIS16(A)
tdrIOIS16(A)
45
ns
INPACK Delay Rising from IORD
45
ns
tAVISL
IOIS16 Delay Falling from Address
35
ns
tAVISH
IOIS16 Delay Rising from Address
35
ns
1. ST CF does not assert the WAIT signal.
26/82
SMCxxxAF
Figure 7.
Command interface
I/O Write timing diagram
Address Inputs
VALID
tsuREG(IOWR)
thA(IOWR)
thREG(IOWR)
–REG
tsuCE(IOWR)
thCE(IOWR)
–CE2/–CE1
tsuA(IOWR)
tw(IOWR)
–IOWR
tdfIOIS16(ADR)
tdrIOIS16(ADR)
–IOIS16
tsu(IOWR)
D0 to D15 (DIN)
th(IOWR)
DIN VALID
AI10085b
1. DIN signifies data provided by the system to the CompactFlash memory card or CF+ card.
Table 21.
I/O Write timing(1)
Cycle time mode
Symbol
IEEE symbol
250 ns
Parameter
Min
Max
Unit
tsu(IOWR)
tQVIWH
Data Setup before IOWR
60
ns
th(IOWR)
tIWHQX
Data Hold following IOWR
30
ns
tw(IOWR)
tIWLIWH
IOWR Width time
165
ns
tsuA(IOWR)
tAVIWL
Address Setup before IOWR
70
ns
thA(IOWR)
tIWHAX
Address Hold following IOWR
20
ns
tsuCE(IOWR)
tELIWL
CE Setup before IOWR
5
ns
thCE(IOWR)
tIWHEH
CE Hold following IOWR
20
ns
tsuREG(IOWR)
tRGLIWL
REG Setup before IOWR
5
ns
thREG(IOWR)
tIWHRGH
REG Hold following IOWR
0
ns
tdfIOIS16(A)
tAVISL
IOIS16 Delay Falling from Address
35
ns
tdrIOIS16(A)
tAVISH
IOIS16 Delay Rising from Address
35
ns
1. ST CF does not assert the WAIT signal.
27/82
Command interface
SMCxxxAF
The timing diagram for True IDE mode of operation in this section is drawn using the
conventions in the ATA-4 specification, which are different than the conventions used in the
PCMCIA specification and earlier versions of this specification. Signals are shown with their
asserted state as High regardless of whether the signal is actually negative or positive true.
Consequently, the -IORD, the -IOWR and the -IOCS16 signals are shown in the diagram
inverted from their electrical states on the bus.
Figure 8.
True IDE mode I/O timing diagram
t0
A0-A2, −CS0,
−CS1(1)
ADDRESS VALID
t1
t2
t9
t8
−IORD/−IOWR
t2i
Write Data D0-D15(2)
VALID
t3
t4
VALID
Read Data D0-D15(2)
t5
t7
t6
t6z
−IOCS16(3)
ai10086b
1. The device addresses consists of −CS0, −CS1, and A2-A0.
2. The Data I/O consist of D15-D0 (16 bit) or D7-D0 (8 bit).
3. −IOCS16 is shown for PIO modes 0, 1 and 2. For other modes, this signal is ignored.
28/82
SMCxxxAF
Table 22.
Symbol
Command interface
True IDE mode I/O Read/Write timing diagram
Parameter(1)
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Unit
Cycle time (min)
600
383
240
180
120
ns
Address Valid to -IORD/-IOWR
setup (min)
70
50
30
30
25
ns
t2(2)
-IORD/-IOWR (min)
165
125
100
80
70
ns
t2(2)
-IORD/-IOWR (min) register (8
bit)
290
290
290
80
70
ns
t2i(2)
-IORD/-IOWR recovery time (min)
-
-
-
70
25
ns
t0(2)
t1
t3
-IOWR data setup (min)
60
45
30
30
20
ns
t4
-IOWR data hold (min)
30
20
15
10
10
ns
t5
-IORD data setup (min)
50
35
20
20
20
ns
t6
-IORD data hold (min)
5
5
5
5
5
ns
t6Z(3)
-IORD data tri-state (max)
30
30
30
30
30
ns
t7(4)
Address valid to -IOCS16
assertion (max)
90
50
40
N/A
N/A
ns
t8(4)
Address valid to -IOCS16
released (max)
60
45
30
N/A
N/A
ns
-IORD/-IOWR to address valid
hold
20
15
10
10
10
ns
t9
1. The maximum load on -IOCS16 is 1 LSTTL with a 50 pF total load.
2. t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recovery time
or command inactive time. The actual cycle time equals the sum of the actual command active time and the actual
command inactive time. The three timing requirements of t0, t2, and t2i have to be met. The minimum total cycle time
requirement is greater than the sum of t2 and t2i. This means a host implementation can lengthen either or both t2 or t2i to
ensure that t0 is equal to or greater than the value reported in the device's identify drive data. A CompactFlash memory
card implementation should support any legal host implementation.
3. This parameter specifies the time from the falling edge of -IORD to the moment when the data bus is no longer driven by
the CompactFlash memory card (tri-state).
4. t7 and t8 apply only to modes 0, 1 and 2. This signal is not valid for other modes.
29/82
Card configuration
6
SMCxxxAF
Card configuration
The CompactFlash memory card is identified by information in the card information structure
(CIS). The card has four Configuration registers (Table 23 and Table 24).
●
Configuration Option register
●
Pin Replacement register
●
Card Configuration and Status register
●
Socket and Copy register
They are used to coordinate the I/O spaces and the Interrupt level of cards that are located
in the system. In addition, in I/O Card mode these registers provide a method for accessing
status information that would normally appear on dedicated pins in Memory Card mode. The
location of the Card Configuration registers should always be read from the CIS.These
registers cannot be used in True IDE mode.
No writes should be performed to the attribute memory except to the Configuration register
addresses. All other attribute memory locations are reserved. See Section 6.5: Attribute
memory function.
Table 23.
CompactFlash memory card registers and memory space decoding
–CE2 –CE1 –REG –OE –WE A10 A9 A8-A4 A3 A2 A1 A0
Selected space
1
1
X
X
X
X
X
XXX
XX
X
X
X
Standby
X
0
0
0
1
0
1
XXX
XX
X
X
0
Configuration registers Read
1
0
1
0
1
X
X
XXX
XX
X
X
X
Common Memory Read (D7 to D0)
0
1
1
0
1
X
X
XXX
XX
X
X
X
Common Memory Read (D15 to D8)
0
0
1
0
1
X
X
XXX
XX
X
X
0
Common Memory Read (D15 to D0)
X
0
0
1
0
0
1
XXX
XX
X
X
0
Configuration registers Write
1
0
1
1
0
X
X
XXX
XX
X
X
X
Common Memory Write (D7 to D0)
0
1
1
1
0
X
X
XXX
XX
X
X
X
Common Memory Write (D15 to D8)
0
0
1
1
0
X
X
XXX
XX
X
X
0
Common Memory Write (D15 to D0)
X
0
0
0
1
0
0
XXX
XX
X
X
0
Card Information Structure Read
1
0
0
1
0
0
0
XXX
XX
X
X
0
Invalid Access (CIS Write)
1
0
0
0
1
X
X
XXX
XX
X
X
1
Invalid Access (Odd Attribute Read)
1
0
0
1
0
X
X
XXX
XX
X
X
1
Invalid Access (Odd Attribute Write)
0
1
0
0
1
X
X
XXX
XX
X
X
X
Invalid Access (Odd Attribute Read)
0
1
0
1
0
X
X
XXX
XX
X
X
X
Invalid Access (Odd Attribute Write)
30/82
SMCxxxAF
Table 24.
Card configuration
CompactFlash memory card configuration registers decoding
–CE2 –CE1 –REG –OE –WE A10
A9
A8A4
A3 A2 A1 A0
Selected register
X
0
0
0
1
0
1
00
0
0
0
0
Configuration Option register Read
X
0
0
1
0
0
1
00
0
0
0
0
Configuration Option register Write
X
0
0
0
1
0
1
00
0
0
1
0
Card Status register Read
X
0
0
1
0
0
1
00
0
0
1
0
Card Status register Write
X
0
0
0
1
0
1
00
0
1
0
0
Pin Replacement register Read
X
0
0
1
0
0
1
00
0
1
0
0
Pin Replacement register Write
X
0
0
0
1
0
1
00
0
1
1
0
Socket and Copy register Read
X
0
0
1
0
0
1
00
0
1
1
0
Socket and Copy register Write
6.1
Configuration Option register (base + 00h in attribute
memory)
The Configuration Option register is used to configure the card’s interface, address
decoding and interrupt to the card (see Table 25).
6.1.1
LevlREQ
This bit is set to one (1) when level mode interrupt is selected, and zero (0) when pulse
mode is selected. Set to zero (0) after power-up.
6.1.2
Conf5 - Conf0 (configuration index)
These bits are used to select the operation mode of the card as shown in Table 26. This bit
is set to ‘0’ after power-up.
Table 25.
Configuration Option register (default value: 00h)
Operation
D7
D6
D5
D4
D3
D2
D1
D0
R/W
X
LevlREQ
Conf5
Conf4
Conf3
Conf2
Conf1
Conf0
Table 26.
CompactFlash memory card configurations
Conf
5
Conf
4
Conf
3
Conf
2
Conf
1
Conf
0
Mapping
mode
Card
mode
Task file register address
0
0
0
0
0
0
Memory
Memory
0h - Fh, 400h - 7FFh
0
0
0
0
0
1
Contiguous
I/O
I/O
xx0h - xxFh
0
0
0
0
1
0
Primary I/O
I/O
1F0h - 1F7h, 3F6h - 3F7h
0
0
0
0
1
1
Secondary I/O
I/O
170h - 177h, 376h - 377h
31/82
Card configuration
6.2
SMCxxxAF
Card Configuration and Status register (base + 02h in
attribute memory)
The Card Configuration and Status register contains information about the card’s status
(see Table 27).
6.2.1
Changed
Indicates that one or both of the pin replacement register (CRDY, or CWProt) bits are set to
‘1’. When the Changed bit is set, –STSCHG (pin 46) is held Low and if the SigChg bit is ‘1’
the card is configured for the I/O interface.
6.2.2
SigChg
This bit is set and reset by the host to enable and disable a state-change signal from the
Status register (issued on Status Changed pin 46). If no state change signal is desired, this
bit should be set ‘0’ and pin 46 (–STSCHG) will be held High while the card is configured for
I/O.
6.2.3
IOis8
The host sets this bit to ‘1’ if the card is to be configured in 8 bit I/O mode. The card is
always configured for both 8 and 16 bit I/O, so this bit is ignored.
6.2.4
PwrDwn
This bit indicates whether the card is in the power saving mode or active mode. When the
PwrDwn bit is set to ‘1’, the card enters power-down mode. When set to ‘0’, the card enters
active mode. The READY value on Pin Replacement register becomes BUSY when this bit
is changed. READY will not become Ready until the power state requested has been
entered. The card automatically powers down when it is idle and powers back up when it
receives a command.
6.2.5
Int
This bit represents the internal state of the interrupt request. It is available whether or not
the I/O interface has been configured. It remains valid until the condition which caused the
interrupt request has been serviced. If interrupts are disabled by the –IEN bit in the Device
Control register, this bit is ‘0’.
Table 27.
32/82
Card Configuration and Status register (default value: 00h)
Operation
D7
D6
D5
D4
D3
D2
D1
D0
Read
Changed
SigChg
IOIS8
0
0
PwrDwn
Int
0
Write
0
SigChg
IOIS8
0
0
PwrDwn
0
0
SMCxxxAF
6.3
Card configuration
Pin Replacement register (base + 04h in attribute memory)
This register contains information on the state of the READY signal when configured in
memory mode and the IREQ signal in I/O mode. See Table 28 and Table 29.
6.3.1
CReady
This bit is set to ‘1’ when the bit RReady changes state. This bit can also be written by the
host.
6.3.2
CWProt
This bit is set to '1' when the bit RWProt changes state. This bit can also be written by the
host.
6.3.3
RReady
This bit is used to determine the internal state of the Ready signal. In I/O mode it is used as
an interrupt request. When written, this bit acts as a mask (MReady) for writing the
corresponding bit CReady.
6.3.4
WProt
This bit is always ‘0’ since the CompactFlash memory card does not have a Write Protect
switch. When written, this bit acts as a mask for writing the corresponding CWProt bit.
6.3.5
MReady
This bit acts as a mask for writing the corresponding CReady bit.
6.3.6
MWProt
This bit when written acts as a mask for writing the corresponding CWProt bit.
Table 28.
Pin Replacement register (default value: 0Ch)
Operation
D7
D6
D5
D4
D3
D2
D1
D0
Read
0
0
CReady
CWProt
1
1
RReady
WProt
Write
0
0
CReady
CWProt
0
0
RReady
MWProt
Table 29.
Pin Replacement Changed bit/Mask bit values
Initial value of
‘C’ status
Written by host
Final ‘C’ bit
Comments
0
0
Unchanged
X
0
1
Unchanged
X
0
1
0
Cleared by host
X
1
1
1
Set by host
‘C’ bit
‘M’ bit
0
X
1
33/82
Card configuration
6.4
SMCxxxAF
Socket and Copy register (base + 06h in attribute memory)
This register contains additional configuration information which identifies the card from
other cards. This register is always written by the system before writing the Configuration
Option register (see Table 30).
6.4.1
Drive #
This value can be used to address two different cards in the case of twin card configuration.
6.4.2
X
The socket number is ignored by the card.
Table 30.
34/82
Socket and Copy register (default value: 00h)
Operation
D7
D6
D5
D4
D3
D2
D1
D0
Read
Reserved
0
0
Drive #
0
0
0
0
Write
0
0
0
Drive #
X
X
X
X
SMCxxxAF
6.5
Card configuration
Attribute memory function
Attribute memory is a space where identification and configuration information are stored,
and is limited to 8 bit wide accesses at even addresses. The Card Configuration registers
are also located here, the base address of the configuration registers is 200h.
For the attribute memory Read function, signals –REG and –OE must be active and –WE
inactive during the cycle. As in the main memory read functions, the signals –CE1 and –CE2
control the even and odd byte address, but only the even byte data is valid during the
attribute memory access. Refer to Table 31 for signal states and bus validity.
Table 31.
Attribute memory function(1)
Function mode
–REG –CE2
–CE1
A10
A9
A0
–OE
–WE
D15 to D8
D7 to D0
Standby
X
H
H
X
X
X
X
X
High-Z
High-Z
Read Byte Access CIS
(8 bits)
L
H
L
L
L
L
L
H
High-Z
Even byte
Write Byte Access CIS
(8 bits) Invalid
L
H
L
L
L
L
H
L
Don’t care
Even byte
Read Byte Access
Configuration
(8 bits)
L
H
L
L
H
L
L
H
High-Z
Even byte
Write Byte Access
Configuration
(8 bits)
L
H
L
L
H
L
H
L
Don’t care
Even byte
Read Byte Access
Configuration CF+ (8
bits)
L
H
L
X
X
L
L
H
High-Z
Even byte
Read Word Access CIS
(16 bits)
L
L
L
L
L
X
L
H
Not valid
Even byte
Write Word Access CIS
(16 bits) Invalid
L
L
L
L
L
X
H
L
Don’t care
Even byte
Read Word Access
Configuration (16 bits)
L
L
L
L
H
X
L
H
Not valid
Even byte
Write Word Access
Configuration (16 bits)
L
L
L
L
H
X
H
L
Don’t care
Even byte
1. The –CE signal or both the –OE signal and the –WE signal must be de-asserted between consecutive cycle operations.
35/82
Card configuration
6.6
SMCxxxAF
I/O transfer function
The I/O transfer to or from the card can be either 8 or 16 bits. When a 16 bit accessible port
is addressed, the –IOIS16 signal is asserted by the card, otherwise it is de-asserted. When
a 16 bit transfer is attempted, and the –IOIS16 signal is not asserted, the system must
generate a pair of 8 bit references to access the word’s even and odd bytes. The card
permits both 8 and 16 bit accesses to all of its I/O addresses, so –IOIS16 is asserted for all
addresses (see Table 32).
Table 32.
I/O function
Function code
–REG
–CE2
–CE1
A0
–IORD
–IOWR
D15 to D8
D7 to D0
Standby mode
X
H
H
X
X
X
High Z
High Z
Byte input access
(8 bits)
L
L
H
H
L
L
L
H
L
L
H
H
High Z
High Z
Even byte
Odd byte
Byte output access
(8 bits)
L
L
H
H
L
L
L
H
H
H
L
L
Don’t care
Don’t care
Even byte
Odd byte
Word input access
(16 bits)
L
L
L
L
L
H
Odd byte
Even byte
Word output access
(16 bits)
L
L
L
L
H
L
Odd byte
Even byte
I/O Read Inhibit
H
X
X
X
L
H
Don’t care
Don’t care
I/O Write inhibit
H
X
X
X
H
L
High Z
High Z
High byte input only
(8 bits)
L
L
H
X
L
H
Odd byte
High Z
High byte output only
(8 bits)
L
L
H
X
H
L
Odd byte
Don’t care
36/82
SMCxxxAF
6.7
Card configuration
Common memory transfer function
The common memory transfer to or from the card permits both 8 or 16 bit access to all of the
common memory addresses. (see Table 33).
Table 33.
Common memory function
Function code
–REG
–CE2
–CE1
A0
–OE
–WE
D15 to D8
D7 to D0
Standby mode
X
H
H
X
X
X
High Z
High Z
Byte Read access
(8 bits)
H
H
H
H
L
L
L
H
L
L
H
H
High Z
High Z
Even byte
Odd byte
Byte Write access
(8 bits)
H
H
H
H
L
L
L
H
H
H
L
L
Don’t care
Don’t care
Even byte
Odd byte
Word Read access
(16 bits)
H
L
L
X
L
H
Odd byte
Even byte
Word Write access
(16 bits)
H
L
L
X
H
L
Odd byte
Even byte
Odd byte read only
(8 bits)
H
L
H
X
L
H
Odd byte
High Z
Odd byte write only
(8 bits)
H
L
H
X
H
L
Odd byte
Don’t care
37/82
Card configuration
6.8
SMCxxxAF
True IDE mode I/O function
The card can be configured in a True IDE mode of operation. It is configured in this mode
only when the –OE signal is grounded by the host during the power-off to power-on cycle. In
this True IDE mode the PCMCIA protocol and configuration are disabled and only I/O
operations to the task file and data register are allowed. No memory or attribute registers
are accessible to the host. The Set Feature command can be used to put the device in 8 bit
mode (see Table 34).
Removing and reinserting the card while the host computer’s power is on will reconfigure
the card to PC Card ATA mode.
Table 34.
True IDE mode I/O function
Function code
–CE2
–CE1
A2 to A0
–IORD
–IOWR
D15 to D8
D7 to D0
Invalid mode
L
L
X
X
X
High Z
High Z
Standby mode
H
H
X
X
X
High Z
High Z
Task File Write
H
L
1h-7h
H
L
Don’t care
Data In
Task File Read
H
L
1h-7h
L
H
High Z
Data Out
Data Register Write
H
L
L
H
L
Odd-byte In
Even-byte In
Data Register Read
H
L
L
L
H
Odd-byte Out
Even-byte Out
Control Register Write
L
H
6h
H
L
Don’t care
Control In
Alternate Status Read
L
H
6h
L
H
High Z
Status Out
Drive Address
L
H
7h
L
H
High Z
Data Out
38/82
SMCxxxAF
Software interface
7
Software interface
7.1
CF-ATA Drive register set definition and protocol
The CompactFlash memory card can be configured as a high performance I/O device
through:
●
Standard PC-AT disk I/O address spaces
–
1F0h-1F7h, 3F6h-3F7h (primary);
–
170h-177h, 376h-377h (secondary) with IRQ 14 (or other available IRQ).
●
Any system decoded 16 byte I/O block using any available IRQ.
●
Memory space.
Communication to or from the card is done using the Task File registers which provide all
the necessary registers for control and status information. The PCMCIA interface connects
peripherals to the host using four-register mapping methods. Table 35 is a detailed
description of these methods:
Table 35.
I/O configurations
Standards configurations
7.2
Config index
I/O or memory
Address
Description
0
Memory
0h-Fh, 400h-7FFh
Memory mapped
1
I/O
xx0h-xxFh
I/O mapped 16 continuous registers
2
I/O
1F0-1F7h, 3F6h-3F7h
Primary I/O mapped
3
I/O
170-177h, 376h-377h
Secondary I/O mapped
Memory mapped addressing (conf = 0)
When the card registers are accessed via memory references, the registers appear in the
common memory space window: 0-2 Kbytes as shown in Table 36. This window accesses
the Data register FIFO. It does not allow random access to the data buffer within the card.
Register 0 is accessed with –CE1 and –CE2 Low, as a word register on the combined Odd
and Even Data Bus (D15 to D0). It can also be accessed with –CE1 Low and –CE2 High, by
a pair of byte accesses to offset 0. The address space of this word register overlaps the
address space of the error and feature bytewide registers at offset 1. When accessed twice
as byte register with –CE1 Low, the first byte is the even byte of the word and the second is
the odd byte. A byte access to address 0 with –CE1 High and –CE2 Low accesses the error
(read) or feature (write) register.
Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and
1. Register 8 is equivalent to register 0, while register 9 accesses the odd byte. Therefore, if
the registers are byte accessed in the order 9 then 8 the data will be transferred odd byte
then even byte. Repeated byte accesses to register 8 or 0 will access consecutive (even
then odd) bytes from the data buffer. Repeated word accesses to register 8, 9 or 0 will
access consecutive words from the data buffer, however repeated byte accesses to register
9 are not supported. Repeated alternating byte accesses to registers 8 then 9 will access
consecutive (even then odd) bytes from the data buffer.
39/82
Software interface
SMCxxxAF
Accesses to even addresses between 400h and 7FFh access register 8. Accesses to odd
addresses between 400h and 7FFh access register 9. This 1 Kbyte memory window to the
data register is provided so that hosts can perform memory-to-memory block moves to the
data register when the register lies in memory space. Some hosts, such as the X86
processors, must increment both the source and destination addresses when executing the
memory-to-memory block move instruction. Some PCMCIA socket adapters also have an
embedded auto incrementing address logic.
A word access to address at offset 8 will provide even data on the least significant byte of
the data bus, along with odd data at offset 9 on the most significant byte of the data bus.
Table 36.
Memory mapped decoding
–REG
A10
A2
A1
A0
Offset
–OE=0
–WE=0
1
0
X
0
0
0
0
0h
Even Data register
Even Data register
1
0
X
0
0
0
1
1h
Error register
Feature register
1
0
X
0
0
1
0
2h
Sector Count register
Sector Count register
1
0
X
0
0
1
1
3h
Sector Number register
Sector Number register
1
0
X
0
1
0
0
4h
Cylinder Low register
Cylinder Low register
1
0
X
0
1
0
1
5h
Cylinder High register
Cylinder High register
1
0
X
0
1
1
0
6h
Select Card/Head
register
Select card/Head register
1
0
X
0
1
1
1
7h
Status register
Command register
1
0
X
1
0
0
0
8h
Dup. Even Data register
Dup. Even Data register
1
0
X
1
0
0
1
9h
Dup. Odd Data register
Dup. Odd Data register
1
0
X
1
1
0
1
Dh
Dup. Error register
Dup. Feature register
1
0
X
1
1
1
0
Eh
Alternate Status register
Device Control register
1
0
X
1
1
1
1
Fh
Drive Address register
Reserved
1
1
X
X
X
X
0
8h
Even Data register
Even Data register
1
1
X
X
X
X
1
9h
Odd Data register
Odd Data register
40/82
A9 to A4 A3
SMCxxxAF
7.3
Software interface
Contiguous I/O mapped addressing (conf = 1)
When the system decodes a contiguous block of I/O registers to select the card, the
registers are accessed in the block of I/O space decoded by the system as shown in
Table 37.
As for the memory mapped addressing, register 0 is accessed with –CE1 Low and –CE2
Low (and A0 Don’t care) as a word register on the combined odd and even data bus (D15 to
D0). This register may also be accessed with –CE1 Low and –CE2 High, by a pair of byte
accesses to offset 0. The address space of this word register overlaps the address space of
the error and feature bytewide registers at offset 1. When accessed twice as byte register
with –CE1 Low, the first byte is the even byte of the word and the second is the odd byte. A
byte access to register 0 with –CE1 High and –CE2 Low accesses the error (read) or feature
(write) register.
Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and
1. Register 8 is equivalent to register 0, while register 9 accesses the odd byte. Therefore, if
the registers are byte accessed in the order 9 then 8 the data will be transferred odd byte
then even byte. Repeated byte accesses to register 8 or 0 will access consecutive (even
than odd) bytes from the data buffer. Repeated word accesses to register 8, 9 or 0 will
access consecutive words from the data buffer, however repeated byte accesses to register
9 are not supported. Repeated alternating byte accesses to registers 8 then 9 will access
consecutive (even then odd) bytes from the data buffer.
Table 37.
Contiguous I/O decoding
–REG
A10 to A4
A3
A2
A1
A0
Offset
–IORD=0
–IOWR=0
0
X
0
0
0
0
0h
Even Data register
Even Data register
0
X
0
0
0
1
1h
Error register
Feature register
0
X
0
0
1
0
2h
Sector Count register
Sector Count register
0
X
0
0
1
1
3h
Sector Number register
Sector Number register
0
X
0
1
0
0
4h
Cylinder Low register
Cylinder Low register
0
X
0
1
0
1
5h
Cylinder High register
Cylinder High register
0
X
0
1
1
0
6h
Select Card/Head register
Select Card/Head register
0
X
0
1
1
1
7h
Status register
Command register
0
X
1
0
0
0
8h
Dup. Even Data register
Dup. Even Data register
0
X
1
0
0
1
9h
Dup. Odd Data register
Dup. Odd Data register
0
X
1
1
0
1
Dh
Dup. Error register
Dup. Feature register
0
X
1
1
1
0
Eh
Alternate Status register
Device Control register
0
X
1
1
1
1
Fh
Drive Address register
Reserved
41/82
Software interface
7.4
SMCxxxAF
I/O primary and secondary address configurations
(conf = 2,3)
When the system decodes the primary and secondary address configurations, the registers
are accessed in the block of I/O space as shown in Table 38.
As for the memory mapped addressing, register 0 is accessed with –CE1 Low and –CE2
Low (and A0 Don’t care) as a word register on the combined odd and even data bus (D15 to
D0). This register may also be accessed with –CE1 Low and –CE2 High, by a pair of byte
accesses to offset 0. The address space of this word register overlaps the address space of
the error and feature bytewide registers at offset 1. When accessed twice as byte register
with –CE1 Low, the first byte is the even byte of the word and the second is the odd byte. A
byte access to register 0 with –CE1 High and –CE2 Low accesses the error (read) or feature
(write) register.
Table 38.
Primary and secondary I/O decoding
–REG
A9 to A4
A3
A2
A1
A0
–IORD=0
–IOWR=0
0
1F(17)h
0
0
0
0
Even Data register
Even Data register
0
1F(17)h
0
0
0
1
Error register
Feature register
0
1F(17)h
0
0
1
0
Sector Count register
Sector Count register
0
1F(17)h
0
0
1
1
Sector Number register
Sector Number register
0
1F(17)h
0
1
0
0
Cylinder Low register
Cylinder Low register
0
1F(17)h
0
1
0
1
Cylinder High register
Cylinder High register
0
1F(17)h
0
1
1
0
Select Card/Head register
Select Card/Head register
0
1F(17)h
0
1
1
1
Status register
Command register
0
3F(37)h
0
1
1
0
Alternate Status register
Device Control register
0
3F(37)h
0
1
1
1
Drive Address register
Reserved
42/82
SMCxxxAF
7.5
Software interface
True IDE mode addressing
When the card is configured in the True IDE mode, the I/O decoding is as shown in Table 39.
Table 39.
True IDE mode I/O decoding
–CE2
–CE1
A2
A1
A0
–IORD=0
–IOWR=0
1
0
0
0
0
Data register
Data register
1
0
0
0
1
Error register
Feature register
1
0
0
1
0
Sector Count register
Sector Count register
1
0
0
1
1
Sector Number register
Sector Number register
1
0
1
0
0
Cylinder Low register
Cylinder Low register
1
0
1
0
1
Cylinder High register
Cylinder High register
1
0
1
1
0
Select Card/Head register
Select Card/Head register
1
0
1
1
1
Status register
Command register
0
1
1
1
0
Alternate Status register
Device Control register
0
1
1
1
1
Drive Address
Reserved
43/82
CF-ATA registers
8
SMCxxxAF
CF-ATA registers
The following section describes the hardware registers used by the host software to issue
commands to the card. These registers are collectively referred to as the ‘task file’.
8.1
Data register (address 1F0h [170h]; offset 0, 8, 9)
The data register is a 16-bit register used to transfer data blocks between the card data
buffer and the host. This register overlaps the error register. Table 40 describes the
combinations of data register access and explains the overlapped data and error/feature
registers. Because of the overlapped registers, access to the 1F1h, 171h or offset 1 are not
defined for word (–CE2 and –CE1 set to ‘0’) operations, and are treated as accesses to the
word data register. The duplicated registers at offsets 8, 9 and Dh have no restrictions on
the operations that can be performed.
Table 40.
8.2
Data register access
Data register
–CE2
–CE1
A0
Offset
Data Bus
Word Data register
0
0
X
0, 8, 9
D15 to D0
Even Data register
1
0
0
0, 8
D7 to D0
Odd Data register
1
0
1
9
D7 to D0
Odd Data register
0
1
X
8, 9
D15 to D8
Error/Feature register
1
0
1
1, Dh
D7 to D0
Error/Feature register
0
1
X
1
D15 to D8
Error/Feature register
0
0
X
Dh
D15 to D8
Error register (address 1F1h [171h]; offset 1, 0Dh read only)
This read only register contains additional information about the source of an error when an
error is indicated in bit 0 of the status register. The bits are defined in Table 41. This register
is accessed on data bits D15 to D8 during a write operation to offset 0 with –CE2 Low and –
CE1 High.
8.2.1
Bit 7 (BBK)
This bit is set when a bad block is detected.
8.2.2
Bit 6 (UNC)
This bit is set when an uncorrectable error is encountered.
8.2.3
Bit 5
This bit is ‘0’.
44/82
SMCxxxAF
8.2.4
CF-ATA registers
Bit 4 (IDNF)
This bit is set if the requested sector ID is in error or cannot be found.
8.2.5
Bit 3
This bit is ‘0’.
8.2.6
Bit 2 (abort)
This bit is set if the command has been aborted because of a card status condition (Not
Ready, Write Fault, etc.) or when an invalid command has been issued.
8.2.7
Bit 1
This bit is ‘0’.
8.2.8
Bit 0 (AMNF)
This bit is set when there is a general error.
Table 41.
8.3
Error register
D7
D6
D5
D4
D3
D2
D1
D0
BBK
UNC
0
IDNF
0
ABRT
0
AMNF
Feature register (address 1F1h [171h]; offset 1, 0Dh write
only)
This write-only register provides information on features that the host can utilize. It is
accessed on data bits D15 to D8 during a write operation to offset 0 with –CE2 Low and –
CE1 High.
8.4
Sector Count register (address 1F2h [172h]; offset 2)
This register contains the number of sectors of data to be transferred on a read or write
operation between the host and card. If the value in this register is zero, a count of 256
sectors is specified. If the command was successful, this register is zero at completion. If
not successfully completed, the register contains the number of sectors that need to be
transferred in order to complete the request. The default value is 01h.
8.5
Sector Number (LBA 7-0) register (address 1F3h [173h];
offset 3)
This register contains the starting sector number or bits 7 to 0 of the logical block address
(LBA), for any data access for the subsequent sector transfer command.
45/82
CF-ATA registers
8.6
SMCxxxAF
Cylinder Low (LBA 15-8) register (address 1F4h [174h];
offset 4)
This register contains the least significant 8 bits of the starting cylinder address or bits 15 to
8 of the logical block address.
8.7
Cylinder High (LBA 23-16) register (address 1F5h [175h];
offset 5)
This register contains the most significant bits of the starting cylinder address or bits 23 to
16 of the logical block address.
8.8
Drive/Head (LBA 27-24) register (address 1F6h [176h]; offset
6)
The Drive/Head register is used to select the drive and head. It is also used to select LBA
addressing instead of cylinder/head/sector addressing. The bits are defined in Table 42.
8.8.1
Bit 7
This bit is set to ‘1’.
8.8.2
Bit 6 (LBA)
LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block Address mode
(LBA). When LBA is set to ‘0’, Cylinder/Head/Sector mode is selected. When LBA is set to
’1’, Logical Block Address mode is selected. In Logical Block Address mode, the logical
block address is interpreted as follows:
8.8.3
●
LBA7-LBA0: Sector Number register D7 to D0.
●
LBA15-LBA8: Cylinder Low register D7 to D0.
●
LBA23-LBA16: Cylinder High register D7 to D0.
●
LBA27-LBA24: Drive/Head register bits HS3 to HS0.
Bit 5
This bit is set to ‘1’.
8.8.4
Bit 4 (DRV)
DRV is the drive number. When DRV is ‘0’, drive/card 0 is selected (master). When DRV is
‘1’, drive/card 1 is selected (slave). The card is set to card 0 or 1 using the copy field (Drive
#) of the PCMCIA Socket & Copy configuration register.
8.8.5
Bit 3 (HS3)
When operating in the Cylinder, Head, Sector mode, this is bit 3 of the head number. It is bit
27 in the Logical Block Address mode.
46/82
SMCxxxAF
8.8.6
CF-ATA registers
Bit 2 (HS2)
When operating in the Cylinder, Head, Sector mode, this is bit 2 of the head number. It is bit
26 in the Logical Block Address mode.
8.8.7
Bit 1 (HS1)
When operating in the Cylinder, Head, Sector mode, this is bit 1 of the head number. It is bit
25 in the Logical Block Address mode.
8.8.8
Bit 0 (HS0)
When operating in the Cylinder, Head, Sector mode, this is bit 0 of the head number. It is bit
24 in the Logical Block Address mode.
Table 42.
Drive/Head register
D7
D6
D5
D4
D3
D2
D1
D0
1
LBA
1
DRV
HS3
HS2
HS1
HS0
47/82
CF-ATA registers
8.9
SMCxxxAF
Status & alternate status registers (address 1F7h [177h] &
3F6h [376h]; offsets 7 & Eh)
These registers return the card status when read by the host.
Reading the status register clears a pending interrupt. Reading the auxiliary status register
does not clear a pending interrupt.
The status register should be accessed in Byte mode; in Word mode it is recommended that
alternate status register is used. The status bits are described as follows
8.9.1
Bit 7 (BUSY)
The busy bit is set when only the card can access the command register and buffer. The
host is denied access. No other bits in this register are valid when this bit is set to ‘1’.
8.9.2
Bit 6 (RDY)
This bit indicates whether the device is capable of performing CompactFlash memory card
operations. This bit is cleared at power-up and remains cleared until the card is ready to
accept a command.
8.9.3
Bit 5 (DWF)
When set this bit indicates a write fault has occurred.
8.9.4
Bit 4 (DSC)
This bit is set when the card is ready.
8.9.5
Bit 3 (DRQ)
The data request is set when the card requires information be transferred either to or from
the host through the data register. The bit is cleared by the next command.
8.9.6
Bit 2 (CORR)
This bit is set when a correctable data error has been encountered and the data has been
corrected. This condition does not terminate a multi-sector read operation.
8.9.7
Bit 1 (IDX)
This bit is always set to ‘0’.
8.9.8
Bit 0 (ERR)
This bit is set when the previous command has ended in some type of error. The bits in the
error register contain additional information describing the error. In case of read or write
access commands that end with an error, the address of the first sector with an error is in
the command block registers. This bit is cleared by the next command.
48/82
SMCxxxAF
CF-ATA registers
Table 43.
8.10
Status & alternate status register
D7
D6
D5
D4
D3
D2
D1
D0
BUSY
RDY
DWF
DSC
DRQ
CORR
0
ERR
Device control register (address 3F6h [376h]; offset Eh)
This write-only register is used to control the CompactFlash memory card interrupt request
and to issue an ATA soft reset to the card. This register can be written even if the device is
BUSY. The bits are defined as follows:
8.10.1
Bit 7 to 3
Don’t care. The host should reset this bit to ‘0’.
8.10.2
Bit 2 (SW Rst)
This bit is set to ‘1’ in order to force the CompactFlash storage card to perform an AT Disk
controller Soft Reset operation. This clears status register and writes diagnostic code in
error register after a write or read sector error. The card remains in reset until this bit is reset
to ‘0.’
8.10.3
Bit 1 (–IEn)
When the Interrupt Enable bit is set to ‘0’, –IREQ interrupts are enabled. When the bit is set
to ‘1’, interrupts from the card are disabled. This bit also controls the Int bit in the card
configuration and status register. It is set to ‘0’ at power-on.
8.10.4
Bit 0
This bit is set to ‘0’.
Table 44.
Device control register
D7
D6
D5
D4
D3
D2
D1
D0
X(0)
X(0)
X(0)
X(0)
X(0)
SW Rst
–IEn
0
49/82
CF-ATA registers
8.11
SMCxxxAF
Card (drive) address register (address 3f7h [377h]; offset Fh)
This read-only register is provided for compatibility with the AT disk drive interface and can
be used for confirming the drive status. It is recommended that this register is not mapped
into the host’s I/O space because of potential conflicts on bit 7. The bits are defined as
follows:
8.11.1
Bit 7
This bit is Don’t care.
8.11.2
Bit 6 (–WTG)
This bit is ‘0’ when a write operation is in progress, otherwise, it is ‘1’.
8.11.3
Bit 5 (–HS3)
This bit is the negation of bit 3 in the drive/head register.
8.11.4
Bit 4 (–HS2)
This bit is the negation of bit 2 in the drive/head register.
8.11.5
Bit 3 (–HS1)
This bit is the negation of bit 1 in the drive/head register.
8.11.6
Bit 2 (–HS0)
This bit is the negation of bit 0 in the drive/head register.
8.11.7
Bit 1 (–nDS1)
This bit is ‘0’ when drive 1 is active and selected.
8.11.8
Bit 0 (–nDS0)
This bit is ‘0’ when the drive 0 is active and selected.
Table 45.
50/82
Card (drive) address register
D7
D6
D5
D4
D3
D2
D1
D0
X
–WTG
–HS3
–HS2
–HS1
–HS0
–nDS1
–nDS0
SMCxxxAF
9
CF-ATA command description
CF-ATA command description
This section defines the software requirements and the format of the commands the host
sends to the card. Commands are issued to the card by loading the required registers in the
command block with the supplied parameters, and then writing the command code to the
command register. There are three classes of command acceptance, all dependent on the
host not issuing commands unless the card is not busy (BSY is ‘0’).
●
Class 1. Upon receipt of a class 1 command, the card sets BSY within 400 ns.
●
Class 2. Upon receipt of a class 2 command, the card sets BSY within 400 ns, sets up
the sector buffer for a write operation, sets DRQ within 700 µs, and clears BSY within
400 ns of setting DRQ.
●
Class 3. Upon receipt of a class 3 command, the card sets BSY within 400 ns, sets up
the sector buffer for a write operation, sets DRQ within 20 ms (assuming no reassignments), and clears BSY within 400 ns of setting DRQ.
For reasons of backward compatibility some commands are implemented as ‘no operation’
NOP.
Table 46 summarizes the CF-ATA command set with the paragraphs that follow describing
the individual commands and the task file for each.
Table 46.
CF-ATA command set(1)
Class
Command
Code
FR
SC
1
Check Power mode
E5h or 98h
D
1
Execute Drive Diagnostic
90h
YD
1
Erase Sector(s)
C0h
1
Identify Drive
ECh
1
Idle
E3h or 97h
1
Idle immediate
E1h or 95h
1
Initialize Drive Parameters
91h
1
NOP
00h
D
1
Read Buffer
E4h
D
1
Read Multiple
C4h
Y
Y
Y
Y
Y
1
Read Sector(s)
20h or 21h
Y
Y
Y
Y
Y
1
Read Verify Sector(s)
40h or 41h
Y
Y
Y
Y
Y
1
Recalibrate
1Xh
D
1
Request Sense
03h
D
1
Seek
7Xh
1
Set Features
EFh
1
Set Multiple mode
C6h
1
Set Sleep mode
E6h or 99h
D
1
Standby
E2h or 96h
D
Y
SN
Y
CY
Y
DH
Y
LBA
Y
D
Y
D
D
Y
Y
Y
Y
Y
Y
Y
D
Y
D
51/82
CF-ATA command description
SMCxxxAF
CF-ATA command set(1) (continued)
Table 46.
Class
Command
Code
FR
SC
SN
CY
DH
LBA
1
Standby immediate
E0h or 94h
1
Translate Sector
87h
1
Wear Level
F5h
Y
2
Write Buffer
E8h
D
3
Write Multiple
C5h
Y
Y
Y
Y
Y
3
Write Multiple w/o Erase
CDh
Y
Y
Y
Y
Y
2
Write Sector(s)
30h or 31h
Y
Y
Y
Y
Y
2
Write Sector(s) w/o Erase
38h
Y
Y
Y
Y
Y
3
Write Verify
3Ch
Y
Y
Y
Y
Y
D
Y
Y
Y
Y
Y
1. FR = Features Register, SC = Sector Count Register, SN = Sector Number Register, CY = Cylinder
Registers, DH = Card/Drive/Head Register, LBA = Logical Block Address Mode Supported (see command
descriptions for use),
Y - The register contains a valid parameter for this command. For the drive/head register Y means both the
Compact Flash memory card and head parameters are used.
D - only the Compact Flash memory card parameter is valid and not the head parameter
C - the register contains command specific data (see command descriptors for use).
9.1
Check Power mode command (98h or E5h)
This command checks the power mode.
Issuing the command while the card is in Standby mode, is about to enter Standby, or is
exiting Standby, the command will set BSY, set the Sector Count register to 00h, clear BSY
and generate an interrupt.
Issuing the command when the card is in Idle mode will set BSY, set the Sector Count
register to FFh, clear BSY and generate an interrupt.
Table 47 defines the byte sequence of the Check Power mode command.
Table 47.
Check Power mode
Bit
7
6
Command (7)
C/D/H (6)
52/82
5
4
3
2
1
98h or E5h
X
Drive
X
Cyl High (5)
X
Cyl Low (4)
X
Sect Num (3)
X
Sect Cnt (2)
X
Feature (1)
X
0
SMCxxxAF
9.2
CF-ATA command description
Execute Drive Diagnostic command (90h)
This command performs the internal diagnostic tests implemented by the card.
In PCMCIA configuration, this command only runs on the card which is addressed by the
drive/head register when the command is issued. This is because PCMCIA card interface
does not allow for direct inter-drive communication.
In True IDE mode, the Drive bit is ignored and the diagnostic command is executed by both
the master and the slave with the master responding with the status for both devices.
Table 48 defines the Execute Drive Diagnostic command byte sequence. The diagnostic
codes shown in Table 49 are returned in the error register at the end of the command.
Table 48.
Execute Drive Diagnostic
Bit
7
6
5
4
3
Command (7)
1
0
90h
C/D/H (6)
X
Drive
X
Cyl High (5)
X
Cyl Low (4)
X
Sect Num (3)
X
Sect Cnt (2)
X
Feature (1)
X
Table 49.
2
Diagnostic codes
Code
Error type
01h
No error detected
02h
Formatter device error
03h
Sector buffer error
04h
ECC circuitry error
05h
Controlling microprocessor error
8Xh
Slave error in True IDE mode
53/82
CF-ATA command description
9.3
SMCxxxAF
Erase Sector(s) command (C0h)
This command is used to pre-erase and condition data sectors prior to a Write Sector
Without Erase command or a Write Multiple Without Erase command. There is no data
transfer associated with this command but a Write Fault error status can occur. Table 50
defines the byte sequence of the Erase Sector command.
Table 50.
Erase Sector(s)
Bit
7
6
5
4
Command (7)
C/D/H (6)
9.4
3
2
1
0
C0h
1
LBA
1
Drive
Head (LBA 27-24)
Cyl High (5)
Cylinder High (LBA 23-16)
Cyl Low (4)
Cylinder Low (LBA 15-8)
Sect Num (3)
Sector Number (LBA 7-0)
Sect Cnt (2)
Sector Count
Feature (1)
X
Identify Drive command (ECh)
The Identify Drive command enables the host to receive parameter information from the
card. This command has the same protocol as the Read Sector(s) command. Table 51
defines the Identify Drive command byte sequence. All reserved bits or words are zero.
Table 52 shows the definition of each field in the identify drive information.
9.4.1
Word 0: general configuration
This field indicates that the device is a CompactFlash memory card.
9.4.2
Word 1: default number of cylinders
This field contains the number of translated cylinders in the default translation mode. This
value will be the same as the number of cylinders.
9.4.3
Word 3: default number of heads
This field contains the number of translated heads in the default translation mode.
9.4.4
Word 6: default number of sectors per track
This field contains the number of sectors per track in the default translation mode.
9.4.5
Word 7-8: number of sectors per card
This field contains the number of sectors per card. This double word value is also the first
invalid address in LBA translation mode.
54/82
SMCxxxAF
9.4.6
CF-ATA command description
Word 10-19: memory card serial number
The contents of this field are right justified and padded with spaces (20h).
9.4.7
Word 23-26: firmware revision
This field contains the revision of the firmware for this product.
9.4.8
Word 27-46: model number
This field contains the model number for this product and is left justified and padded with
spaces (20h).
9.4.9
Word 47: read/write multiple sector count
This field contains the maximum number of sectors that can be read or written per interrupt
using the Read Multiple or Write Multiple commands.
9.4.10
9.4.11
Word 49: capabilities
●
Bit 13 Standby timer: it is set to ’0’ to indicate that the Standby timer operation is
defined by the manufacturer.
●
Bit 9 LBA support: CompactFlash memory cards support LBA mode addressing.
●
Bit 8 DMA Support: DMA mode is not supported.
Word 51: PIO data transfer cycle timing mode
This field defines the mode for PIO data transfer. For backward compatibility with BIOSs
written before word 64 was defined for advanced modes, a device reports in word 51, the
highest original PIO mode it can support (PIO mode 0, 1 or 2).
Bits 15-8: are set to 02H.
9.4.12
9.4.13
Word 53: translation parameter valid
●
Bit 1: is set to '1' to indicate that words 64 to 70 are valid
●
Bit 0: is set to '1' to indicate that words 54 to 58 are valid
Word 54-56: current number of cylinders, heads, sectors/track
These fields contains the current number of user addressable cylinders, heads, and
sectors/track in the current translation mode.
9.4.14
Word 57-58: current capacity
This field contains the product of the current cylinders, heads and sectors.
55/82
CF-ATA command description
9.4.15
9.4.16
SMCxxxAF
Word 59: multiple sector setting
●
Bits 15-9 are reserved and must be set to ‘0’.
●
Bit 8 is set to ‘1’, to indicate that the multiple sector setting is valid.
●
Bits 7-0 are the current setting for the number of sectors to be transferred for every
interrupt, on Read/Write Multiple commands; the only values returned are 00h or 01h.
Word 60-61: total sectors addressable in LBA mode
This field contains the number of sectors addressable for the card in LBA mode only.
9.4.17
Word 64: advanced PIO transfer modes supported
This field is bit significant. Any number of bits may be set to ‘1’ in this field by the
CompactFlash memory card to indicate the advanced PIO modes it is capable of
supporting.
9.4.18
●
Bits 7-2 are reserved for future advanced PIO modes.
●
Bit 1 is set to ‘1’, indicates that the CompactFlash memory card supports PIO mode 4.
●
Bit 0 is set to ‘1’ to indicate that the CompactFlash memory card supports PIO mode 3.
Word 67: minimum PIO transfer cycle time without flow control
This field gives the minimum cycle time (in ns) that the host should use for the
CompactFlash memory card to provide data integrity during transfer when flow control is not
used. The value returned is 78h (for cycle time values refer to Table 22).
9.4.19
Word 68: minimum PIO transfer cycle time with IORDY
This field gives the minimum cycle time (in ns) supported by the CompactFlash memory
card to perform data transfers using IORDY flow control. The value returned is 78h (for
cycle time values refer to Table 22).
Table 51.
Identify drive
Bit
7
6
5
4
Command (7)
C/D/H (6)
56/82
3
2
1
ECh
X
Drive
X
Cyl High (5)
X
Cyl Low (4)
X
Sect Num (3)
X
Sect Cnt (2)
X
Feature (1)
X
0
SMCxxxAF
CF-ATA command description
Table 52.
Identify drive information
Word
address
Default
value
Total
bytes
0
848Ah
2
General configuration (signature for the CompactFlash
memory card)
1
XXXXh
2
Default number of cylinders
2
0000h
2
Reserved
3
00XXh
2
Default number of heads
4
0000h
2
Obsolete
5
0000h
2
Obsolete
6
XXXXh
2
Default number of sectors per track
7-8
XXXXh
4
Number of sectors per card (word 7 = MSW, word 8 = LSW)
9
0000h
2
Obsolete
10-19
aaaa
20
Serial number in ASCII (right justified)
20
0000h
2
Obsolete
Data field type information
21
0000h
2
Obsolete
22
0004h
2
Reserved
23-26
aaaa
8
Firmware revision in ASCII. Big endian byte order in word
27-46
aaaa
40
Model number in ASCII (right justified) big endian byte order
in word
47
0001h
2
Maximum number of sectors on read/write multiple
command
48
0000h
2
Reserved
49
0200h
2
Capabilities
50
0000h
2
Reserved
51
0200h
2
PIO data transfer cycle timing mode
52
0000h
2
Obsolete
53
0003h
2
Field validity
54
XXXXh
2
Current numbers of cylinders
55
XXXXh
2
Current numbers of heads
56
XXXXh
2
Current sectors per track
57-58
XXXXh
4
Current capacity in sectors (LBAs) (word 57 = LSW, word 58
= MSW)
59
01XXh
2
Multiple sector setting
60-61
XXXXh
4
Total number of sectors addressable in LBA mode
62-63
0000h
4
Reserved
64
0003h
2
Advanced PIO modes supported
65-66
0000h
4
Reserved
67
0078h
2
Minimum PIO transfer cycle time without flow control
68
0078h
2
69-128
0000h
120
Reserved
Minimum PIO transfer cycle time with IORDY flow control
129-159
0000h
62
Manufacturer unique bytes
160-255
0000h
192
Reserved
57/82
CF-ATA command description
9.5
SMCxxxAF
Idle command (97h or E3h)
This command causes the card to set BSY, enter the Idle mode, clear BSY and generate an
interrupt. If the sector count is non-zero, it is interpreted as a timer count (each count is
5 ms) and the automatic power down mode is enabled. If the sector count is zero, the
automatic power-down mode is disabled. Note that this time base (5 ms) is different from
the ATA specification. Table 53 defines the byte sequence of the Idle command.
Table 53.
Idle
Bit
7
6
Command (7)
C/D/H (6)
58/82
5
4
3
2
1
97h or E3h
X
Drive
X
Cyl High (5)
X
Cyl Low (4)
X
Sect Num (3)
X
Sect Cnt (2)
Timer Count (5 ms increments)
Feature (1)
X
0
SMCxxxAF
9.6
CF-ATA command description
Idle Immediate command (95h or E1h)
This command causes the card to set BSY, enter the Idle mode, clear BSY and generate an
interrupt. Table 54 defines the Idle Immediate command byte sequence.
Table 54.
Idle Immediate
Bit
7
6
5
4
Command (7)
2
1
0
95h or E1h
C/D/H (6)
9.7
3
X
Drive
X
Cyl High (5)
X
Cyl Low (4)
X
Sect Num (3)
X
Sect Cnt (2)
X
Feature (1)
X
Initialize Drive Parameters command (91h)
This command enables the host to set the number of sectors per track and the number of
heads per cylinder. Only the Sector Count and the Card/Drive/Head registers are used by
this command. Table 55 defines the Initialize Drive Parameters command byte sequence.
Table 55.
Initialize Drive Parameters
Bit
7
6
5
4
Command (7)
C/D/H (6)
3
2
1
0
91h
X
0
X
Drive
Max Head (no. of heads 1)
Cyl High (5)
X
Cyl Low (4)
X
Sect Num (3)
X
Sect Cnt (2)
Number of sectors
Feature (1)
X
59/82
CF-ATA command description
9.8
SMCxxxAF
NOP command (00h)
This command always fails with the CompactFlash memory card returning command
aborted. Table 56 defines the byte sequence of the NOP command.
Table 56.
NOP
Bit
7
6
5
4
3
Command (7)
1
0
00h
C/D/H (6)
9.9
2
X
Drive
X
Cyl High (5)
X
Cyl Low (4)
X
Sect Num (3)
X
Sect Cnt (2)
X
Feature (1)
X
Read Buffer command (E4h)
The Read Buffer command enables the host to read the current contents of the card’s sector
buffer. This command has the same protocol as the Read Sector(s) command. Table 57
defines the Read Buffer command byte sequence.
Table 57.
Read Buffer
Bit
7
6
5
4
Command (7)
C/D/H (6)
60/82
3
2
1
E4h
X
Drive
X
Cyl High (5)
X
Cyl Low (4)
X
Sect Num (3)
X
Sect Cnt (2)
X
Feature (1)
X
0
SMCxxxAF
9.10
CF-ATA command description
Read Multiple command (C4h)
The Read Multiple command performs similarly to the Read Sectors command. Interrupts
are not generated on every sector, but on the transfer of a block which contains the number
of sectors defined by a Set Multiple command.
Command execution is identical to the Read Sectors operation except that the number of
sectors defined by a Set Multiple command are transferred without intervening interrupts.
DRQ qualification of the transfer is required only at the start of the data block, not on each
sector.
The block count of sectors to be transferred without intervening interrupts is programmed by
the Set Multiple mode command, which must be executed prior to the Read Multiple
command. When the Read Multiple command is issued, the Sector Count register contains
the number of sectors (not the number of blocks or the block count) requested. If the
number of requested sectors is not evenly divisible by the block count, as many full blocks
as possible are transferred, followed by a final, partial block transfer. The partial block
transfer is for n sectors, where:
n = (sector count) module (block count).
If the Read Multiple command is attempted before the Set Multiple mode command has
been executed or when Read Multiple commands are disabled, the Read Multiple operation
is rejected with an aborted command error. Disk errors encountered during Read Multiple
commands are posted at the beginning of the block or partial block transfer, but DRQ is still
set and the data transfer will take place as it normally would, including transfer of corrupted
data, if any.
Interrupts are generated when DRQ is set at the beginning of each block or partial block.
The error reporting is the same as that on a Read Sector(s) command. This command reads
from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests
256 sectors. The transfer begins at the sector specified in the Sector Number register.
If an error occurs, the read terminates at the sector where the error occurred. The
Command Block registers contain the cylinder, head and sector number of the sector where
the error occurred. The flawed data is pending in the sector buffer.
Subsequent blocks or partial blocks are transferred only if the error was a correctable data
error. All other errors cause the command to stop after transfer of the block which contained
the error.
Table 58 defines the Read Multiple command byte sequence.
Table 58.
Read Multiple
Bit
7
6
5
4
3
Command (7)
C/D/H (6)
2
1
0
C4h
1
LBA
1
Drive
Head (LBA 27-24)
Cyl High (5)
Cylinder High (LBA 23-16)
Cyl Low (4)
Cylinder Low (LBA 15-8)
Sect Num (3)
Sector Number (LBA 7-0)
Sect Cnt (2)
Sector Count
Feature (1)
X
61/82
CF-ATA command description
9.11
SMCxxxAF
Read Sector(s) command (20h or 21h)
This command reads from 1 to 256 sectors as specified in the Sector Count register. A
sector count of 0 requests 256 sectors. The transfer begins at the sector specified in the
Sector Number register. When this command is issued and after each sector of data (except
the last one) has been read by the host, the card sets BSY, puts the sector of data in the
buffer, sets DRQ, clears BSY, and generates an interrupt. The host then reads the 512
bytes of data from the buffer.
If an error occurs, the read terminates at the sector where the error occurred. The
Command Block registers contain the cylinder, head, and sector number of the sector
where the error occurred. The flawed data is pending in the sector buffer. Table 59 defines
the Read Sector command byte sequence.
Table 59.
Bit
Read Sector(s)
7
6
5
4
Command
(7)
C/D/H (6)
9.12
3
2
1
0
20h or 21h
1
LBA
1
Drive
Head (LBA 27-24)
Cyl High
(5)
Cylinder High (LBA 23-16)
Cyl Low (4)
Cylinder Low (LBA 15-8)
Sect Num
(3)
Sector Number (LBA 7-0)
Sect Cnt
(2)
Sector Count
Feature (1)
X
Read Verify Sector(s) command (40h or 41h)
This command is identical to the Read Sectors command, except that DRQ is never set and
no data is transferred to the host. When the command is accepted, the card sets BSY.
When the requested sectors have been verified, the card clears BSY and generates an
interrupt.
If an error occurs, the verify terminates at the sector where the error occurs. The Command
Block registers contain the cylinder, head and sector number of the sector where the error
occurred. The Sector Count register contains the number of sectors not yet verified.
Table 60 defines the Read Verify Sector command byte sequence.
62/82
SMCxxxAF
CF-ATA command description
Table 60.
Read Verify Sector(s)
Bit
7
6
5
4
Command (7)
C/D/H (6)
9.13
3
2
1
0
40h or 41h
1
LBA
1
Drive
Head (LBA 27-24)
Cyl High (5)
Cylinder High (LBA 23-16)
Cyl Low (4)
Cylinder Low (LBA 15-8)
Sect Num (3)
Sector Number (LBA 7-0)
Sect Cnt (2)
Sector Count
Feature (1)
X
Recalibrate command (1Xh)
This command is effectively a NOP command to the card and is provided for compatibility
purposes. Table 61 defines the Recalibrate command byte sequence.
Table 61.
Recalibrate
Bit
7
6
5
4
Command (7)
C/D/H (6)
9.14
3
2
1
0
1Xh
1
LBA
1
Drive
X
Cyl High (5)
X
Cyl Low (4)
X
Sect Num (3)
X
Sect Cnt (2)
X
Feature (1)
X
Request Sense command (03h)
This command requests extended error information for the previous command. Table 62
defines the Request Sense command byte sequence. Table 63 defines the valid extended
error codes. The extended error code is returned to the host in the Error register.
63/82
CF-ATA command description
Table 62.
SMCxxxAF
Request Sense
Bit
7
6
5
4
Command (7)
C/D/H (6)
2
1
0
03h
1
X
1
Drive
X
Cyl High (5)
X
Cyl Low (4)
X
Sect Num (3)
X
Sect Cnt (2)
X
Feature (1)
X
Table 63.
64/82
3
Extended Error codes
Extended error code
Description
00h
No error detected
01h
Self test OK (no error)
09h
Miscellaneous error
21h
Invalid address (requested head or sector invalid)
2Fh
Address overflow (address too large)
35h, 36h
Supply or generated voltage out of tolerance
11h
Uncorrectable ECC Error
18h
Corrected ECC Error
05h, 30-34h, 37h, 3Eh
Self test or diagnostic failed
10h, 14h
ID not found
3Ah
Spare sectors exhausted
1Fh
Data transfer error / aborted command
0Ch, 38h, 3Bh, 3Ch, 3Fh
Corrupted media format
03h
Write / Erase failed
SMCxxxAF
9.15
CF-ATA command description
Seek command (7Xh)
This command is effectively a NOP command to the card although it does perform a range
check of cylinder and head or LBA address and returns an error if the address is out of
range. Table 64 shows the Seek command byte sequence.
Table 64.
Seek
Bit
7
6
5
Command (7)
C/D/H (6)
9.16
4
3
2
1
0
7Xh
1
LBA
1
Drive
Head (LBA 27-24)
Cyl High (5)
Cylinder High (LBA 23-16)
Cyl Low (4)
Cylinder Low (LBA 15-8)
Sect Num (3)
X (LBA 7-0)
Sect Cnt (2)
X
Feature (1)
X
Set Features command (EFh)
This command is used by the host to establish or select certain features. Table 65 shows the
Set Features command byte sequence. Table 66 defines all features that are supported.
Features 01h and 81h are used to enable and clear 8 bit data transfer modes in True IDE
mode. If the 01h Feature command is issued all data transfers will occur on the low order
D7D0 data bus and the –IOIS16 signal will not be asserted for data register accesses.
Feature 03h allows the host to select the PIO transfer mode by specifying a value in the
Sector Count register (see Table 67 for values). The upper 5 bits define the type of transfer
and the low order 3 bits encode the mode value. One PIO mode should be selected at all
times. The host may change the selected mode by issuing the Set Features command.
Feature code 9Ah enables the host to configure the card to best meet the host system's
power requirements. The host sets a value in the Sector Count register that is equal to onefourth of the desired maximum average current (in mA) that the card should consume. For
example, if the Sector Count register were set to 6, the card would be configured to provide
the best possible performance without exceeding 24 mA. Upon completion of the command,
the card responds to the host with the range of values supported by the card. The minimum
value is set in the Cylinder Low register, and the maximum value is set in the Cylinder Hi
register. The default value, after a power on reset, is to operate at the highest performance
and therefore the highest current mode.
The card will accept values outside this programmable range, but will operate at either the
lowest power or highest performance as appropriate.
65/82
CF-ATA command description
Table 65.
SMCxxxAF
Set Features
Bit
7
6
5
4
3
Command (7)
C/D/H (6)
X
Drive
0
X
X
Cyl Low (4)
X
Sect Num (3)
X
Sect Cnt (2)
Config
Feature (1)
Feature
Features supported
Feature
Operation
01h
Enable 8 bit data transfers.
03h
Set transfer mode based on value in Sector Count register.
55h
Disable Read Look Ahead.
69h
NOP Accepted for backward compatibility.
81h
Disable 8 bit data transfer.
96h
NOP accepted for backward compatibility.
97h
Accepted for backward compatibility. Use of this feature is not recommended.
9Ah
Set the host current source capability. Allows trade-off between current drawn and
read/write speed.
Table 67.
Transfer mode values
Mode
Bits (7:3)
Bits (2:0)
PIO default mode
00000b
000b
PIO default mode, disable
IORDY
00000b
001b
PIO flow control transfer
mode
00001b
Mode(1)
1. Mode = transfer mode number.
66/82
1
EFh
Cyl High (5)
Table 66.
2
SMCxxxAF
9.17
CF-ATA command description
Set Multiple mode command (C6h)
This command enables the card to perform Read and Write Multiple operations and
establishes the block count for these commands. The Sector Count register is loaded with
the number of sectors per block. Upon receipt of the command, the card sets BSY and
checks the Sector Count register.
If the Sector Count register contains a valid value and the block count is supported, the
value is loaded for all subsequent Read Multiple and Write Multiple commands and
execution is enabled. If a block count is not supported, an aborted command error is posted,
and Read Multiple and Write Multiple commands are disabled. If the Sector Count register
contains ‘0’ when the command is issued, Read and Write Multiple commands are disabled.
At power-on the default mode is Read and Write Multiple disabled, unless it is disabled by a
Set Feature command. Table 68 defines the Set Multiple Mode command byte sequence.
Table 68.
Set Multiple mode
Bit
7
6
5
4
3
Command (7)
1
0
C6h
C/D/H (6)
9.18
2
X
Drive
X
Cyl High (5)
X
Cyl Low (4)
X
Sect Num (3)
X
Sect Cnt (2)
Sector Count
Feature (1)
X
Set Sleep mode command (99h or E6h)
This command causes the CompactFlash memory card to set BSY, enter the Sleep mode,
clear BSY and generate an interrupt. Recovery from sleep mode is accomplished by simply
issuing another command. Sleep mode is also entered when internal timers expire so the
host does not need to issue this command except when it wishes to enter Sleep mode
immediately. The default value for the timer is 5 milliseconds. Note that this time base
(5 ms) is different from the ATA specification. Table 69 defines the Set Sleep mode
command byte sequence.
Table 69.
Set Sleep mode
Bit
7
6
Command (7)
C/D/H (6)
5
4
3
2
1
0
99h or E6h
X
Drive
X
Cyl High (5)
X
Cyl Low (4)
X
Sect Num (3)
X
Sect Cnt (2)
X
Feature (1)
X
67/82
CF-ATA command description
9.19
SMCxxxAF
Standby command (96h or E2)
This command causes the card to set BSY, enter the Sleep mode (which corresponds to the
ATA ‘Standby’ mode), clear BSY and return the interrupt immediately. Recovery from Sleep
mode is accomplished by issuing another command. Table 70 defines the Standby
command byte sequence.
Table 70.
Standby
Bit
7
6
5
4
Command (7)
2
1
0
96h or E2h
C/D/H (6)
9.20
3
X
Drive
X
Cyl High (5)
X
Cyl Low (4)
X
Sect Num (3)
X
Sect Cnt (2)
X
Feature (1)
X
Standby Immediate command (94h or E0h)
This command causes the card to set BSY, enter the Sleep mode (which corresponds to the
ATA Standby mode), clear BSY and return the interrupt immediately.
Recovery from Sleep mode is accomplished by issuing another command. Table 71 defines
the Standby Immediate byte sequence.
Table 71.
Standby Immediate
Bit
7
6
Command (7)
C/D/H (6)
68/82
5
4
3
2
1
94h or E0h
X
Drive
X
Cyl High (5)
X
Cyl Low (4)
X
Sect Num (3)
X
Sect Cnt (2)
X
Feature (1)
X
0
SMCxxxAF
9.21
CF-ATA command description
Translate Sector command (87h)
This command allows the host a method of determining the exact number of times a user
sector has been erased and programmed. The controller responds with a 512-byte buffer of
information containing the desired cylinder, head and sector, including its logical address,
and the hot count, if available, for that sector. Table 72 defines the Translate Sector
command byte sequence. Table 73 represents the information in the buffer.
Table 72.
Translate Sector
Bit
7
6
5
4
3
Command (7)
C/D/H (6)
2
0
87h
1
LBA
1
Drive
Head (LBA 27-24)
Cyl High (5)
Cylinder High (LBA 23-16)
Cyl Low (4)
Cylinder Low (LBA 15-8)
Sect Num (3)
Sector Number (LBA 7-0)
Sect Cnt (2)
X
Feature (1)
X
Table 73.
1
Translate Sector information
Address
Information
00h-01h
Cylinder MSB (00), Cylinder LSB (01)
02h
Head
03h
Sector
04-06h
LBA MSB (04) - LSB (06)
07-12h
Reserved
13h
Erased Flag (FFh) = Erased; 00h = Not Erased
14h-17h
Reserved
18h-1Ah
Hot Count MSB (18) - LSB (1A); 0 = Hot Count not supported
1Bh-1FFh
Reserved
69/82
CF-ATA command description
9.22
SMCxxxAF
Wear Level command (F5h)
This command is effectively a NOP command and only implemented for backward
compatibility. The Sector Count register will always be returned with a 00h indicating Wear
Level is not needed.
Table 74 defines the Wear Level command byte sequence.
Table 74.
Wear Level
Bit
7
6
5
4
Command (7)
2
1
0
F5h
C/D/H (6)
9.23
3
X
Drive
Flag
Cyl High (5)
X
Cyl Low (4)
X
Sect Num (3)
X
Sect Cnt (2)
Completion Status
Feature (1)
X
Write Buffer command (E8h)
The Write Buffer command enables the host to overwrite contents of the card’s sector buffer
with any data pattern desired. This command has the same protocol as the Write Sector(s)
command and transfers 512 bytes.
Table 75 defines the Write Buffer command byte sequence.
Table 75.
Write Buffer
Bit
7
6
5
4
Command (7)
C/D/H (6)
70/82
3
2
1
E8h
X
Drive
X
Cyl High (5)
X
Cyl Low (4)
X
Sect Num (3)
X
Sect Cnt (2)
X
Feature (1)
X
0
SMCxxxAF
9.24
CF-ATA command description
Write Multiple command (C5h)
This command is similar to the Write Sectors command. The card sets BSY within 400 ns of
accepting the command. Interrupts are not presented on each sector but on the transfer of a
block which contains the number of sectors defined by Set Multiple. Command execution is
identical to the Write Sectors operation except that the number of sectors defined by the Set
Multiple command is transferred without intervening interrupts.
DRQ qualification of the transfer is required only at the start of the data block, not on each
sector. The block count of sectors to be transferred without intervening interrupts is
programmed by the Set Multiple Mode command, which must be executed prior to the Write
Multiple command.
When the Write Multiple command is issued, the Sector Count register contains the number
of sectors (not the number of blocks or the block count) requested. If the number of
requested sectors is not evenly divisible by the sector/block, as many full blocks as possible
are transferred, followed by a final, partial block transfer. The partial block transfer is for n
sectors, where:
n = (sector count) module (block count).
If the Write Multiple command is attempted before the Set Multiple Mode command has
been executed or when Write Multiple commands are disabled, the Write Multiple operation
will be rejected with an aborted command error.
Errors encountered during Write Multiple commands are posted after the attempted writes
of the block or partial block transferred. The Write command ends with the sector in error,
even if it is in the middle of a block. Subsequent blocks are not transferred in the event of an
error. Interrupts are generated when DRQ is set at the beginning of each block or partial
block.
The Command Block registers contain the cylinder, head and sector number of the sector
where the error occurred and the Sector Count register contains the residual number of
sectors that need to be transferred for successful completion of the command. For example,
each block has 4 sectors, a request for 8 sectors is issued and an error occurs on the third
sector. The Sector Count register contains 6 and the address is that of the third sector.
Note: The current revision of the CompactFlash memory card only supports a block count of
1 as indicated in the Identify Drive command information. The Write Multiple command is
provided for compatibility with future products which may support a larger block count.
Table 76 defines the Write Multiple command byte sequence.
Table 76.
Write Multiple
Bit
7
6
5
4
Command (7)
C/D/H (6)
3
2
1
0
C5h
1
LBA
1
Drive
Head
Cyl High (5)
Cylinder High
Cyl Low (4)
Cylinder Low
Sect Num (3)
Sector Number
Sect Cnt (2)
Sector Count
Feature (1)
X
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CF-ATA command description
9.25
SMCxxxAF
Write Multiple without Erase command (CDh)
This command is similar to the Write Multiple command with the exception that an implied
erase before write operation is not performed. The sectors should be pre-erased with the
Erase Sector(s) command before this command is issued. Table 77 defines the Write
Multiple without Erase command byte sequence.
Table 77.
Write Multiple without Erase
Bit
7
6
5
4
Command (7)
2
1
0
CDh
C/D/H (6)
9.26
3
X
LBA
Driv
e
1
Cyl High (5)
Cylinder High
Cyl Low (4)
Cylinder Low
Sect Num (3)
Sector Number
Sect Cnt (2)
Sector Count
Feature (1)
X
Head
Write Sector(s) command (30h or 31h)
This command writes from 1 to 256 sectors as specified in the Sector Count register. A
sector count of zero requests 256 sectors. The transfer begins at the sector specified in the
Sector Number register. When this command is accepted, the Card sets BSY, sets DRQ
and clears BSY, then waits for the host to fill the sector buffer with the data to be written. No
interrupt is generated to start the first host transfer operation. No data should be transferred
by the host until BSY has been cleared by the host.
For multiple sectors, after the first sector of data is in the buffer, BSY will be set and DRQ
will be cleared. After the next buffer is ready for data, BSY is cleared, DRQ is set and an
interrupt is generated. When the final sector of data is transferred, BSY is set and DRQ is
cleared. It will remain in this state until the command is completed at which time BSY is
cleared and an interrupt is generated. If an error occurs during a write of more than one
sector, writing terminates at the sector where the error occurred. The Command Block
registers contain the cylinder, head and sector number of the sector where the error
occurred. The host may then read the command block to determine what error has
occurred, and on which sector. Table 78 defines the Write Sector(s) command byte
sequence.
Table 78.
Write Sector(s)
Bit
7
6
5
Command (7)
C/D/H (6)
Cyl High (5)
72/82
4
3
2
1
30h or 31h
1
LBA
1
Drive
Head (LBA 27-24)
Cylinder High (LBA 23-16)
Cyl Low (4)
Cylinder Low (LBA 15-8)
Sect Num (3)
Sector Number (LBA 7-0)
Sect Cnt (2)
Sector Count
Feature (1)
X
0
SMCxxxAF
9.27
CF-ATA command description
Write Sector(s) without Erase command (38h)
This command is similar to the Write Sector(s) command with the exception that an implied
erase before write operation is not performed. This command has the same protocol as the
Write Sector(s) command. The sectors should be pre-erased with the Erase Sector(s)
command before this command is issued. If the sector is not pre-erased a normal write
sector operation will occur. Table 79 defines the Write Sector(s) without Erase command
byte sequence.
M
Table 79.
Write Sector(s) without Erase
Bit
7
6
5
4
3
Command (7)
1
0
38h
C/D/H (6)
9.28
2
1
LB
A
1
Drive
Head (LBA 27-24)
Cyl High (5)
Cylinder High (LBA 23-16)
Cyl Low (4)
Cylinder Low (LBA 15-8)
Sect Num (3)
Sector Number (LBA 7-0)
Sect Cnt (2)
Sector Count
Feature (1)
X
Write Verify command (3Ch)
This command is similar to the Write Sector(s) command, except each sector is verified
immediately after being written. This command has the same protocol as the Write Sector(s)
command. Table 80 defines the Write Verify command byte sequence.
Table 80.
Write Verify
Bit
7
6
5
4
3
Command (7)
C/D/H (6)
2
1
0
3Ch
1
LBA
1
Drive
Head (LBA 27-24)
Cyl High (5)
Cylinder High (LBA 23-16)
Cyl Low (4)
Cylinder Low (LBA 15-8)
Sect Num (3)
Sector Number (LBA 7-0)
Sect Cnt (2)
Sector Count
Feature (1)
X
73/82
CIS information (typical)
10
CIS information (typical)
-------0000: Code 01, link 04
DF 79 01 FF
-------–
Tuple CISTPL_DEVICE (01), length 4 (04)
–
Device type is FUNCSPEC
–
Extended speed byte used
–
Device speed is 80 ns
–
Write protect switch is not in control
–
Device size is 2 Kbytes
-------000C: Code 1C, link 05
02 DF 79 01 FF
-------–
Tuple CISTPL_DEVICE_OC (1C), length 5 (05)
–
Device conditions: VCC = 3.3 V
–
Device type is FUNCSPEC
–
Extended speed byte used
–
Device speed is 80 ns
–
Write protect switch is not in control
–
Device size is 2 Kbytes
-------001A: Code 18, link 02
DF 01
-------–
Tuple CISTPL_JEDEC_C (18), length 2 (02)
–
Device 0 JEDEC id: Manufacturer DF, ID 01
-------0022: Code 20, link 04
0A 00 00 00
-------– Tuple CISTPL_MANFID (20), length 4 (04)
– Manufacturer # 0x000A hardware rev 0.00
-------002E: Code 15, link 12
04 01 53 54 4D 00 53 54 4D 2D x x x x 42 00
00 FF
74/82
SMCxxxAF
SMCxxxAF
CIS information (typical)
-------–
Tuple CISTPL_VERS_1 (15), length 18 (12)
–
Major version 4, minor version 1
–
Product Information: Manufacturer: "STM",
–
Product name: "STM-xxxxB"
-------0056: Code 21, link 02
04 01
-------–
Tuple CISTPL_FUNCID (21), length 2 (02)
–
Function code 04 (Fixed Disk), system init 01
-------005E: Code 22, link 02
01 01
-------–
Tuple CISTPL_FUNCE (22), length 2 (02)
–
This is a PC Card ATA Disk
-------0066: Code 22, link 03
02 0C 0F
-------–
Tuple CISTPL_FUNCE (22), length 3 (03)
–
VPP is not required
–
This is a silicon device
–
Identify drive model/serial number is guaranteed unique
–
Low-power modes supported: Sleep Standby Idle
–
Drive automatically minimizes power
–
All modes include 3F7 or 377
–
Index bit is not supported
–
-IOIS16 is unspecified in twin configurations
-------0070: Code 1A, link 05
01 03 00 02 0F
75/82
CIS information (typical)
SMCxxxAF
-------–
Tuple CISTPL_CONFIG (1A), length 5 (05)
–
Last valid configuration index is 3
–
Configuration register base address is 200
–
Configuration registers present: configuration option register at 200
–
Card configuration and Status register at 202
–
Pin Replacement register at 204
–
Socket and Copy register at 206
-------007E: Code 1B, link 08
C0 C0 A1 01 55 08 00 20
-------–
Tuple CISTPL_CFTABLE_ENTRY (1B), length 8 (08)
–
Configuration table index is 00 (default)
–
Interface type is memory
–
BVDs not active, WP not active, RdyBsy active
–
Wait signal support required
–
VCC Power Description: Nom V = 5.0 V
–
map 2048 bytes of memory to card address 0
–
Miscellaneous Features: Max Twins 0, -Audio, -ReadOnly, +PowerDown
-------0092: Code 1B, link 06
00 01 21 B5 1E 4D
-------–
Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06)
–
Configuration table index is 00
–
VCC power description: Nom V = 3.30 V, Peak I = 45.0 mA
-------00A2: Code 1B, link 0A
C1 41 99 01 55 64 F0 FF FF 20
--------
76/82
–
Tuple CISTPL_CFTABLE_ENTRY (1B), length 10 (0A)
–
Configuration table index is 01 (default)
–
Interface type is I/O
–
BVDs not active, WP not active, RdyBsy active
–
Wait signal support not required
–
VCC power description: Nom V = 5.0 V
–
Decode 4 I/O lines, bus size 8 or 16
–
IRQ may be shared, pulse and level mode interrupts are supported
–
Interrupts in mask FFFF are supported
–
Miscellaneous Features: Max Twins 0, -Audio, -ReadOnly, +PowerDown
SMCxxxAF
CIS information (typical)
-------00BA: Code 1B, link 06
01 01 21 B5 1E 4D
-------–
Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06)
–
Configuration Table Index is 01
–
VCC power description: Nom V = 3.30 V,
–
Peak I = 45.0 mA
-------00CA: Code 1B, link 0F
C2 41 99 01 55 EA 61 F0 01 07 F6 03 01 EE 20
-------–
Tuple CISTPL_CFTABLE_ENTRY (1B), length 15 (0F)
–
Configuration Table Index is 02 (default)
–
Interface type is I/O
–
BVDs not active, WP not active, RdyBsy active
–
Wait signal support not required
–
VCC power description:
–
Nom V = 5.0 V
–
Decode 10 I/O lines, bus size 8 or 16
–
I/O block at 01F0, length 8
–
I/O block at 03F6, length 2
–
IRQ may be shared, pulse and level mode interrupts are supported
–
Only IRQ14 is supported
–
Miscellaneous features: Max Twins 0, -Audio, -ReadOnly, +PowerDown
-------00EC: Code 1B, link 06
02 01 21 B5 1E 4D
-------–
Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06)
–
Configuration table index is 02
–
VCC power description: Nom V = 3.30 V, Peak I = 45.0 mA
-------00FC: Code 1B, link 0F
C3 41 99 01 55 EA 61 70 01 07 76 03 01 EE 20
77/82
CIS information (typical)
SMCxxxAF
-------–
Tuple CISTPL_CFTABLE_ENTRY (1B), length 15 (0F)
–
Configuration table index is 03 (default)
–
Interface type is I/O
–
BVDs not active, WP not active, RdyBsy active
–
Wait signal support not required
–
VCC power description: Nom V = 5.0 V
–
Decode 10 I/O lines, bus size 8 or 16
–
I/O block at 0170, length 8
–
I/O block at 0376, length 2
–
IRQ may be shared, pulse and level mode interrupts are supported
–
Only IRQ14 is supported
–
Miscellaneous features: Max Twins 0, -Audio, -ReadOnly, +PowerDown
-------011E: Code 1B, link 06
03 01 21 B5 1E 4D
-------–
Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06)
–
Configuration table index is 03
–
VCC power description: Nom V = 3.30 V, Peak I = 45.0 mA
-------012E: Code 14, link 00
-------–
Tuple CISTPL_NO_LINK (14), length 0 (00)
-------0134: Code FF
-------–
78/82
Tuple CISTPL_END (FF)
SMCxxxAF
11
Package mechanical
Package mechanical
In order to meet environmental requirements, Numonyx offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
second-level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at:
www.numonyx.com.
Type I CompactFlash memory card dimensions
1.60mm ± 0.5
(0.063in ± 0.002)
26
50
0.99mm± 0.05
(0.039in ± 0.002)
1.65mm
(0.130in)
4X R 0.5mm ± 0.1
(4X R 0.020in ± 0.004)
1
1.01mm ± 0.07
(0.039in ± 0.003)
25
1.01mm ± 0.07
(0.039in ± 0.003)
2.44mm ± 0.07
(0.096in ± 0.003)
2.15mm ± 0.07
(0.085in ± 0.003)
2X 3.00mm ± 0.07
(2X 0.118in ± 0.003)
36.40mm ± 0.15
(1.433in ± 0.006)
P
Optional
Configuration
(see note)
TO
2X 25.78mm ± 0.07
(2X 1.015in ± 0.003)
3.30mm ± 0.10
(0.130in ± 0.004)
2X 12.00mm ± 0.1
(2X 0.472in ± 0.004)
Figure 9.
0.76mm ± 0.07
(0.030in ± 0.003)
41.66mm ± 0.13
(1.640in ± 0.005)
42.80mm ± 0.10
(1.685in ± 0.004)
0.63mm ± 0.07
(0.025in ± 0.003)
AI04301b
79/82
Ordering information
12
SMCxxxAF
Ordering information
Table 81.
Ordering information scheme
Example:
SMC
256
A
F
Y
6
E
Memory card standard
SMC = Storage Medium, CompactFlash
Density
032 = 32 Mbytes
064 = 64 Mbytes
128 = 128 Mbytes
256 = 256 Mbytes
512 = 512 Mbytes
Options of the standard
A = CF type I
Memory type
F = Flash memory
Card Version
Y= Version depending on device technology
Temperature range
6 = -40 to 85 °C
Packing
Blank = Standard packing (tray)
E = ECOPACK package, standard packing (tray)
Note:
Other digits may be added to the ordering code for preprogrammed parts or other options.
Devices are shipped from the factory with the memory content bits erased to ’1’.
For further information on any aspect of the device, please contact your nearest Numonyx
Sales Office.
80/82
SMCxxxAF
13
Revision history
Revision history
Table 82.
Document revision history
Date
Revision
Changes
22-Sep-2006
1
Initial release.
14-Nov-2007
2
ECOPACK text added in Section 11: Package mechanical.
Minor text changes.
12-Dec-2007
3
Applied Numonyx branding.
81/82
SMCxxxAF
Please Read Carefully:
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IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY
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NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
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Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility
applications.
Numonyx may make changes to specifications and product descriptions at any time, without notice.
Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,
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these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
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visiting Numonyx's website at http://www.numonyx.com.
Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 11/5/7, Numonyx B.V. All Rights Reserved.
82/82