Si5365 P R E L I M I N A R Y D A TA S H E E T PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER Description Features The Si5365 is a low jitter, precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre Channel, in which the application requires clock multiplication without jitter attenuation. The Si5365 accepts four clock inputs ranging from 19.44 to 707 MHz and generates five frequency-multiplied clock outputs ranging from 19.44 to 1050 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, and Fibre Channel rates. The Si5365 is based on Silicon Laboratories' 3rdgeneration DSPLL® technology, which provides anyrate frequency synthesis in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8 or 2.5 V supply, the Si5365 is ideal for providing clock multiplication in high performance timing applications. Selectable output frequencies ranging from 19.44 to 1050 MHz Low jitter clock outputs w/jitter generation as low as 0.6 ps rms (50 kHz–80 MHz) Integrated loop filter with selectable loop bandwidth (30 kHz to 1.3 MHz) Four clock inputs w/manual or automatically controlled hitless switching Five clock outputs with selectable signal format (LVPECL, LVDS, CML, CMOS) Support for ITU G.709 FEC ratios (255/238, 255/237, 255/236) LOS alarm outputs Digitally-controlled output phase adjust Pin-programmable settings On-chip voltage regulator for 1.8 or 2.5 V ±10% operation Small size: 14 x 14 mm 100-pin TQFP Pb-free, RoHS compliant Applications SONET/SDH OC-48/OC-192 line cards GbE/10GbE, 1/2/4/8/10GFC line cards ITU G.709 line cards Test and measurement CKIN1 ÷ N31 CKIN2 ÷ N32 ÷ NC1 CKOUT1 ÷ NC2 CKOUT2 ÷ NC3 CKOUT3 ® CKIN3 CKIN4 ÷ N33 DSPLL ÷ N34 ÷ N2 Divider Select Manual/Auto Switch ÷ NC4 CKOUT4 ÷ NC5 CKOUT5 Clock Select LOS/FOS Alarms Frequency Select Control Bandwidth Select VDD (1.8 or 2.5 V) GND Preliminary Rev. 0.34 3/07 Copyright © 2007 by Silicon Laboratories Si5365 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Si5365 Table 1. Performance Specifications (VDD = 1.8 or 2.5 V ±10%, TA = –40 to 85 ºC) Parameter Temperature Range Supply Voltage Supply Current Symbol Min Typ Max Unit TA –40 25 85 ºC VDD 2.25 2.5 2.75 V 1.62 1.8 1.98 V fOUT = 622.08 MHz All CKOUTs enabled LVPECL format output — 394 435 mA Only CKOUT1 enabled — 253 284 mA fOUT = 19.44 MHz All CKOUTs enabled CMOS format output — 278 321 mA Only CKOUT1 enabled — 229 261 mA Tristate/Sleep Mode — TBD TBD mA Input frequency and clock multiplication ratio pinselectable from table of values using FRQSEL and FRQTBL settings. Consult Silicon Laboratories configuration software DSPLLsim or Any-Rate Precision Clock Family Reference Manual at www.silabs.com/timing for table selections. 19.44 — 707.35 MHz 19.44 — 1049.76 MHz 0.25 — 1.9 VPP 1.8 V ±10% 0.9 — 1.4 V 2.5 V ±10% 1.0 — 1.7 V IDD Input Clock Frequency (CKIN1, CKIN2, CKIN3, CKIN4) CKF Output Clock Frequency (CKOUT1, CKOUT2, CKOUT3, CKOUT4, CKOUT5) CKOF Test Condition Input Clocks (CKIN1, CKIN2, CKIN3, CKIN4) Differential Voltage Swing CKNDPP Common Mode Voltage CKNVCM Rise/Fall Time CKNTRF 20–80% — — 11 ns Duty Cycle CKNDC Whichever is less 40 — 60 % 50 — — ns LVPECL 100 Ω load line-to-line VDD – 1.42 — VDD – 1.25 V 1.1 — 1.9 V 0.5 — 0.93 V 20–80% — 230 350 ps Output Clocks (CKOUT1, CKOUT2, CKOUT3, CKOUT4, CKOUT5) Common Mode VOCM Differential Output Swing VOD Single Ended Output Swing VSE Rise/Fall Time CKOTRF Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing. 2 Preliminary Rev. 0.34 Si5365 Table 1. Performance Specifications (Continued) (VDD = 1.8 or 2.5 V ±10%, TA = –40 to 85 ºC) Parameter Symbol Duty Cycle Test Condition Min Typ Max Unit 45 — 55 % fOUT = 622.08 MHz, LVPECL output format 50 kHz–80 MHz — 0.6 TBD ps rms 12 kHz–20 MHz — 0.6 TBD ps rms — 0.05 0.1 dB fOUT = 622.08 MHz 100 Hz offset — TBD TBD dBc/Hz 1 kHz offset — TBD TBD dBc/Hz 10 kHz offset — TBD TBD dBc/Hz 100 kHz offset — TBD TBD dBc/Hz 1 MHz offset — TBD TBD dBc/Hz CKODC PLL Performance Jitter Generation JGEN Jitter Transfer JPK Phase Noise CKOPN Subharmonic Noise SPSUBH Phase Noise @ 100 kHz Offset — TBD TBD dBc Spurious Noise SPSPUR Max spur @ n x F3 (n > 1, n x F3 < 100 MHz) — TBD TBD dBc θJA Still Air — 40 — ºC/W Package Thermal Resistance Junction to Ambient Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing. Table 2. Absolute Maximum Ratings Parameter Symbol Value Unit DC Supply Voltage VDD –0.5 to 2.75 V LVCMOS Input Voltage VDIG –0.3 to (VDD + 0.3) V Operating Junction Temperature TJCT –55 to 150 ºC Storage Temperature Range TSTG –55 to 150 ºC 2 kV ESD MM Tolerance 200 V Latch-Up Tolerance JESD78 Compliant ESD HBM Tolerance (100 pF, 1.5 kΩ) Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Preliminary Rev. 0.34 3 Si5365 155.52 MHz in, 622.08 MHz out 0 Phase Noise (dBc/Hz) -20 -40 -60 -80 -100 -120 -140 -160 100 1000 10000 100000 1000000 Offset Frequency (Hz) Figure 1. Typical Phase Noise Plot 4 Preliminary Rev. 0.34 10000000 100000000 Si5365 System Power Supply C10 Ferrite Bead 1 µF C1–9 130 Ω VDD GND 0.1 µF VDD = 3.3 V CKOUT1+ 130 Ω 0.1 µF + 100 Ω CKIN1+ CKOUT1– 0.1 µF – CKIN1– 82 Ω Input Clock Sources1 82 Ω Clock Outputs VDD = 3.3 V 130 Ω 130 Ω CKIN4+ CKIN4– 82 Ω CKOUT5+ 0.1 µF + 100 Ω 82 Ω CKOUT5– 0.1 µF – Si5365 Manual/Automatic Clock Selection (L) AUTOSEL2 Input Clock Select CKSEL[1:0]3 Frequency Table Select FRQTBL2 Frequency Select FRQSEL[3:0]2 Bandwidth Select BWSEL[1:0]2 Signal Format Select SFOUT[1:0]2 CKOUT_3 and CKOUT_4 Divider Control Clock Output 2 Disable/ Bypass Mode Control DIV34[1:0]2 DBL2_BY2 Clock Outputs 3 and 4 Disable DBL34 CKOUT5 Disable DBL52 Reset RST ALRMOUT CnB Alarm Output Indicator CKIN_n Invalid Indicator (n = 1 to 3) Notes: 1. Assumes differential LVPECL termination (3.3 V) on clock inputs. 2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD). 3. Assumes manual input clock selection. Figure 2. Si5365 Typical Application Circuit Preliminary Rev. 0.34 5 Si5365 1. Functional Description The Si5365 is a low jitter, precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre Channel, in which the application requires clock multiplication without jitter attenuation. The Si5365 accepts four clock inputs ranging from 19.44 to 707 MHz and generates five frequency-multiplied clock outputs ranging from 19.44 to 1050 MHz. By default the four clock inputs are at the same frequency and the five clock outputs are at the same frequency. Two of the output clocks can be divided down further to generate an integer sub-multiple frequency. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, and Fibre Channel rates. In addition to providing clock multiplication in SONET and datacom applications, the Si5365 supports SONET-to-datacom frequency translations. Silicon Laboratories offers a PCbased software utility, DSPLLsim, that can be used to look up valid Si5365 frequency translations. This utility can be downloaded from www.silabs.com/timing. This information is also available in the Any-Rate Precision Clock Family Reference Manual, also available from www.silabs.com/timing. The Si5365 is based on Silicon Laboratories' 3rdgeneration DSPLL® technology, which provides anyrate frequency synthesis in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The Si5365 PLL loop bandwidth is digitally programmable via the BWSEL[1:0] pins and supports a range from 30 kHz to 1.3 MHz. The DSPLLsim software utility can be used to calculate valid loop bandwidth settings for a given input clock frequency/clock multiplication ratio. 6 The Si5365 monitors all input clocks for loss-of-signal and provides a LOS alarm when it detects a missing clock. In the case when the input clocks enter alarm conditions, the PLL will freeze the DCO output frequency near its last value to maintain operation with an internal state close to the last valid operating state. The Si5365 has five differential clock outputs. The signal format of the clock outputs is programmable to support LVPECL, LVDS, CML, or CMOS loads. If not required, unused clock outputs can be powered down to minimize power consumption. The phase difference between the selected input clock and the output clocks is adjustable in 200 ps increments for system skew control. For system-level debugging, a bypass mode is available which drives the output clock directly from the input clock, bypassing the internal DSPLL. The device is powered by a single 1.8 or 2.5 V supply. 1.1. Further Documentation Consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual (FRM) for more detailed information about the Si5365. The FRM can be downloaded from www.silabs.com/timing. Silicon Laboratories has developed a PC-based software utility called DSPLLsim to simplify device configuration, including frequency planning and loop bandwidth selection. This utility can be downloaded from www.silabs.com/timing. Preliminary Rev. 0.34 Si5365 VDD CKOUT3+ CKOUT3– VDD SFOUT1 VDD CKOUT1– CKOUT1+ VDD DSBL34 CKOUT5– VDD CKOUT5+ VDD NC VDD CKOUT2+ CKOUT2– SFOUT0 VDD VDD CKOUT4– VDD CKOUT4+ VDD 2. Pin Descriptions: Si5365 NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 1 NC NC 2 74 NC RST 3 73 NC FRQTBL 4 NC VDD 5 72 71 VDD 6 70 FRQSEL2 GND GND 7 69 FRQSEL1 8 FRQSEL0 C1B 9 68 67 C2B C3B 10 66 DIV34_0 11 65 ALRMOUT 12 64 GND GND CS0_C3A 13 63 VDD GND 14 VDD VDD 15 62 61 GND 16 17 60 BWSEL0 59 C2A 18 58 C1A 57 CS1_C4A NC GND Si5365 GND PAD FRQSEL3 DIV34_1 BWSEL1 GND 19 NC 20 56 GND NC 21 55 NC AUTOSEL NC 22 54 53 NC NC 24 25 52 NC NC GND DBL5 NC NC NC CKIN1– GND CKIN1+ GND VDD GND CKIN3– GND CKIN3+ DBL2_BY GND CKIN2– GND CKIN2+ VDD GND CKIN4– CKIN4+ GND VDD 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 GND NC 23 Table 3. Si5365 Pin Descriptions Pin # Pin Name 1, 2, 17, 20, 21, 23, 24, 25, 47, 48, 49, 52, 53, 54, 55, 72, 73, 74, 75, 90 NC I/O Signal Level Description No Connect. These pins must be left unconnected for normal operation. Preliminary Rev. 0.34 7 Si5365 Table 3. Si5365 Pin Descriptions (Continued) Pin # Pin Name 3 RST I LVCMOS External Reset. Active low input that performs external hardware reset of device. Resets all internal logic to a known state and forces the device registers to their default value. Clock outputs are tristated during reset. After rising edge of RST signal, the device will perform an internal self-calibration. This pin has a weak pull-up. 4 FRQTBL I 3-Level Frequency Table Select. This pin selects SONET/SDH, datacom, or SONET/SDH to datacom frequency translation table. L = SONET/SDH. M = Datacom. H = SONET/SDH to Datacom. This pin has a weak pull-down. 5, 6, 15, 27, 32, 42, 62, 63, 76, 79, 81, 84, 86, 89, 91, 94, 96, 99, 100 VDD VDD Supply VDD. The device operates from a 1.8 or 2.5 V supply. Bypass capacitors should be associated with the following VDD pins: Pins Bypass Cap 5, 6 0.1 µF 15 0.1 µF 27 0.1 µF 62, 63 0.1 µF 76, 79 1.0 µF 81, 84 0.1 µF 86, 89 0.1 µF 91, 94 0.1 µF 96, 99, 100 0.1 µF 7, 8, 14, 16, 18, 19, 26, 28, 31, 33, 36, 38, 41, 43, 46, 51, 56, 64, 65 GND GND Supply Ground. These pins must be connected to system ground. Minimize the ground path impedance for optimal performance. 9 C1B O LVCMOS CKIN1 Invalid Indicator. This pin is an active high alarm output associated with CKIN1. Once triggered, the alarm will remain high until CKIN1 is validated. 0 = No alarm on CKIN1. 1 = Alarm on CKIN1. 10 C2B O LVCMOS CKIN2 Invalid Indicator. This pin is an active high alarm output associated with CKIN2. Once triggered, the alarm will remain high until CKIN2 is validated. 0 = No alarm on CKIN2. 1 = Alarm on CKIN2. 11 C3B O LVCMOS CKIN3 Invalid Indicator. This pin is an active high alarm output associated with CKIN3. 0 = No alarm on CKIN3. 1 = Alarm on CKIN3. 8 I/O Signal Level Description Preliminary Rev. 0.34 Si5365 Table 3. Si5365 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level Description 12 ALRMOUT O LVCMOS Alarm Output Indicator. This pin is an active high alarm output associated with CKIN4 or the frame sync alignment alarm. 0 = ALRMOUT not active. 1 = ALRMOUT active. 13 57 CS0_C3A CS1_C4A I/O LVCMOS Input Clock Select/CKINn Active Clock Indicator. If manual clock selection mode is chosen (AUTOSEL = 1), the CS[1:0] pins function as the manual input clock selector control. CS[1:0] Active Input Clock 00 CKIN1 01 CKIN2 10 CKIN3 11 CKIN4 These inputs are internally deglitched to prevent inadvertent clock switching during changes in the CSn input state. If automatic clock detection is chosen (AUTOSEL = M or H), these pins function as the CKINn active clock indicator output. 0 = CKINn is not the active input clock. 1 = CKINn is currently the active input clock to the PLL. This pin has a weak pull-down. 22 AUTOSEL I 3-Level Manual/Automatic Clock Selection. Three level input that selects the method of input clock selection to be used. L = Manual. M = Automatic non-revertive. H = Automatic revertive. 29 30 CKIN4+ CKIN4– I MULTI Clock Input 4. Differential clock input. This input can also be driven with a single-ended signal. 34 35 CKIN2+ CKIN2– I MULTI Clock Input 2. Differential input clock. This input can also be driven with a single-ended signal. 37 DBL2_BY I 3-Level CKOUT2 Disable/PLL Bypass Mode Control. Controls enable of CKOUT2 divider/output buffer path and PLL bypass mode. L = CKOUT2 Enabled. M = CKOUT2 Disabled. H = BYPASS Mode with CKOUT2 enabled. 39 40 CKIN3+ CKIN3– I MULTI Clock Input 3. Differential clock input. This input can also be driven with a single-ended signal. 44 45 CKIN1+ CKIN1– I MULTI Clock Input 1. Differential clock input. This input can also be driven with a single-ended signal. Preliminary Rev. 0.34 9 Si5365 Table 3. Si5365 Pin Descriptions (Continued) Pin # Pin Name 50 DBL5 I 3-Level 58 C1A O LVCMOS CKIN1 Active Clock Indicator. This pin serves as the CKIN1 active clock indicator. 0 = CKIN1 is not the active input clock. 1 = CKIN1 is currently the active input clock to the PLL. 59 C2A O LVCMOS CKIN2 Active Clock Indicator. This pin serves as the CKIN2 active clock indicator. 0 = CKIN2 is not the active input clock. 1 = CKIN2 is currently the active input clock to the PLL. 60 61 BWSEL0 BWSEL1 I 3-Level Bandwidth Select. These pins are three level inputs that select the DSPLL closed loop bandwidth according to the Any-Rate Precision Clock Family Reference Manual. 66 67 DIV34_0 DIV34_1 I 3-Level CKOUT3 and CKOUT4 Divider Control. These pins control the division of CKOUT3 and CKOUT4 relative to the CKOUT2 output frequency. Detailed operations and timing characteristics for these pins may be found in the Any-Rate Precision Clock Family Reference Manual. 68 69 70 71 FRQSEL0 FRQSEL1 FRQSEL2 FRQSEL3 I 3-Level Multiplier Select. These pins are three level inputs that select the input clock and clock multiplication setting according to the Any-Rate Precision Clock Family Reference Manual, depending on the FRQTBL setting. 77 78 CKOUT3+ CKOUT3– O MULTI Clock Output 3. Differential output clock with a frequency specified by FRQSEL and FRQTBL settings. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. 10 I/O Signal Level Description CKOUT5 Disable. This pin performs the following functions: L = Normal operation. Output path is active and signal format is determined by SFOUT inputs. M = CMOS signal format. Overrides SFOUT signal format to allow CKOUT5 to operate in CMOS format while the clock outputs operate in a differential output format. H = Powerdown. Entire CKOUT5 divider and output buffer path is powered down. CKOUT5 output will be in tristate mode during powerdown. Preliminary Rev. 0.34 Si5365 Table 3. Si5365 Pin Descriptions (Continued) Pin # Pin Name 80 95 SFOUT1 SFOUT0 I/O Signal Level I 3-Level Description Signal Format Select. Three level inputs that select the output signal format (common mode voltage and differential swing) for all of the clock outputs and CKOUT5. SFOUT[1:0] Signal Format HH Reserved HM Reserved HL CML MH LVPECL MM Reserved ML LVDS LH CMOS LM Tristate/Sleep LL Reserved 82 83 CKOUT1– CKOUT1+ O MULTI Clock Output 1. Differential output clock with a frequency specified by FRQSEL and FRQTBL. Output signal format is selected by SFOUT pins. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. 85 DBL34 I LVCMOS Output 3 and 4 Disable. Active high input. When active, entire CKOUT3 and CKOUT4 divider and output buffer path is powered down. CKOUT3 and CKOUT4 outputs will be in tristate mode during powerdown. This pin has a weak pull-down. 87 88 CKOUT5– CKOUT5+ O MULTI Clock Output 5. Fifth high-speed clock output with a frequency specified by FRQSEL and FRQTBL. Output signal format is selected by SFOUT pins. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. 92 93 CKOUT2+ CKOUT2– O MULTI Clock Output 2. Differential output clock with a frequency specified by FRQSEL and FRQTBL. Output signal format is selected by SFOUT pins. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. 97 98 CKOUT4– CKOUT4+ O MULTI Clock Output 4. Differential output clock with a frequency specified by FRQSEL and FRQTBL settings. Output signal format is selected by SFOUT pins. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. Supply Ground Pad. The ground pad must provide a low thermal and electrical impedance to a ground plane. GND PAD GND PAD GND Preliminary Rev. 0.34 11 Si5365 3. Ordering Guide 12 Ordering Part Number Package Temperature Range Si5365-B-GQ 100-Pin 14 x 14 mm TQFP –40 to 85 °C Preliminary Rev. 0.34 Si5365 4. Package Outline: 100-Pin TQFP Figure 3 illustrates the package details for the Si5365. Table 4 lists the values for the dimensions shown in the illustration. Figure 3. 100-Pin Thin Quad Flat Package (TQFP) Table 4. 100-Pin Package Diagram Dimensions Dimension Min Nom Max Dimension Min Nom Max A — — 1.20 E 16.00 BSC. A1 0.05 — 0.15 E1 14.00 BSC. A2 0.95 1.00 1.05 E2 3.85 4.00 4.15 b 0.17 0.22 0.27 L 0.45 0.60 0.75 c 0.09 — 0.20 aaa — — 0.20 D 16.00 BSC. bbb — — 0.20 D1 14.00 BSC. ccc — — 0.08 ddd — — 0.08 Θ 0º 3.5º 7º D2 e 3.85 4.00 0.50 BSC. 4.15 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This package outline conforms to JEDEC MS-026, variant AED-HD. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Preliminary Rev. 0.34 13 Si5365 5. Recommended PCB Layout Figure 4. PCB Land Pattern Diagram 14 Preliminary Rev. 0.34 Si5365 Table 5. PCB Land Pattern Dimensions Dimension MIN MAX e 0.50 BSC. E 15.40 REF. D 15.40 REF. E2 3.90 4.10 D2 3.90 4.10 GE 13.90 — GD 13.90 — X — 0.30 Y 1.50 REF. ZE — 16.90 ZD — 16.90 R1 R2 0.15 REF — 1.00 Notes (General): 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-7351 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Notes (Solder Mask Design): 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Notes (Stencil Design): 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. Notes (Card Assembly): 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Preliminary Rev. 0.34 15 Si5365 DOCUMENT CHANGE LIST Revision 0.32 to Revision 0.33 Condensed format. Revision 0.33 to Revision 0.34 16 Removed references to latency control, INC, and DEC pins. Updated Table 1, “Performance Specifications,” on page 2. Changed LVTTL to LVCMOS in Table 2, “Absolute Maximum Ratings,” on page 3. Added Figure 1, “Typical Phase Noise Plot,” on page 4. Updated Figure 2, “Si5365 Typical Application Circuit”. Updated “2. Pin Descriptions: Si5365”. Updated "3. Ordering Guide" on page 12. Added “5. Recommended PCB Layout”. Preliminary Rev. 0.34 Si5365 NOTES: Preliminary Rev. 0.34 17 Si5365 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: [email protected] Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. 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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 18 Preliminary Rev. 0.34