Si5326 P R E L I M I N A R Y D A TA S H E E T ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR Description Features The Si5326 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. The Si5326 accepts dual clock inputs ranging from 2 kHz to 710 MHz and generates two clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down separately from a common source. The device provides virtually any frequency translation combination across this operating range. The Si5326 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. The Si5326 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5326 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications. Generates any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from an input frequency of 2 kHz to 710 MHz Ultra-low jitter clock outputs w/jitter generation as low as 0.3 ps rms (50 kHz–80 MHz) Integrated loop filter with selectable loop bandwidth (60 Hz to 8.4 kHz) Meets OC-192 GR-253-CORE jitter specifications Dual clock inputs w/manual or automatically controlled hitless switching Dual clock outputs with selectable signal format (LVPECL, LVDS, CML, CMOS) Support for ITU G.709 and custom FEC ratios (255/238, 255/237, 255/236) LOL, LOS, FOS alarm outputs Digitally-controlled output phase adjust Applications I2C or SPI programmable On-chip voltage regulator for 1.8, 2.5, or 3.3 V ±10% operation Small size: 6 x 6 mm 36-lead QFN Pb-free, ROHS compliant SONET/SDH OC-48/OC-192 line cards GbE/10GbE, 1/2/4/8/10GFC line cards ITU G.709 and custom FEC line cards Optical modules Wireless basestations Data converter clocking xDSL SONET/SDH + PDH clock synthesis Test and measurement Xtal or Refclock CKIN1 CKIN2 ÷ N31 ÷ NC1 CKOUT1 ÷ NC2 CKOUT2 ® ÷ N32 DSPLL ÷ N2 Loss of Signal/ Frequency Offset Loss of Lock I2C/SPI Port Device Interrupt Rate Select Confidential Rev. 0.2 2/07 VDD (1.8, 2.5, or 3.3 V) Control Signal Detect GND Clock Select Latency Control Copyright © 2007 by Silicon Laboratories Si5326 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Si5326 Table 1. Performance Specifications (VDD = 1.8, 2.5, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Symbol Temperature Range Supply Voltage Supply Current Input Clock Frequency (CKIN1, CKIN2) Output Clock Frequency (CKOUT1, CKOUT2) Min Typ Max Unit TA –40 25 85 ºC VDD 2.97 3.3 3.63 V 2.25 2.5 2.75 V 1.62 1.8 1.98 V fOUT = 622.08 MHz Both CKOUTs enabled LVPECL format output — 251 279 mA CKOUT2 disabled — 217 243 mA fOUT = 19.44 MHz Both CKOUTs enabled CMOS format output — 204 234 mA CKOUT2 disabled — 194 220 mA Tristate/Sleep Mode — TBD TBD mA Input frequency and clock multiplication ratio determined by programming device PLL dividers. Consult Silicon Laboratories configuration software DSPLLsim to determine PLL divider settings for a given input frequency/clock multiplication ratio combination. 0.002 — 710 MHz 0.002 970 1213 — 945 1134 1417 MHz 0.25 — 1.9 VPP 1.8 V ±10% 0.9 — 1.4 V 2.5 V ±10% 1.0 — 1.7 V 3.3 V ±10% 1.1 — 1.95 V IDD CKF CKOF Test Condition Input Clocks (CKIN1, CKIN2) Differential Voltage Swing CKNDPP Common Mode Voltage CKNVCM Rise/Fall Time CKNTRF 20–80% — — 11 ns Duty Cycle CKNDC Whichever is less 40 — 60 % 50 — — ns LVPECL 100 Ω load line-to-line VDD – 1.42 — VDD – 1.25 V 1.1 — 1.9 0.5 — 0.93 V 20–80% — 230 350 ps Output Clocks (CKOUT1, CKOUT2) Common Mode VOCM Differential Output Swing VOD Single Ended Output Swing VSE Rise/Fall Time CKOTRF Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing. 2 Confidential Rev. 0.2 Si5326 Table 1. Performance Specifications (Continued) (VDD = 1.8, 2.5, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Symbol Min Typ Max Unit 45 — 55 % fOUT = 622.08 MHz, LVPECL output format 50 kHz–80 MHz — 0.3 TBD ps rms 12 kHz–20 MHz — 0.3 TBD ps rms 800 Hz–80 MHz — TBD TBD ps rms JPK — 0.05 0.1 dB External Reference Jitter Transfer JPKEXTN — TBD TBD dB Phase Noise CKOPN fOUT = 622.08 MHz 100 Hz offset — TBD TBD dBc/Hz 1 kHz offset — TBD TBD dBc/Hz 10 kHz offset — TBD TBD dBc/Hz 100 kHz offset — TBD TBD dBc/Hz 1 MHz offset — TBD TBD dBc/Hz Duty Cycle Test Condition CKODC PLL Performance Jitter Generation JGEN Jitter Transfer Subharmonic Noise SPSUBH Phase Noise @ 100 kHz Offset — TBD TBD dBc Spurious Noise SPSPUR Max spur @ n x F3 (n > 1, n x F3 < 100 MHz) — TBD TBD dBc Theta JA Still Air — TBD — ºC/W Package Thermal Resistance Junction to Ambient Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing. Table 2. Absolute Maximum Ratings Parameter Symbol Value Unit DC Supply Voltage VDD –0.5 to 3.6 V LVCMOS Input Voltage VDIG –0.3 to (VDD + 0.3) V Operating Junction Temperature TJCT –55 to 150 ºC Storage Temperature Range TSTG –55 to 150 ºC 2 kV 200 V ESD HBM Tolerance (100 pF, 1.5 kΩ) ESD MM Tolerance Latch-Up Tolerance JESD78 Compliant Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Confidential Rev. 0.2 3 Si5326 155.52 MHz in, 622.08 MHz out 0 Phase Noise (dBc/Hz) -20 -40 -60 -80 -100 -120 -140 -160 100 1000 10000 100000 1000000 Offset Frequency (Hz) Figure 1. Typical Phase Noise Plot 4 Confidential Rev. 0.2 10000000 100000000 Si5326 Figure 2. Si5326 Typical Application Circuit (I2C Control Mode) Figure 3. Si5326 Typical Application Circuit (SPI Control Mode) Confidential Rev. 0.2 5 Si5326 1. Functional Description The Si5326 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. The Si5326 accepts dual clock inputs ranging from 2 kHz to 710 MHz and generates two independent, synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides virtually any frequency translation combination across this operating range. Independent dividers are available for each input clock and output clock, so the Si5326 can accept input clocks at different frequencies and it can generate output clocks at different frequencies. The Si5326 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. Silicon Laboratories offers a PC-based software utility, DSPLLsim, that can be used to determine the optimum PLL divider settings for a given input frequency/clock multiplication ratio combination that minimizes phase noise and power consumption. This utility can be downloaded from www.silabs.com/timing. The Si5326 is based on Silicon Laboratories' 3rdgeneration DSPLL® technology, which provides anyrate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The Si5326 PLL loop bandwidth is digitally programmable and supports a range from 60 Hz to 8.4 kHz. The DSPLLsim software utility can be used to calculate valid loop bandwidth settings for a given input clock frequency/clock multiplication ratio. The Si5326 supports hitless switching between the two input clocks in compliance with GR-253-CORE and GR1244-CORE that greatly minimizes the propagation of phase transients to the clock outputs during an input clock transition (<200 ps typ). Manual and automatic revertive and non-revertive input clock switching options are available. The Si5326 monitors both input clocks for loss-of-signal and provides a LOS alarm when it detects missing pulses on either input clock. The device monitors the lock status of the PLL. The lock detect algorithm works by continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. The Si5326 also monitors frequency offset alarms (FOS), which indicate if an input clock is within a specified frequency precision relative to the frequency of a reference clock. Both Stratum 3/3E and SONET Minimum Clock (SMC) FOS thresholds are supported. The Si5326 provides a digital hold capability that allows the device to continue generation of a stable output clock when the selected input reference is lost. During digital hold, the DSPLL generates an output frequency 6 based on a historical average frequency that existed a fixed amount of time before the error event occurred, eliminating the effects of phase and frequency transients that may occur immediately preceding digital hold. Fine phase adjustment is available and is set using the FLAT register bits. The nominal range and resolution of the FLAT[14:0] latency adjustment word are: ±110 ps and 3.05 ps respectively. The Si5326 has two differential clock outputs. The electrical format of each clock output is independently programmable to support LVPECL, LVDS, CML, or CMOS loads. If not required, the second clock output can be powered down to minimize power consumption. The phase difference between the selected input clock and the output clocks is adjustable in 200 ps increments for system skew control. In addition, the phase of one output clock may be adjusted in relation to the phase of the other output clock. The resolution varies from 800 ps to 2.2 ns depending on the PLL divider settings. Consult the DSPLLsim configuration software to determine the phase offset resolution for a given input clock/clock multiplication ratio combination. For systemlevel debugging, a bypass mode is available which drives the output clock directly from the input clock, bypassing the internal DSPLL. The device is powered by a single 1.8, 2.5, or 3.3 V supply. 1.1. External Reference An external, high quality 38.88 MHz clock or a low-cost 114.285 MHz 3rd overtone crystal is used as part of a fixed-frequency oscillator within the DSPLL. This external reference is required for the device to perform jitter attenuation. Silicon Laboratories recommends using a high-quality crystal from TXC (www.txc.com.tw), part number 7MA1400014. An external 38.88 MHz clock from a high quality OCXO or TCXO can also be used as a reference for the device. In digital hold, the DSPLL remains locked to this external reference. Any changes in the frequency of this reference when the DSPLL is in digital hold will be tracked by the output of the device. Note that crystals can have temperature sensitivities. 1.2. Further Documentation Consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual (FRM) for more detailed information about the Si5326. The FRM can be downloaded from www.silabs.com/timing. Silicon Laboratories has developed a PC-based software utility called DSPLLsim to simplify device configuration, including frequency planning and loop bandwidth selection. This utility can be downloaded from www.silabs.com/timing. Confidential Rev. 0.2 Si5326 CKOUT1– CKOUT1+ NC VDD GND NC CKOUT2– CKOUT2+ CMODE 2. Pin Descriptions: Si5326 36 35 34 33 32 31 30 29 28 RST 1 27 SDI NC 2 26 A2_SS INT_C1B 3 25 A1 C2B 4 VDD 5 24 A0 XA 6 XB 7 GND 8 20 INC NC 9 19 DEC GND Pad 23 SDA_SDO 22 SCL 21 CS_CA LOL CKIN1– CKIN1+ RATE1 NC CKIN2– CKIN2+ VDD RATE0 10 11 12 13 14 15 16 17 18 Pin numbers are preliminary and subject to change. Pin # Pin Name I/O Signal Level Description 1 RST I LVCMOS External Reset. Active low input that performs external hardware reset of device. Resets all internal logic to a known state and forces the device registers to their default value. Clock outputs are tristated during reset. After rising edge of RST signal, the Si5326 will perform an internal self-calibration. This pin has a weak pull-up. 2, 9, 14, 30, 33 NC — — 3 INT_C1B O LVCMOS No Connect. This pin must be left unconnected for normal operation. Interrupt/CKIN1 Invalid Indicator. This pin functions as a device interrupt output or an alarm output for CKIN1. If used as an interrupt output, INT_PIN must be set to 1. The pin functions as a maskable interrupt output with active polarity controlled by the INT_POL register bit. If used as an alarm output, the pin functions as a LOS (and optionally FOS) alarm indicator for CKIN1. Set CK1_BAD_PIN = 1 and INT_PIN = 0. 0 = CKIN1 present. 1 = LOS (FOS) on CKIN1. The active polarity is controlled by CK_BAD_POL. If no function is selected, the pin tristates. Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5326 Register Map. Confidential Rev. 0.2 7 Si5326 Pin # Pin Name I/O Signal Level Description 4 C2B O LVCMOS CKIN2 Invalid Indicator. This pin functions as a LOS (and optionally FOS) alarm indicator for CKIN2 if CK2_BAD_PIN = 1. 0 = CKIN2 present. 1 = LOS (FOS) on CKIN2. The active polarity can be changed by CK_BAD_POL. If CK2_BAD_PIN = 0, the pin tristates. 5, 10, 32 VDD VDD Supply Supply. The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capacitors should be associated with the following Vdd pins: 5 0.1 µF 10 0.1 µF 32 0.1 µF A 1.0 µF should be placed as close to the device as is practical. 7 6 XB XA I Analog External Crystal or Reference Clock. External crystal should be connected to these pins to use internal oscillator based reference. If external reference is used, apply reference clock to XA input and leave XB pin floating. External reference must be from a high-quality clock source (TCXO, OCXO). Frequency of crystal or external clock is set by RATE[1:0] pins. 8, 31 GND GND Supply Ground. Must be connected to system ground. Minimize the ground path impedance for optimal performance of this device. 11 15 RATE0 RATE1 I 3-Level External Crystal or Reference Clock Rate. Three level inputs that select the type and rate of external crystal or reference clock to be applied to the XA/XB port. LM = 38.88 MHz external clocks MM = 114.285 MHz 3rd OT crystal HH = converts part to Si5325, and no external crystal or reference is needed 16 17 CKIN1+ CKIN1– I Multi Clock Input 1. Differential input clock. This input can also be driven with a singleended signal. Input frequency range is 2 kHz to 710 MHz. 12 13 CKIN2+ CKIN2– I Multi Clock Input 2. Differential input clock. This input can also be driven with a singleended signal. Input frequency range is 2 kHz to 710 MHz. 18 LOL O LVCMOS PLL Loss of Lock Indicator. This pin functions as the active high PLL loss of lock indicator if the LOL_PIN register bit is set to 1. 0 = PLL locked. 1 = PLL unlocked. If LOL_PIN = 0, this pin will tristate. Active polarity is controlled by the LOL_POL bit. The PLL lock status will always be reflected in the LOL_INT read only register bit. Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5326 Register Map. 8 Confidential Rev. 0.2 Si5326 Pin # Pin Name I/O Signal Level Description 19 DEC I LVCMOS Latency Decrement. A pulse on this pin decreases the input to output device latency by 1/fOSC (approximately 200 ps). There is no limit on the range of latency adjustment by this method. Pin control is enabled by setting INCDEC_PIN = 1. If INCDEC_PIN = 0, this pin is ignored and output latency is controlled via the CLAT register. If both INC and DEC are tied high, phase buildout is disabled and the device maintains a fixed-phase relationship between the selected input clock and the output clock during an input clock switch. This pin has a weak pull-down. 20 INC I LVCMOS Latency Increment. A pulse on this pin increases the input to output device latency by 1/fOSC (approximately 200 ps). There is no limit on the range of latency adjustment by this method. Pin control is enabled by setting INCDEC_PIN = 1. If INCDEC_PIN = 0, this pin is ignored and output latency is controlled via the CLAT register. If both INC and DEC are tied high, phase buildout is disabled and the device maintains a fixed-phase relationship between the selected input clock and the output clock during an input clock switch. This pin has a weak pull-down. 21 CS_CA I/O LVCMOS Input Clock Select/Active Clock Indicator. In manual clock selection mode, this pin functions as the manual input clock selector if the CKSEL_PIN is set to 1. 0 = Select CKIN1. 1 = Select CKIN2. If CKSEL_PIN = 0, the CKSEL_REG register bit controls this function and this input tristates. In automatic clock selection mode, this pin indicates which of the two input clocks is currently the active clock. If alarms exist on both clocks, CK_ACTV will indicate the last active clock that was used before entering the digital hold state. The CK_ACTV_PIN register bit must be set to 1 to reflect the active clock status to the CK_ACTV output pin. 0 = CKIN1 active input clock. 1 = CKIN2 active input clock. If CK_ACTV_PIN = 0, this pin will tristate. The CK_ACTV status will always be reflected in the CK_ACTV_REG read only register bit. This pin has a weak pull-down. 22 SCL I LVCMOS Serial Clock/Serial Clock. This pin functions as the serial clock input for both SPI and I2C modes. Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5326 Register Map. Confidential Rev. 0.2 9 Si5326 Pin # Pin Name I/O Signal Level Description 23 SDA_SDO I/O LVCMOS Serial Data. In I2C control mode (CMODE = 0), this pin functions as the bidirectional serial data port. In SPI control mode (CMODE = 1), this pin functions as the serial data output. 25 24 A1 A0 I LVCMOS Serial Port Address. In I2C control mode (CMODE = 0), these pins function as hardware controlled address bits. In SPI control mode (CMODE = 1), these pins are ignored. 26 A2_SS I LVCMOS Serial Port Address/Slave Select. In I2C control mode (CMODE = 0), this pin functions as a hardware controlled address bit. In SPI control mode (CMODE = 1), this pin functions as the slave select input. 27 SDI I LVCMOS Serial Data In. In I2C control mode (CMODE = 0), this pin is ignored. In SPI control mode (CMODE = 1), this pin functions as the serial data input. 29 28 CKOUT1– CKOUT1+ O Multi Output Clock 1. Differential output clock with a frequency range of 10 MHz to 1.4175 GHz. Output signal format is selected by SFOUT1_REG register bits. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. 34 35 CKOUT2– CKOUT2+ O Multi Output Clock 2. Differential output clock with a frequency range of 10 MHz to 1.4175 GHz. Output signal format is selected by SFOUT2_REG register bits. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. 36 CMODE I LVCMOS GND PAD GND GND Supply Control Mode. Selects I2C or SPI control mode for the Si5326. 0 = I2C Control Mode 1 = SPI Control Mode Ground Pad. The ground pad must provide a low thermal and electrical impedance to a ground plane. Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5326 Register Map. 10 Confidential Rev. 0.2 Si5326 3. Ordering Guide Ordering Part Number Output Clock Frequency Range Package Temperature Range Si5326A-B-GM 2 kHz–945 MHz 970–1134 MHz 1.213–1.417 GHz 36-Lead 6 x 6 mm QFN –40 to 85 °C Si5326B-B-GM 2 kHz–808 MHz 36-Lead 6 x 6 mm QFN –40 to 85 °C Si5326C-B-GM 2 kHz–346 MHz 36-Lead 6 x 6 mm QFN –40 to 85 °C Confidential Rev. 0.2 11 Si5326 4. Package Outline: 36-Pin QFN Figure 4 illustrates the package details for the Si5326. Table 3 lists the values for the dimensions shown in the illustration. Figure 4. 36-Pin Quad Flat No-lead (QFN) Table 3. Package Dimensions Symbol Millimeters Symbol Millimeters Min Nom Max A 0.80 0.85 0.90 A1 0.00 0.01 0.05 θ — — 12º b 0.18 0.23 0.30 aaa — — 0.10 bbb — — 0.10 ccc — — 0.05 D D2 6.00 BSC 3.95 4.10 4.25 L Min Nom Max 0.50 0.60 0.75 e 0.50 BSC ddd — — 0.10 E 6.00 BSC eee — — 0.05 E2 3.95 4.10 4.25 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-220, variation VJJD. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. 12 Confidential Rev. 0.2 Si5326 5. Recommended PCB Layout Figure 5. PCB Land Pattern Diagram Confidential Rev. 0.2 13 Si5326 Table 4. PCB Land Pattern Dimensions Dimension MIN MAX e 0.50 BSC. E 5.42 REF. D 5.42 REF. E2 4.00 4.20 D2 4.00 4.20 GE 4.53 — GD 4.53 — X — 0.28 Y 0.89 REF. ZE — 6.31 ZD — 6.31 Notes (General): 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Notes (Solder Mask Design): 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Notes (Stencil Design): 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. Notes (Card Assembly): 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. 14 Confidential Rev. 0.2 Si5326 DOCUMENT CHANGE LIST Revision 0.1 to Revision 0.2 Updated LVTTL to LVCMOS is Table 2, “Absolute Maximum Ratings,” on page 3. Added Figure 1, “Typical Phase Noise Plot,” on page 4. Updated Figure 2, “Si5326 Typical Application Circuit (I2C Control Mode),” and Figure 3, “Si5326 Typical Application Circuit (SPI Control Mode),” on page 5 to show preferred external reference interface. Updated “2. Pin Descriptions: Si5326”. Added RATE0 and changed RATE to RATE1 and expanded RATE[1:0] description. Changed font of register names to underlined italics. Updated "3. Ordering Guide" on page 11. Added "4. Package Outline: 36-Pin QFN" on page 12. Added “5. Recommended PCB Layout”. Confidential Rev. 0.2 15 Si5326 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: [email protected] Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. 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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 16 Confidential Rev. 0.2