a FEATURES Fast Throughput Rate: 1 MSPS Specified for VDD of 3 V and 5 V Low Power at Max Throughput Rate: 3.75 mW Max at 833 kSPS with 3 V Supplies 9 mW Max at 1 MSPS with 5 V Supplies Fully Differential Analog Input Wide Input Bandwidth: 70 dB SINAD at 300 kHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays High-Speed Serial Interface—SPITM/QSPITM MICROWIRETM/DSP Compatible Power-Down Mode: 1 A Max 8-Lead SOIC and SOIC Packages APPLICATIONS Transducer Interface Battery-Powered Systems Data Acquisition Systems Portable Instrumentation Motor Control Communications Differential Input, 1 MSPS 12-Bit ADC in SOIC-8 and SO-8 AD7450 FUNCTIONAL BLOCK DIAGRAM VDD VIN+ T/H VIN– 12-BIT SUCCESSIVE APPROXIMATION ADC VREF AD7450 SCLK CONTROL LOGIC SDATA CS GND GENERAL DESCRIPTION The AD7450 is a 12-bit, high-speed, low power, successive approximation (SAR) analog-to-digital converter that features a fully differential analog input. It operates from a single 3 V or 5 V power supply and features throughput rates up to 833 kSPS or 1 MSPS, respectively. The AD7450 uses advanced design techniques to achieve low power dissipation at high throughput rates. This part contains a low noise, wide bandwidth, differential trackand-hold amplifier (T/H) that can handle input frequencies in excess of 1 MHz with the –3 dB point typically being 20 MHz. The reference voltage for the AD7450 is applied externally to the VREF pin and can be varied from 100 mV to 3.5 V, depending on the power supply and what suits the application. The value of the reference voltage determines the common-mode voltage range of the part. With this truly differential input structure and variable reference input, the user can select a variety of input ranges and bias points. 2. High throughput with low power consumption. With a 3 V supply, the AD7450 offers 3.75 mW max power consumption for 833 kSPS throughput. The conversion and data acquisition processes are controlled using CS and the serial clock, allowing the device to interface with microprocessors or DSPs. The input signals are sampled on the falling edge of CS, and the conversion is also initiated at this point. The SAR architecture of this part ensures that there are no pipeline delays. PRODUCT HIGHLIGHTS 1. Operation with either 3 V or 5 V power supplies. 3. Fully differential analog input. 4. Flexible power/serial clock speed management. The conversion rate is determined by the serial clock, allowing the power to be reduced as the conversion time is reduced through the serial clock speed increase. This part also features a shutdown mode to maximize power efficiency at lower throughput rates. 5. Variable voltage reference input. 6. No pipeline delay. 7. Accurate control of the sampling instant via a CS input and once-off conversion control. 8. ENOB > 8 bits typically with 100 mV reference. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/461/3113 © Analog Devices, Inc., 2002 AD7450–SPECIFICATIONS1(V DD = 2.7 V to 3.3 V, fSCLK = 15 MHz, fS = 833 kSPS, VREF = 1.25 V, FIN = 200 kHz; VDD = 4.75 V to 5.25 V, fSCLK = 18 MHz, fS = 1 MSPS, VREF = 2.5 V, FIN = 300 kHz; VCM2 = VREF; TA = TMIN to TMAX, unless otherwise noted.) Parameter DYNAMIC PERFORMANCE Signal-to-(Noise + Distortion) Ratio (SINAD)3 Total Harmonic Distortion (THD)3 Peak Harmonic or Spurious Noise3 Intermodulation Distortion (IMD)3 Second Order Terms Third Order Terms Aperture Delay3 Aperture Jitter3 Full Power Bandwidth3 Conditions/Comments A Version B Version Unit VDD = 5 V VDD = 3 V VDD = 5 V, –80 dB typ VDD = 3 V, –78 dB typ VDD = 5 V, –82 dB typ VDD = 3 V, –80 dB typ 70 68 –75 –73 –75 –73 70 68 –75 –73 –75 –73 dB min dB min dB max dB max dB max dB max @ –3 dB @ –0.1 dB –85 –85 10 50 20 2.5 –85 –85 10 50 20 2.5 dB typ dB typ ns typ ps typ MHz typ MHz typ –87 –87 dB typ 12 ±2 12 ±1 Bits LSB max Guaranteed No Missed Codes to 12 Bits VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V –1/+2 ±3 ±6 ±3 ±6 ±3 ±6 ±1 ±3 ±6 ±3 ±6 ±3 ±6 LSB max LSB max LSB max LSB max LSB max LSB max LSB max 2 ⫻ VREF5 VIN+ – VIN– VIN+ – VIN– V VCM2 = VREF VCM2 = VREF VCM ± VREF/2 VCM ± VREF/2 ±1 20 6 VCM ± VREF/2 VCM ± VREF/2 ±1 20 6 V V µA max pF typ pF typ 2.56 2.56 V 1.257 ±1 15 1.257 ±1 15 V µA max pF typ 2.4 0.8 ±1 10 2.4 0.8 ±1 10 V min V max µA max pF max 2.8 2.4 0.4 ±1 10 Two’s Complement 2.8 2.4 0.4 ±1 10 Two’s Complement V min V min V max µA max pF max Power Supply Rejection Ratio (PSRR)3, 4 DC ACCURACY Resolution Integral Nonlinearity (INL)3 Differential Nonlinearity (DNL)3 Zero Code Error3 Positive Gain Error3 Negative Gain Error3 ANALOG INPUT Full-Scale Input Span Absolute Input Voltage VIN+ VIN– DC Leakage Current Input Capacitance REFERENCE INPUT VREF Input Voltage When in Track When in Hold 5 V supply (± 1% tolerance for specified performance) 3 V supply (± 1% tolerance for specified performance) DC Leakage Current VREF Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN8 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance8 Output Coding Typically 10 nA, VIN = 0 V or VDD VDD = 5 V, ISOURCE = 200 µA VDD = 3 V, ISOURCE = 200 µA ISINK = 200 µA –2– Rev. A AD7450 Parameter CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time3, 8 Throughput Rate9 POWER REQUIREMENTS VDD IDD10, 11 Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode Power Dissipation Normal Mode (Operational) Full Power-Down Mode Conditions/Comments A Version B Version Unit 888 ns with an 18 MHz SCLK 1.07 µs with a 15 MHz SCLK Sine Wave Input 16 16 SCLK Cycles 200 200 ns max VDD = 5 V VDD = 3 V 1 833 1 833 MSPS max kSPS max Range: 3 V ± 10%; 5 V ± 5% 3/5 3/5 V min/max VDD = 3 V/5 V SCLK; ON or OFF VDD = 5 V; fSAMPLE = 1 MSPS VDD = 3 V; fSAMPLE = 833 kSPS SCLK ON or OFF 0.5 1.8 1.25 1 0.5 1.8 1.25 1 mA typ mA max mA max µA max VDD = 5 V; fSAMPLE = 1 MSPS; 1.38 mW typ for 100 KSPS10 VDD = 3 V; fSAMPLE = 833 kSPS; 0.53 mW typ for 100 KSPS10 VDD = 5 V; SCLK ON or OFF VDD = 3 V; SCLK ON or OFF 9 9 mW max 3.75 3.75 mW max 5 3 5 3 µW max µW max NOTES 1 Temperature range is as follows: A and B Versions: –40°C to +85°C. 2 Common-mode voltage. The input signal can be centered on any choice of dc common-mode voltage as long as this value is in the range specified in Figures 8 and 9. 3 See Terminology section. 4 A 200 mV p-p sine wave, varying in frequency from 1 kHz to 200 kHz is coupled onto VDD. A 2.2 nF capacitor is used to decouple VDD to GND. 5 If the input spans of V IN+ and VIN– are both VREF, and they are 180° out of phase, the differential voltage is 2 ⫻ VREF. 6 The AD7450 is functional with a reference input from 100 mV and for V DD = 5 V, the reference can range up to 3.5 V (see References section). 7 The AD7450 is functional with a reference input from 100 mV and for V DD = 3 V, the reference can range up to 2.2 V (see References section). 8 Sample tested @ 25°C to ensure compliance. 9 See Serial Interface section. 10 See Power Versus Throughput Rate section. 11 Measured with a midscale dc input. Rev. A –3– AD7450 TIMING SPECIFICATIONS1, 2 (VDD = 2.7 V to 3.3 V, fSCLK = 15 MHz, fS = 833 kSPS, VREF = 1.25 V; VDD = 4.75 V to 5.25 V, fSCLK = 18 MHz, fS = 1 MSPS, VREF = 2.5 V; VCM3 = VREF; TA = TMIN to TMAX, unless otherwise noted.) Parameter fSCLK4 tCONVERT tQUIET t1 t2 t3 5 t4 5 t5 t6 t7 t8 6 tPOWER-UP7 Limit at TMIN, TMAX 3V 5V Unit Description 50 15 16 ⫻ tSCLK 1.07 25 50 18 16 ⫻ tSCLK 0.88 25 kHz min MHz max µs max ns min 10 10 20 40 0.4 tSCLK 0.4 tSCLK 10 10 35 1 10 10 20 40 0.4 tSCLK 0.4 tSCLK 10 10 35 1 ns min ns min ns max ns max ns min ns min ns min ns min ns max µs max tSCLK = 1/fSCLK SCLK = 15 MHz, 18 MHz Minimum Quiet Time between the End of a Serial Read and the Next Falling Edge of CS Minimum CS Pulsewidth CS Falling Edge to SCLK Falling Edge Setup Time Delay from CS Falling Edge until SDATA Three-State Disabled Data Access Time after SCLK Falling Edge SCLK High Pulsewidth SCLK Low Pulsewidth SCLK Edge to Data Valid Hold Time SCLK Falling Edge to SDATA Three-State Enabled SCLK Falling Edge to SDATA Three-State Enabled Power-Up Time from Full Power-Down NOTES 1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. 2 See Figure 1 and the Serial Interface section. 3 Common-mode voltage. 4 Mark/space ratio for the SCLK input is 40/60 to 60/40. 5 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V, and the time for an output to cross 0.4 V or 2.0 V for VDD = 3 V. 6 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 7 See Power-Up Time section. Specifications subject to change without notice. t1 CS tCONVERT t2 t5 SCLK 1 2 3 4 5 13 14 t7 t3 SDATA 0 15 16 t8 t6 tQUIET t4 0 0 0 DB11 DB10 DB2 DB1 DB0 THREE-STATE 4 LEADING ZEROS Figure 1. Serial Interface Timing Diagram –4– Rev. A AD7450 ABSOLUTE MAXIMUM RATINGS 1 Lead Temperature, Soldering Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . . 215oC Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220oC ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 kV (TA = 25°C, unless otherwise noted.) VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V VIN+ to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V VIN– to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Digital Input Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V Digital Output Voltage to GND . . . . . –0.3 V to VDD + 0.3 V VREF to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Input Current to Any Pin Except Supplies2 . . . . . . . ± 10 mA Operating Temperature Range Commercial (A and B Version) . . . . . . . . . –40oC to +85oC Storage Temperature Range . . . . . . . . . . . . –65oC to +150oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC SOIC, µSOIC Package, Power Dissipation . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . . . . . 157°C/W (SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 205.9°C/W (µSOIC) JC Thermal Impedance . . . . . . . . . . . . . . . . . 56°C/W (SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 43.74°C/W (µSOIC) NOTES 1 Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch up. 200A IOL TO OUTPUT PIN 1.6V CL 50pF 200A IOH Figure 2. Load Circuit for Digital Output Timing Specifications CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7450 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A –5– WARNING! ESD SENSITIVE DEVICE AD7450 PIN CONFIGURATION VREF 1 VIN+ 2 AD7450 8 VDD 7 SCLK TOP VIEW VIN– 3 (Not to Scale) 6 SDATA GND 4 5 CS PIN FUNCTION DESCRIPTION Pin Number Mnemonic Function 1 VREF Reference Input for the AD7450. An external reference must be applied to this input. For a 5 V power supply, the reference is 2.5 V (± 1%), and for a 3 V power supply, the reference is 1.25 V (± 1%) for specified performance. This pin should be decoupled to GND with a capacitor of at least 0.1 µF. See the References section for more details. 2 VIN+ Positive Terminal for Differential Analog Input 3 VIN– Negative Terminal for Differential Analog Input 4 GND Analog Ground. Ground reference point for all circuitry on the AD7450. All analog input signals and any external reference signal should be referred to this GND voltage. 5 CS Chip Select. Active low logic input. This input provides the dual function of initiating a conversion on the AD7450 and framing the serial data transfer. 6 SDATA Serial Data. Logic output. The conversion result from the AD7450 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists of four leading zeros followed by the 12 bits of conversion data that is provided MSB first. The output coding is two’s complement. 7 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the AD7450’s conversion process. 8 VDD Power Supply Input. VDD is 3 V (± 10%) or 5 V (± 5%). This supply should be decoupled to GND with a 0.1 µF capacitor and a 10 µF tantalum capacitor. –6– Rev. A AD7450 TERMINOLOGY Signal-to-(Noise + Distortion) Ratio Aperture Jitter This is the sample-to-sample variation in the effective point in time at which the actual sample is taken. This is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Full Power Bandwidth The full power bandwidth of an ADC is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 0.1 dB or 3 dB for a full-scale input. Common-Mode Rejection Ratio (CMRR) The common-mode rejection ratio is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 200 mV p-p sine wave applied to the common-mode voltage of VIN+ and VIN– of frequency fs: Signal–to–(Noise + Distortion) = (6.02 N + 1.76) dB Thus, for a 12-bit converter, this is 74 dB. CMRR( dB ) = 10 log ( Pf /Pfs ) Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7450, it is defined as: 2 THD (dB ) = 20 log 2 2 2 V2 + V3 + V4 + V5 + V6 Pf is the power at the frequency f in the ADC output; Pfs is the power at frequency fs in the ADC output. Integral Nonlinearity (INL) 2 This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. V1 where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second to the sixth harmonics. Differential Nonlinearity (DNL) This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Peak Harmonic or Spurious Noise Zero Code Error Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it will be a noise peak. This is the deviation of the last code transition (011...110 to 011...111) from the ideal VIN+ – VIN– (i.e., +VREF – 1 LSB), after the zero code error has been adjusted out. Intermodulation Distortion Negative Gain Error With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where m and n = 0, 1, 2, or 3. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa – fb), while the third order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa –2fb). This is the deviation of the first code transition (100...000 to 100...001) from the ideal VIN+ – VIN– (i.e., –VREF + 1 LSB), after the zero code error has been adjusted out. This is the deviation of the midscale code transition (111...111 to 000...000) from the ideal VIN+ – VIN– (i.e., 0 LSB). Positive Gain Error Track and Hold Acquisition Time The track and hold acquisition time is the minimum time required for the track and hold amplifier to remain in track mode for its output to reach and settle to within 0.5 LSB of the applied input signal. The AD7450 is tested using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used. In this case, the second order terms are usually distanced in frequency from the original sine waves, while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs. Power Supply Rejection Ratio (PSRR) The power supply rejection ratio is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 200 mV p-p sine wave applied to the ADC VDD supply of frequency fS. PSRR ( dB ) = 10 log ( Pf /Pfs ) Pf is the power at frequency f in the ADC output; Pfs is the power at frequency fs in the ADC output. Aperture Delay This is the amount of time from the leading edge of the sampling clock until the ADC actually takes the sample. Rev. A –7– AD7450–Typical Performance Characteristics (Default Conditions: TA = 25C) 0 0 –60 –67 –60 –80 –71 –100 –100 –73 –120 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY – kHz TPC 1. Dynamic Performance at 1 MSPS with VDD = 5 V 0 50 100 150 200 250 300 FREQUENCY – kHz 0.8 0.6 0.6 0.6 0.4 0.4 0.4 0 –0.2 –0.4 INL ERROR – LSB 1.0 0.8 DNL ERROR – LSB 1.0 0.8 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 3072 –1.0 0 4096 TPC 4. Typical Differential Nonlinearity (DNL) VDD = 5 V 1024 2048 CODE 3072 4096 0 TPC 5. Typical Differential Nonlinearity (DNL) VDD = 3 V 1024 2048 CODE 3072 4096 TPC 6. Typical Integral Nonlinearity (INL) VDD = 5 V 1.5 1.0 1.0 0.8 1.0 0.4 0.2 0 –0.2 –0.4 POSITIVE DNL 0.5 0 NEGATIVE DNL –0.5 –0.6 CHANGE IN DNL-LSB CHANGE IN DNL-LSB 0.6 INL ERROR – LSB –0.4 –0.8 2048 CODE 1000 0 –0.8 1024 100 INPUT FREQUENCY – kHz –0.2 –0.6 0 VDD = 5.25V 0.2 –0.6 –1.0 VDD = 3.3V TPC 3. SINAD vs. Analog Frequency for Various Supply Voltages 1.0 0.2 VDD = 4.75V –75 10 350 TPC 2. Dynamic Performance at 833 kSPS with VDD = 3 V VDD = 2.7V –69 –80 –120 DNL ERROR – LSB –65 fIN = 300kHz SINAD = 70.2dB THD = –82dB PK NOISE = –87.1dB –40 SNR – dBs –40 SNR – dBs –20 fIN = 300kHz SINAD = 71.7dB THD = –82.8dB PK NOISE = –85.3dB SINAD – dB –20 –63 8192 POINT FFT fSAMPLE = 833kSPS 8192 POINT FFT fSAMPLE = 1MSPS POSITIVE DNL 0.5 0 –0.5 NEGATIVE DNL –0.8 –1.0 –1.0 0 1024 2048 CODE 3072 4096 TPC 7. Typical Integral Nonlinearity (INL) VDD = 3 V –1.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VREF TPC 8. Change in DNL vs. Reference Voltage VDD = 5 V –8– 0 0.6 1.2 VREF 1.8 2.4 TPC 9. Change in DNL vs. Reference Voltage VDD = 3.3 V* Rev. A AD7450 1.5 1 2.0 0 1.5 –1 0.5 0 –0.5 NEGATIVE INL 1.0 POSITIVE INL 0.5 0 –0.5 NEGATIVE INL –1.0 –1.5 0 0.5 1.0 1.5 2.0 2.5 3.0 9,000 8,000 0 0.6 1.2 VREF 7,000 8,000 7,000 6,000 6,000 5,000 5,000 4,000 4,000 3,000 3,000 2,000 2,000 1,000 1,000 0 2044 2045 2046 2047 CODE 2048 2049 TPC 13. Histogram of the Output Codes with a DC Input for VDD = 5 V VIN = V IN– 10,000 CONVERSIONS fS = 833kSPS 0 2044 90 CODES 71 CODES 2046 2047 CODE –7 0.75 1.25 1.75 2.25 VREF 2.75 3.25 3.50 TPC 12. Change in Zero-Code Error vs. Reference Voltage VDD = 5 V and 3.3 V* 11 VDD = 5V fS = 1MSPS 10 9 8 VDD = 3.3V fS = 833kSPS 7 6 2048 2049 TPC 14. Histogram of the Output Codes with a DC Input for VDD = 3 V VDD = 3V 50 40 30 20 10 10,000 TPC 16. CMRR vs. Input Frequency for VDD = 5 V and 3 V *See References section. Rev. A –6 0 2045 60 100 1,000 FREQUENCY – kHz –5 12 VDD = 5V 80 0 10 2.4 9,839 CODES 90 70 1.8 TPC 11. Change in INL vs. Reference Voltage VDD = 3.3 V* 9,000 VIN = V IN– 10,000 CONVERSIONS fS = 1MSPS –4 –1.5 EFFECTIVE NUMBER OF BITS 10,000 CODES fS = 833kSPS –3 –8 10,000 10,000 VDD = 3.3V –2 –9 0.25 3.5 TPC 10. Change in INL vs. Reference Voltage VDD = 5 V fS = 1MSPS –1.0 VREF CMRR – dB ZERO-CODE ERROR – LSB POSITIVE INL CHANGE IN INL-LSB CHANGE IN INL-LSB 1.0 VDD = 5V –9– 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VREF TPC 15. Change in ENOB vs. Reference Voltage VDD = 5 V and 3.3 V* AD7450 CIRCUIT INFORMATION CAPACITIVE DAC The AD7450 is a fast, low power, single-supply, 12-bit successive approximation analog-to-digital converter (ADC). It can operate with a 5 V and 3 V power supply and is capable of throughput rates up to 1 MSPS and 833 kSPS when supplied with an 18 MHz or 15 MHz clock, respectively. This part requires an external reference to be applied to the VREF pin, with the value of the reference chosen depending on the power supply and what suits the application. When operated with a 5 V supply, the maximum reference that can be applied to the part is 3.5 V, and when operated with a 3 V supply, the maximum reference that can be applied to the part is 2.2 V. (See the References section.) B VIN+ VIN– B VIN– 1LSB = 2 VREF/4096 011...111 ADC CODE 011...110 B 000...001 000...000 111...111 100...010 100...001 100...000 –VREF + 1LSB 0LSB +VREF – 1LSB ANALOG INPUT (VIN+ – VIN–) Figure 5. Ideal Transfer Characteristics TYPICAL CONNECTION DIAGRAM COMPARATOR + CONTROL LOGIC SW3 CS The output coding for the AD7450 is two’s complement. The designed code transitions occur at successive LSB values (i.e., 1 LSB, 2 LSB, and so on), and the LSB size is 2 ⫻ VREF / 4096. The ideal transfer characteristic of the AD7450 is shown in Figure 5. CAPACITIVE DAC A SW1 A SW2 – ADC TRANSFER FUNCTION The AD7450 is a successive approximation ADC based on two capacitive DACs. Figures 3 and 4 show simplified schematics of the ADC in acquisition and conversion phase, respectively. The ADC is comprised of control logic, a SAR, and two capacitive DACs. In Figure 3 (the acquisition phase), SW3 is closed and SW1 and SW2 are in Position A, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input. VIN+ CONTROL LOGIC SW3 CAPACITIVE DAC CONVERTER OPERATION CS + A SW1 A SW2 Figure 4. ADC Conversion Phase The AD7450 has an on-chip differential track-and-hold amplifier, a successive approximation (SAR) ADC, and a serial interface that is housed in either an 8-lead SOIC or µSOIC package. The serial clock input accesses data from the part and also provides the clock source for the successive approximation ADC. The AD7450 features a power-down option for reduced power consumption between conversions. The power-down feature is implemented across the standard serial interface as described in the Modes of Operation section. B COMPARATOR CS – CS CAPACITIVE DAC Figure 3. ADC Acquisition Phase When the ADC starts a conversion (Figure 4), SW3 will open and SW1 and SW2 will move to Position B, causing the comparator to become unbalanced. Both inputs are disconnected once the conversion begins. The control logic and the charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC’s output code. The output impedances of the sources driving the VIN+ and VIN– pins must be matched; otherwise, the two inputs will have different settling times, resulting in errors. Figure 6 shows a typical connection diagram for the AD7450 for both 5 V and 3 V supplies. In this setup, the GND pin is connected to the analog ground plane of the system. The VREF pin is connected to either a 2.5 V or a 1.25 V decoupled reference source, depending on the power supply, to set up the analog input range. The common-mode voltage has to be set up externally and is the value that the two inputs are centered on. For more details on driving the differential inputs and setting up the common mode, see the Driving Differential Inputs section. The conversion result for the ADC is output in a 16-bit word consisting of four leading zeros followed by the MSB of the 12-bit result. For applications where power consumption is of concern, the power-down mode should be used between conversions, or bursts of several conversions, to improve power performance. See Modes of Operation section. –10– Rev. A AD7450 Figures 8 and 9 show how the common-mode range typically varies with VREF for both a 5 V and a 3 V power supply. The common mode must be in this range to guarantee the functionality of the AD7450. 3V/5V SUPPLY 0.1F 10F SERIAL INTERFACE VDD VREF p-p CM* VIN+ For ease of use, the common mode can be set up to be equal to VREF, resulting in the differential signal being ± VREF centered on VREF. When a conversion takes place, the common mode is rejected resulting in a virtually noise free signal of amplitude –VREF to +VREF corresponding to the digital codes of 0 to 4095. SCLK AD7450 C/P SDATA CS VREF p-p CM* VIN– 5.0 GND 4.5 COMMON-MODE RANGE – V VREF 1.25V/2.5V VREF 0.1F *CM = COMMON-MODE VOLTAGE Figure 6. Typical Connection Diagram 4.0 3.5 3.25V 3.0 COMMON-MODE RANGE 2.5 2.0 1.75V 1.5 1.0 THE ANALOG INPUT 0.5 The analog input of the AD7450 is fully differential. Differential signals have a number of benefits over single-ended signals, including noise immunity based on the device’s common-mode rejection, improvements in distortion performance, doubling of the device’s available dynamic range, and flexibility in input ranges and bias points. 0 0.25 0.75 1.25 1.75 2.25 2.75 3.25 3.50 VREF Figure 8. Input Common-Mode Range vs. VREF (VDD = 5 V and VREF (Max) = 3.5 V) Figure 7 defines the fully differential analog input of the AD7450. 3.0 2.5 VIN+ COMMON-MODE RANGE – V VREF p-p AD7450 VREF p-p VIN– COMMON-MODE VOLTAGE Figure 7. Differential Input Definition The amplitude of the differential signal is the difference between the signals applied to the VIN+ and VIN– pins (i.e., VIN+ – VIN–). VIN+ and VIN– are simultaneously driven by two signals each of amplitude VREF that are 180° out of phase. The amplitude of the differential signal is therefore –V REF to +V REF p-p (i.e., 2 ⫻ VREF). This is regardless of the common mode (CM). The common mode is the average of the two signals, i.e., (VIN+ + VIN–)/2, and is therefore the voltage that the two inputs are centered on. This results in the span of each input being CM ± VREF/2. This voltage has to be set up externally and its range varies with VREF. As the value of VREF increases, the common-mode range decreases. When driving the inputs with an amplifier, the actual common-mode range will be determined by the amplifier’s output voltage swing. Rev. A 2.0 2V COMMON-MODE RANGE 1.5 1.0 1V 0.5 0 0.25 0.50 0.75 1.00 1.25 VREF 1.50 1.75 2.00 2.20 Figure 9. Input Common-Mode Range vs. VREF (VDD = 3 V and VREF (Max) = 2.2 V) Figure 10 shows examples of the inputs to VIN+ and VIN– for different values of VREF for VDD = 5 V. It also gives the maximum and minimum common-mode voltages for each reference value according to Figure 8. –11– AD7450 total harmonic distortion (THD) that can be tolerated. The THD will increase as the source impedance increases and the performance will degrade. Figure 12 shows a graph of the THD versus the analog input signal frequency for different source impedances. REFERENCE = 1.25V VIN– COMMON-MODE (CM) CMMIN = 0.625V CMMAX = 4.42V COMMON-MODE (CM) CMMIN = 1.25V CMMAX = 3.75V 1.25V p-p VIN REFERENCE = 2.5V VIN– –70 TA = 25C VDD = 3V RIN = 1k 2.5V p-p –72 VIN –74 THD – dBs Figure 10. Examples of the Analog Inputs to VIN+ and VIN– for Different Values of VREF for VDD = 5 V Analog Input Structure Figure 11 shows the equivalent circuit of the analog input structure of the AD7450. The four diodes provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV. This will cause these diodes to become forward biased and start conducting into the substrate. These diodes can conduct up to 10 mA without causing irreversible damage to the part. The capacitors, C1, in Figure 11 are typically 4 pF and can primarily be attributed to pin capacitance. The resistors are lumped components made up of the ON resistance of the switches. The value of these resistors is typically about 100 Ω. The capacitors, C2, are the ADC’s sampling capacitors and have a capacitance of 16 pF typically. VDD = 3V RIN = 100 –76 –78 –80 VDD = 5V RIN = 100 –82 10 VDD = 5V RIN = 1k 100 INPUT FREQUENCY – kHz 1000 Figure 12. THD vs. Analog Input Frequency for Various Source Impedances for VDD = 5 V and 3 V –60 TA = 25C –65 –70 THD – dBs For ac applications, removing high-frequency components from the analog input signal is recommended by the use of an RC low-pass filter on the relevant analog input pins. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances will significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp will be a function of the particular application. Figure 13 shows a graph of the THD versus the analog input frequency for VDD of 5 V ± 5% and 3 V ± 10%, while sampling at 1 MSPS and 833 kSPS with a SCLK of 18 MHz and 15 MHz, respectively. In this case, the source impedance is 10 Ω. –75 VDD = 3.3V VDD = 2.7V –80 VDD –85 D R1 VDD = 5.25V C2 VIN+ C1 –95 10 D R1 C2 VIN– C1 100 INPUT FREQUENCY – kHz 1000 Figure 13. THD vs. Analog Input Frequency for 3 V ± 10% and 5 V ± 5% Supply Voltages VDD D VDD = 4.75V –90 D Figure 11. Equivalent Analog Input Circuit Conversion Phase—Switches Open Track Phase—Switches Closed When no amplifier is used to drive the analog input, the source impedance should be limited to values lower than 1 kΩ. The maximum source impedance will depend on the amount of DRIVING DIFFERENTIAL INPUTS Differential operation requires that VIN+ and VIN– be simultaneously driven with two equal signals that are 180o out of phase. The common mode must be set up externally and has a range that is determined by VREF, the power supply, and the particular amplifier used to drive the analog inputs (see Figures 8 and 9). Differential modes of operation with either an ac or dc input provide the best THD performance over a wide frequency range. Since not all applications have a signal preconditioned for differential operation, there is often a need to perform singleended-to-differential conversion. –12– Rev. A AD7450 3.75V 2.5V Rf1 1.25V Rs* Rg1 GND VIN+ VOCM +2.5V 51R Rg2 C* AD7450 AD8138 Rs* –2.5V VIN– C* Rf2 *MOUNT AS CLOSE TO THE AD7450 AS POSSIBLE AND ENSURE HIGH PRECISION Rs AND Cs ARE USED VREF 3.75V 2.5V 1.25V EXTERNAL VREF (2.5V) Rs – 50R; C – 1nF; Rg1 = Rf1 = Rf2 = 499R; Rg2 = 523R Figure 14. Using the AD8138 as a Single-Ended-to-Differential Amplifier Differential Amplifier An ideal method of applying differential drive to the AD7450 is to use a differential amplifier, such as the AD8138. This part can be used as a single-ended-to-differential amplifier or as a differentialto-differential amplifier. In both cases, the analog input needs to be bipolar. It also provides common-mode level shifting and buffering of the bipolar input signal. Figure 14 shows how the AD8138 can be used as a single-ended-to-differential amplifier. The positive and negative outputs of the AD8138 are connected to the respective inputs on the ADC via a pair of series resistors to minimize the effects of switched capacitance on the front end of the ADC. The RC low-pass filter on each analog input is recommended in ac applications to remove the high-frequency components of the analog input. The architecture of the AD8138 results in outputs that are highly balanced over a wide frequency range without requiring tightly matched external components. If the analog input source being used has zero impedance then all four resistors (Rg1, Rg2, Rf1, and Rf2) should be the same. If the source has a 50 Ω impedance and a 50 Ω termination, for example, the value of Rg2 should be increased by 25 Ω to balance this parallel impedance on the input and thus ensure that both the positive and negative analog inputs have the same gain (see Figure 14). The outputs of the amplifier are perfectly matched, balanced differential outputs of identical amplitude and exactly 180o out of phase. The voltage applied to Point A sets up the common-mode voltage. In both diagrams, it is connected in some way to the reference, but any value in the common-mode range can be input here to set up the common mode. Examples of suitable dual op amps that could be used in this configuration to provide differential drive to the AD7450 are the AD8042, AD8056, and AD8022. Care must be taken when choosing the op amp, since the selection will depend on the required power supply and the system performance objectives. The driver circuits in Figure 15a and Figure 15b are optimized for dc coupling applications requiring optimum distortion performance. The differential op amp driver circuit in Figure 15a is configured to convert and level shift a single-ended, ground referenced (bipolar) signal to a differential signal centered at the VREF level of the ADC. 390 V+ Op Amp Pair An op amp pair can be used to directly couple a differential signal to the AD7450. The circuit configurations shown in Figures 15a and 15b show how a dual op amp can be used to convert a single-ended signal into a differential signal for both a bipolar and a unipolar input signal, respectively. VDD 27 GND The AD8138 is specified with 3 V, 5 V, and ± 5 V power supplies, but the best results are obtained when it is supplied by ± 5 V. A lower cost device that could also be used in this configuration with slight differences in characteristics to the AD8138, but with similar performance and operation, is the AD8132. Rev. A 220 2 VREF p-p V– 220 VIN+ AD7450 220 VIN– 220 VREF V+ 27 A 0.1F V– 20k 10k EXTERNAL VREF Figure 15a. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Input into a Differential Input –13– AD7450 The circuit configuration shown in Figure 15b converts a unipolar, single-ended signal into a differential signal. Example 1: VIN max = VDD + 0.3 VIN max = VREF + VREF 2 220 2 VREF p-p V+ 390 If VDD = 5 V VDD 27 VREF ThenVIN max = 5.3V GND Therefore 3 × VREF 2 = 5.3 V V– VIN+ VREF max = 3.5V AD7450 220 VIN– 220 VREF Therefore, when operating at VDD = 5 V, the value of VREF can range from 100 mV to a maximum value of 3.5 V. When VDD = 4.75 V, VREF max = 3.37 V. V+ 0.1F 27 A Example 2: VIN max = VDD + 0.3 V– 10k VIN max = VREF + VREF 2 EXTERNAL VREF If VDD = 3.3 V ThenVIN max = 3.6 V Figure 15b. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Input into a Differential Input Therefore 3 × VREF 2 = 3.6 V VREF max = 2.4 V RF Transformer In systems that do not need to be dc-coupled, an RF transformer with a center tap offers a good solution for generating differential inputs. Figure 16 shows how a transformer is used for singleended-to-differential conversion. It provides the benefits of operating the ADC in the differential mode without contributing additional noise and distortion. An RF transformer also has the benefit of providing electrical isolation between the signal source and the ADC. A transformer can be used for most ac applications. The center tap is used to shift the differential signal to the common-mode level required. In this case, it is connected to the reference so the common-mode level is the value of the reference. 3.75V 2.5V 1.25V R R VIN+ C These examples show that the maximum reference applied to the AD7450 is directly dependant on the value of VDD. The performance of the part at different reference values is shown in TPC 8 to TPC 12 and in TPC 15. The value of the reference sets the analog input span and the common-mode voltage range. Errors in the reference source will result in gain errors in the AD7450 transfer function and will add to specified full-scale errors on the part. A capacitor of 0.1 µF should be used to decouple the VREF pin to GND. Table I lists examples of suitable voltage references to be used that are available from Analog Devices, and Figure 17 shows a typical connection diagram for the VREF pin. Table I. Examples of Suitable Voltage References AD7450 VIN– R Therefore, when operating at VDD = 3.3 V, the value of VREF can range from 100 mV to a maximum value of 2.4 V. When VDD = 2.7 V, VREF max = 2 V. 3.75V 2.5V Reference Output Voltage Initial Accuracy (% Max) Operating Current (A) 1.25V AD589 AD1580 REF192 REF43 AD780 1.235 1.225 2.5 2.5 2.5 1.2–2.8 0.08–0.8 0.08–0.4 0.06–0.1 0.04–0.2 50 50 45 600 1000 VREF EXTERNAL VREF (2.5V) Figure 16. Using an RF Transformer to Generate Differential Inputs VDD REFERENCES SECTION An external reference source is required to supply the reference to the AD7450. This reference input can range from 100 mV to 3.5 V. With a 5 V power supply, the specified reference is 2.5 V and the maximum reference is 3.5 V. With a 3.3 V power supply, the specified reference is 1.25 V and the maximum reference is 2.4 V. In both cases, the reference is functional from 100 mV. It is important to ensure that, when choosing the reference value for a particular application, the maximum analog input range (VIN max) is never greater than VDD + 0.3 V to comply with the maximum ratings of the part. The following two examples calculate the maximum VREF input that can be used when operating the AD7450 at VDD of 5 V and 3.3 V, respectively. AD780 NC VDD 0.1F 1 2 VIN 10nF 0.1F AD7450* O/P SEL 8 NC VREF 7 NC 3 TEMP VOUT 6 4 GND TRIM 5 NC 2.5V 0.1F NC = NO CONNECT *ADDITIONAL PINS OMITTED FOR CLARITY Figure 17. Typical VREF Connection Diagram for VDD = 5 V –14– Rev. A AD7450 SINGLE-ENDED OPERATION When supplied with a 5 V power supply, the AD7450 can handle a single-ended input. The design of this part is optimized for differential operation, so with a single-ended input, performance will degrade. Linearity will typically degrade by 0.2 LSBs, zero code and full-scale errors will typically degrade by 2 LSBs, and ac performance is not guaranteed. To operate the AD7450 in single-ended mode, the VIN+ input is coupled to the signal source, while the VIN– input is biased to the appropriate voltage corresponding to the midscale code transition. This voltage is the common mode, which is a fixed dc voltage (usually the reference). The VIN+ input swings around this value and should have voltage span of 2 ⫻ VREF to make use of the full dynamic range of the part. Therefore, the input signal will have peak-to-peak values of common mode ± VREF. If the analog input is unipolar then an op amp in a noninverting unity gain configuration can be used to drive the VIN+ pin. Because the ADC operates from a single supply, it is necessary to level shift ground based bipolar signals to comply with the input requirements. An op amp can be configured to rescale and level shift the ground based bipolar signal so it is compatible with the selected input range of the AD7450 (see Figure 18). +2.5V 0V VIN –2.5V Timing Example 1 Having fSCLK = 18 MHz and a throughput rate of 1 MSPS gives a cycle time of: 1 Throughput = 1 1, 000 , 000 = 1 µs A cycle consists of: t2 + 12.5 (1 fSCLK ) + t ACQ = 1 µs 10 ns + 12.5 (1 18 MHz ) + t ACQ = 1 µs 2.5V 0V R + R AD7450 VIN– EXTERNAL VREF (2.5V) t ACQ = 296 ns VIN+ – R This 296 ns satisfies the requirement of 200 ns for tACQ. From Figure 20, tACQ is comprised of: VREF 2.5 (1 fSCLK ) + t8 + tQUIET 0.1F where t8 = 35 ns. This allows a value of 122 ns for tQUIET, satisfying the minimum requirement of 25 ns. Figure 18. Applying a Bipolar Single-Ended Input to the AD7450 Timing Example 2 Having fSCLK = 5 MHz and a throughput rate of 315 kSPS gives a cycle time of: SERIAL INTERFACE Figure 19 shows a detailed timing diagram for the serial interface of the AD7450. The serial clock provides the conversion clock and also controls the transfer of data from the AD7450 during conversion. CS initiates the conversion process and frames the data transfer. The falling edge of CS puts the track-and-hold into hold mode and takes the bus out of three-state. The analog input is sampled and the conversion initiated at this point. The conversion will require 16 SCLK cycles to complete. Once 13 SCLK falling edges have occurred, the track-and-hold will go back into track on the next SCLK rising edge as shown at Point B in Figure 19. On the 16th SCLK falling edge, the SDATA line will go back into three-state. 1 Throughput = 1 315, 000 = 3.174 µs A cycle consists of: t2 + 12.5 (1 fSCLK ) + t ACQ = 3.174 µs Therefore if t2 is 10 ns then: 10 ns + 12.5 (1 5 MHz ) + t ACQ = 3.174 µs t ACQ = 664 ns This 664 ns satisfies the requirement of 200 ns for tACQ. From Figure 20, tACQ is comprised of: If the rising edge of CS occurs before 16 SCLKs have elapsed, the conversion will be terminated, and the SDATA line will go back into three-state. Sixteen serial clock cycles are required to perform a conversion and to access data from the AD7450. CS going low provides the first leading zero to be read in by the microcontroller or DSP. The remaining data is then clocked out on the subsequent SCLK falling edges beginning with the second leading zero. Thus, the first falling clock edge on the serial clock provides the second leading zero. The final bit in the data transfer Rev. A In applications with a slower SCLK, it may be possible to read in data on each SCLK rising edge, i.e., the first rising edge of SCLK after the CS falling edge would have the leading zero provided and the 15th SCLK edge would have DB0 provided. Therefore, if t2 = 10 ns then: 5V R is valid on the 16th falling edge, having been clocked out on the previous (15th) falling edge. Once the conversion is complete and the data has been accessed after the 16 clock cycles, it is important to ensure that before the next conversion is initiated, enough time is left to meet the acquisition and quiet time specifications (see timing examples). To achieve 1 MSPS with an 18 MHz clock for VDD = 5 V, an 18 clock burst will perform the conversion and leave enough time before the next conversion for the acquisition and quiet time. This is the same for achieving 833 kSPS with a 15 MHz clock for VDD = 3 V. 2.5 (1 fSCLK ) + t8 + tQUIET where t8 = 35 ns. This allows a value of 129 ns for tQUIET, satisfying the minimum requirement of 25 ns. As in this example and with other slower clock values, the signal may already be acquired before the conversion is complete, but it is still necessary to leave 25 ns minimum tQUIET between conversions. In Timing Example 2, the signal should be fully acquired at approximately Point C in Figure 20. –15– AD7450 t1 CS tCONVERT t2 B t5 SCLK 1 2 3 4 5 13 14 t7 0 16 t8 t6 tQUIET t4 t3 SDATA 15 0 0 0 DB11 DB10 DB2 DB1 DB0 THREE-STATE 4 LEADING ZEROS Figure 19. Serial Interface Timing Diagram CS tCONVERT SCLK 10ns t2 t5 1 2 3 4 C B 5 13 14 15 16 t8 t6 tQUIET tACQ 12.5(1/fSCLK) 1/THROUGHPUT Figure 20. Serial Interface Timing Example MODES OF OPERATION The mode of operation of the AD7450 is selected by controlling the logic state of the CS signal during a conversion. There are two possible modes of operation, normal mode and power-down mode. The point at which CS is pulled high after the conversion has been initiated will determine whether or not the AD7450 will enter the power-down mode. Similarly, if already in power-down, CS controls whether the device will return to normal operation or remain in power-down. These modes of operation are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for differing application requirements. Sixteen serial clock cycles are required to complete the conversion and access the complete conversion result. CS may idle high until the next conversion or idle low until sometime prior to the next conversion. Once a data transfer is complete, i.e., when SDATA has returned to three-state, another conversion can be initiated after the quiet time, tQUIET, has elapsed by again bringing CS low. CS SCLK 10 1 16 Normal Mode This mode is intended for the fastest throughput rate performance. The user does not have to worry about any power-up times since the AD7450 is kept fully powered up. Figure 21 shows the general diagram of the operation of the AD7450 in this mode. The conversion is initiated on the falling edge of CS as described in the Serial Interface section. To ensure the part remains fully powered up, CS must remain low until at least 10 SCLK falling edges have elapsed after the falling edge of CS. If CS is brought high any time after the 10th SCLK falling edge, but before the 16th SCLK falling edge, the part will remain powered up, but the conversion will be terminated and SDATA will go back into three-state. SDATA 4 LEADING ZEROS AND CONVERSION RESULT Figure 21. Normal Mode Operation Power-Down Mode This mode is intended for use in applications where slower throughput rates are required; either the ADC is powered down between each conversion or a series of conversions may be performed at a high throughput rate, during which the ADC is powered down for a relatively long duration between these bursts of several conversions. When the AD7450 is in the power-down mode, all analog circuitry is powered down. To enter power-down mode, the conversion process must be interrupted by bringing CS high anywhere after the second falling edge of SCLK and before the 10th falling edge of SCLK as shown in Figure 22. –16– Rev. A AD7450 track-and-hold, which was in hold mode while the part was powered down, returns to track mode after the first SCLK edge the part receives after the falling edge of CS. This is shown as Point A in Figure 23. CS 1 SCLK 2 10 Although at any SCLK frequency one dummy cycle is sufficient to power the device up and acquire VIN, it does not necessarily mean that a full dummy cycle of 16 SCLKs must always elapse to power up the device and acquire VIN fully; 1 µs will be sufficient to power the device up and acquire the input signal. THREE-STATE SDATA Figure 22. Entering Power-Down Mode Once CS has been brought high in this window of SCLKs, the part will enter power-down, the conversion that was initiated by the falling edge of CS will be terminated, and SDATA will go back into three-state. The time from the rising edge of CS to SDATA three-state enabled will never be greater than t8 (see Timing Specifications). If CS is brought high before the second SCLK falling edge, the part will remain in normal mode and will not power down. This will avoid accidental power-down due to glitches on the CS line. To exit this mode of operation and power the AD7450 up again, a dummy conversion is performed. On the falling edge of CS, the device will begin to power up and continue to power up as long as CS is held low until after the falling edge of the 10th SCLK. The device will be fully powered up after 1 µs has elapsed and, as shown in Figure 23, valid data will result from the next conversion. If CS is brought high before the 10th falling edge of SCLK, the AD7450 will again go back into power-down. This avoids accidental power-up due to glitches on the CS line or an inadvertent burst of eight SCLK cycles while CS is low. So although the device may begin to power up on the falling edge of CS, it will again power down on the rising edge of CS as long as it occurs before the 10th SCLK falling edge. Power-Up Time The power-up time of the AD7450 is typically 1 µs, which means that with any frequency of SCLK up to 18 MHz, one dummy cycle will always be sufficient to allow the device to power up. Once the dummy cycle is complete, the ADC will be fully powered up and the input signal will be acquired properly. The quiet time, tQUIET, must still be allowed from the point at which the bus goes back into three-state after the dummy conversion to the next falling edge of CS. When running at the maximum throughput rate of 1 MSPS, the AD7450 will power up and acquire a signal within ± 0.5 LSB in one dummy cycle, i.e., 1 µs. When powering up from the power-down mode with a dummy cycle, as in Figure 23, the For example, if a 5 MHz SCLK frequency was applied to the ADC, the cycle time would be 3.2 µs (i.e., 1/(5 MHz) ⫻ 16). In one dummy cycle, 3.2 µs, the part would be powered up and VIN acquired fully. However, after 1 µs with a 5 MHz SCLK, only 5 SCLK cycles would have elapsed. At this stage, the ADC would be fully powered up and the signal acquired. So, in this case, the CS can be brought high after the 10th SCLK falling edge and brought low again after a time, tQUIET, to initiate the conversion. When power supplies are first applied to the AD7450, the ADC may either power up in the power-down mode or normal mode. Because of this, it is best to allow a dummy cycle to elapse to ensure the part is fully powered up before attempting a valid conversion. Likewise, if the user wishes the part to power up in power-down mode, then the dummy cycle may be used to ensure the device is in power-down by executing a cycle such as that shown in Figure 22. Once supplies are applied to the AD7450, the power-up time is the same as that when powering up from the power-down mode. It takes approximately 1 µs to power up fully if the part powers up in normal mode. It is not necessary to wait 1 µs before executing a dummy cycle to ensure the desired mode of operation. Instead, the dummy cycle can occur directly after power is supplied to the ADC. If the first valid conversion is then performed directly after the dummy conversion, care must be taken to ensure that adequate acquisition time has been allowed. As mentioned earlier, when powering up from the power-down mode, the part will return to track upon the first SCLK edge applied after the falling edge of CS. However, when the ADC powers up initially after supplies are applied, the track-and-hold will already be in track. This means if (assuming one has the facility to monitor the ADC supply current) the ADC powers up in the desired mode of operation, and thus a dummy cycle is not required to change the mode, then a dummy cycle is not required to place the track-and-hold into track. tPOWER-UP CS SCLK THE PART IS FULLY POWERED UP WITH V IN FULLY ACQUIRED THE PART BEGINS TO POWER UP 1 10 16 1 10 A SDATA INVALID DATA VALID DATA Figure 23. Exiting Power-Down Mode Rev. A –17– 16 AD7450 POWER VERSUS THROUGHPUT RATE AD7450 to ADSP-21xx By using the power-down mode on the AD7450 when not converting, the average power consumption of the ADC decreases at lower throughput rates. Figure 24 shows how, as the throughput rate is reduced, the device remains in its power-down state longer, and the average power consumption reduces accordingly. It shows this for both 5 V and 3 V power supplies. The ADSP-21xx DSPs are interfaced directly to the AD7450 without any glue logic required. For example, if the AD7450 is operated in continuous sampling mode with a throughput rate of 100 kSPS and an SCLK of 18 MHz, and the device is placed in the power-down mode between conversions, then the power consumption is calculated as follows: Power dissipation during normal operation = 9 mW max for VDD = 5 V. If the power-up time is one dummy cycle, i.e., 1 µs, and the remaining conversion time is another cycle, i.e., 1 µs, then the AD7450 can be said to dissipate 9 mW for 2 µs* during each conversion cycle. The SPORT control register should be set up as follows: TFSW = RFSW = 1, Alternate Framing INVRFS = INVTFS = 1, Active Low Frame Signal DTYPE = 00, Right Justify Data SLEN = 1111, 16-Bit Data-Words ISCLK = 1, Internal Serial Clock TFSR = RFSR = 1, Frame Every Word IRFS = 0 ITFS = 1 To implement the power-down mode, SLEN should be set to 1001 to issue an 8-bit SCLK burst. The connection diagram is shown in Figure 25. The ADSP-21xx has the TFS and RFS of the SPORT tied together, with TFS set as an output and RFS set as an input. The DSP operates in alternate framing mode and the SPORT control register is set up as described. The frame synchronization signal generated on the TFS is tied to CS and, as with all signal processing applications, equidistant sampling is necessary. However, in this example, the timer interrupt is used to control the sampling rate of the ADC and, under certain conditions, equidistant sampling may not be achieved. If the throughput rate = 100 kSPS, then the cycle time = 10 µs, and the average power dissipated during each cycle is: (2/10) ⫻ 9 mW = 1.8 mW For the same scenario, if VDD = 3 V, the power dissipation during normal operation is 3.75 mW max. The AD7450 can now be said to dissipate 3.75 mW for 2 µs* during each conversion cycle. The average power dissipated during each cycle with a throughput rate of 100 kSPS is therefore: AD7450* ADSP-21xx* SCLK (2/10) ⫻ 3.75 mW = 0.75 mW SDATA This is how the power numbers in Figure 24 are calculated. CS For throughput rates above 320 kSPS, it is recommended that the serial clock frequency is reduced for optimum power performance. SCLK DR RFS TFS 100 *ADDITIONAL PINS OMITTED FOR CLARITY VDD = 5V SCLK = 18MHz Figure 25. Interfacing to the ADSP-21xx POWER – mW 10 1 VDD = 3V SCLK = 15MHz 0.1 0.01 0 50 100 150 200 250 THROUGHPUT – kSPS 300 350 Figure 24. Power vs. Throughput Rate for Power-Down Mode MICROPROCESSOR AND DSP INTERFACING The serial interface on the AD7450 allows the part to be directly connected to a range of different microprocessors. This section explains how to interface the AD7450 with some of the more common microcontroller and DSP serial interface protocols. *This figure assumes a very small time to enter power-down mode. This will increase as the burst of clocks used to enter the power-down mode is increased. The timer registers are loaded with a value that provides an interrupt at the required sample interval. When an interrupt is received, a value is transmitted with TFS/DT (ADC control word). The TFS is used to control the RFS and hence the reading of data. The frequency of the serial clock is set in the SCLKDIV register. When the instruction to transmit with TFS is given, (i.e., AX0 = TX0), the state of the SCLK is checked. The DSP will wait until the SCLK has gone High, Low, and High before transmission will start. If the timer and SCLK values are chosen such that the instruction to transmit occurs on or near the rising edge of SCLK, then the data may be transmitted, or it may wait until the next clock edge. For example, the ADSP-2111 has a master clock frequency of 16 MHz. If the SCLKDIV register is loaded with the value 3, then a SCLK of 2 MHz is obtained and eight master clock periods will elapse for every 1 SCLK period. If the timer registers are loaded with the value 803, then 100.5 SCLKs will occur between interrupts and subsequently between transmit instructions. This situation will result in nonequidistant sampling as the transmit instruction is occurring on a SCLK edge. If the number of SCLKs between interrupts is a whole integer figure of N, then equidistant sampling will be implemented by the DSP. –18– Rev. A AD7450 AD7450 to TMS320C5x/C54x AD7450 to DSP56xxx The serial interface on the TMS320C5x/C54x uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices, such as the AD7450. The CS input allows easy interfacing between the TMS320C5x/C54x and the AD7450 with no glue logic required. The serial port of the TMS320C5x/C54x is set up to operate in burst mode with internal CLKX (Tx serial clock) and FSX (Tx frame sync). The serial port control register (SPC) must have the following setup: FO = 0, FSM = 1, MCM = 1, and TXM = 1. The format bit, FO, may be set to 1 to set the word length to 8 bits in order to implement the power-down mode on the AD7450. The connection diagram is shown in Figure 26. For signal processing applications, it is imperative that the frame synchronization signal from the TMS320C5x/C54x provide equidistant sampling. The connection diagram in Figure 28 shows how the AD7450 can be connected to the SSI (synchronous serial interface) of the DSP56xxx family of DSPs from Motorola. The SSI is operated in synchronous mode (SYN bit in CRB = 1) with internally generated 1-bit clock period frame sync for both Tx and Rx (Bits FSL1 = 1 and FSL0 = 0 in CRB). Set the word length to 16 by setting Bits WL1 = 1 and WL0 = 0 in CRA. To implement the power-down mode on the AD7450, the word length can be changed to 8 bits by setting its WL1 = 0 and WL0 = 0 in CRA. It should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the DSP56xxx will provide equidistant sampling. DSP56xxx* AD7450* SCLK SCLK TMS320C5x/C54x* AD7450* SCLK CLKX SDATA SRD CS SR2 CLKR SDATA CS DR FSX *ADDITIONAL PINS OMITTED FOR CLARITY FSR *ADDITIONAL PINS OMITTED FOR CLARITY Figure 26. Interfacing to the TMS320C5x/C54x AD7450 to MC68HC16 The serial peripheral interface (SPI) on the MC68HC16 is configured for master mode (MSTR) = 1, clock polarity bit (CPOL) = 1, and clock phase bit (CPHA) = 0. The SPI is configured by writing to the SPI control register (SPCR)—see the 68HC16 user manual. The serial transfer will take place as a 16-bit operation when the SIZE bit in the SPCR register is set to SIZE = 1. To implement the power-down modes with an 8-bit transfer set SIZE = 0. A connection diagram is shown in Figure 27. MC68HC16* AD7450* SCLK SCLK/PMC2 SDATA MISO/PMC0 CS SS/PMC3 *ADDITIONAL PINS OMITTED FOR CLARITY Figure 27. Interfacing to the MC68HC16 Figure 28. Interfacing to the DSP56xxx APPLICATION HINTS Grounding and Layout The printed circuit board that houses the AD7450 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes since it gives the best shielding. Digital and analog ground planes should be joined in only one place, and the connection should be a star ground point established as close to the GND pin on the AD7450 as possible. Avoid running digital lines under the device, as this will couple noise onto the die. The analog ground plane should be allowed to run under the AD7450 to avoid noise coupling. The power supply lines to the AD7450 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. Good decoupling is also important. All analog supplies should be decoupled with 10 µF tantalum capacitors in parallel with 0.1 µF capacitors to GND. To achieve the best from these decoupling components, they must be placed as close as possible to the device. Rev. A –19– AD7450 EVALUATING THE AD7450 PERFORMANCE The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the Evaluation Board Controller. The Evaluation Board Controller can be used in conjunction with the AD7450 evaluation board, as well as many other Analog Devices evaluation boards ending with the CB designator, to demonstrate/evaluate the ac and dc performance of the AD7450. The software allows the user to perform ac (fast Fourier Transform) and dc (Histogram of codes) tests on the AD7450. See the evaluation board technical note for more information. –20– Rev. A AD7450 OUTLINE DIMENSIONS Figure 29. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 3.20 3.00 2.80 8 3.20 3.00 2.80 1 5 5.15 4.90 4.65 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.15 0.05 COPLANARITY 0.10 0.40 0.25 6° 0° 0.23 0.09 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 30. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. A| Page 21 0.80 0.55 0.40 AD7450 ORDERING GUIDE Model1 AD7450ARZ AD7450ARZ-REEL AD7450ARZ-REEL7 AD7450ARMZ AD7450ARMZ-REEL7 AD7450BRZ AD7450BRMZ 1 Temperature Range 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C Package Description 8-Lead Mini Small Outline Package [SOIC_N] 8-Lead Mini Small Outline Package [SOIC_N] 8-Lead Mini Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [MSOP] 8-Lead Standard Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [MSOP] Z = RoHS Compliant Part. – REVISION HISTORY 9/10—Rev 0 to Rev. A Updated Outline Dimensions ........................................................21 Changes to Ordering Guide ...........................................................22 ©2002–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02646-0-9/10(A) Rev. A | Page 22 Package Option R-8 R-8 R-8 RM-8 RM-8 R-8 RM-8 Branding Information C3S C3S C3R