PRELIMINARY TECHNICAL DATA a 3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT AD7276/AD7277/AD7278 Preliminary Technical Data FEATURES Fast Throughput Rate: 3MSPS Specified for VDD of 2.35 V to 3.6V Low Power: 13.5 mW max at 3MSPS with 3V Supplies TBD mW typ at 1.5MSPS with 3V Supplies Wide Input Bandwidth: 70dB SNR at 1MHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays High Speed Serial Interface SPITM/QSPITM/MICROWIRETM/DSP Compatible Power Down Mode: 1µA max 6-Lead TSOT Package 8-lead MSOP Package AD7476 and AD7476A pin compatible FUNCTIONAL BLOCK DIAGRAM V DD V IN T/H 8-/10-/12-BIT SUCCESSIVE APPROXIMATION ADC SCLK CONTROL LOGIC SDATA &6 AD7276/AD7277/AD7278 APPLICATIONS Battery-Powered Systems Personal Digital Assistants Medical Instruments Mobile Communications Instrumentation and Control Systems Data Acquisition Systems High-Speed Modems Optical Sensors GENERAL DESCRIPTION The AD7276/AD7277/AD7278 are 12-bit, 10-bit and 8bit, high speed, low power, successive-approximation ADCs respectively. The parts operate from a single 2.35V to 3.6 V power supply and feature throughput rates up to 3 MSPS. The parts contain a low-noise, wide bandwidth track/hold amplifier which can handle input frequencies in excess of TBD MHz. The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and the conversion is also initiated at this point. There are no pipeline delays associated with the part. The AD7276/AD7277/AD7278 use advanced design techniques to achieve very low power dissipation at high throughput rates. The reference for the part is taken internally from VDD. This allows the widest dynamic input range to the ADC. Thus the analog input range for the part is 0 to VDD. The conversion rate is determined by the SCLK. GND PRODUCT HIGHLIGHTS 1. 3MSPS ADCs in a 6-lead TSOT package. 2. AD7476/77/78 and AD7476A/77A/78A pin compatible. 3. High Throughput with Low Power Consumption. 4. Flexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock allowing the conversion time to be reduced through the serial clock speed increase. This allows the average power consumption to be reduced when a power-down mode is used while not converting. The part also features a power-down mode to maximize power efficiency at lower throughput rates. Current consumption is 1 µA max when in Power-Down mode. 5. Reference derived from the power supply. 6. No Pipeline Delay. The parts feature a standard successive-approximation ADC with accurate control of the sampling instant via a CS input and once-off conversion control. REV. PrF (6/04) Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.Trademarks and registered tradermarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2004 PRELIMINARY TECHNICAL DATA AD7278-SPECIFICATIONS Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD) 2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD) 2 Second Order Terms Third Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity 2 Differential Nonlinearity 2 Offset Error 2 Gain Error 2 Total Unadjusted Error (TUE)2 ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN, SCLK Pin Input Current, IIN, CS Pin Input Capacitance, CIN3 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding CONVERSION RATE Conversion Time Track/Hold Acquisition Time2 Throughput Rate POWER REQUIREMENTS VDD I DD Normal Mode(Static) Normal Mode (Operational) Full Power-Down Mode (Static) Full Power-Down Mode (Dynamic) Power Dissipation 4 Normal Mode (Operational) Full Power-Down (VDD=+2.35 V to +3.6 V, fSCLK=52 MHz, fSAMPLE=3 MSPS unless otherwise noted; TA=TMIN to TMAX, unless otherwise noted.) B Grade1 Units Test Conditions/Comments fIN= 1MHz Sine Wave 49 -65 -65 dB min dB max dB max -76 -76 TBD TBD TBD TBD dB typ dB typ ns typ ps typ MHz typ MHz typ 8 ±0.3 ±0.3 ±0.5 ±TBD ±0.5 ±TBD ±TBD Bits LSB max LSB max LSB max LSB typ LSB max LSB typ LSB max 0 to VDD ±0.5 TBD Volts µA max pF typ 0.7(V DD ) 2 0.2(V DD ) 0.8 ±0.5 ±TBD 10 V min V min V max V max µA max µA max pF max VDD - 0.2 V min 0.2 V max ±1 µA max 10 pF max Straight (Natural) Binary 192 50 3 ns max ns max MSPS max 2.35/3.6 Vmin/max 2.5 4.5 1 TBD mA mA µA mA typ max max typ 13.5 3 mW max µW max fa= TBD kHz, fb= TBD kHz fa= TBD kHz, fb= TBD kHz @ 3 dB @ 0.1dB Guaranteed No Missed Codes to 8 Bits 2.35V⭐Vdd⭐ 2.7V 2.7V < Vdd⭐ 3.6V 2.35V⭐Vdd< 2.7V 2.7V ⭐Vdd⭐ 3.6V Typically TBD nA, VIN= 0 V or VDD ISOURCE= 200 µA,VDD= 2.35 V to 3.6V I SINK= 200µA 10 SCLK Cycles with SCLK at 52 MHz Digital I/Ps= 0V or VDD VDD= 2.35V to 3.6V, SCLK On or Off VDD= 2.35V to 3.6V, fSAMPLE = 3MSPS SCLK On or Off, typically TBD nA V DD= 3V, f SAMPLE = 1MSPS V DD= 3V, f SAMPLE = 3MSPS V DD = 3V NOTES 1 Temperature range from –40°C to +85°C. 2 See Terminology. 3 Guaranteed by characterization. 4 See Power Versus Throughput Rate section. Specifications subject to change without notice. –2– REV. PrF PRELIMINARY TECHNICAL DATA AD7277-SPECIFICATIONS Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD) 2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD) 2 Second Order Terms Third Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity 2 Differential Nonlinearity 2 Offset Error 2 Gain Error 2 Total Unadjusted Error (TUE)2 ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN, SCLK Pin Input Current, IIN, CS Pin Input Capacitance, CIN3 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding CONVERSION RATE Conversion Time Track/Hold Acquisition Time 2 Throughput Rate POWER REQUIREMENTS VDD I DD Normal Mode(Static) Normal Mode (Operational) Full Power-Down Mode(Static) Full Power-Down Mode(Dynamic) Power Dissipation 4 Normal Mode (Operational) Full Power-Down (VDD=+2.35 V to +3.6 V, fSCLK=52 MHz, fSAMPLE=3MSPS unless otherwise noted; TA=TMIN to TMAX, unless otherwise noted.) B Grade1 Units fIN = 1 MHz Sine Wave 61 -73 -74 dB min dB max dB max -82 -82 TBD TBD TBD TBD dB typ dB typ ns typ ps typ MHz typ MHz typ 10 ±0.5 ±0.5 ±1 ±TBD ±1 ±TBD ±TBD Bits LSB LSB LSB LSB LSB LSB LSB 0 to VDD ±0.5 TBD 0.7(V DD ) 2 0.2(V DD ) 0.8 ±0.5 ±TBD 10 max max max typ max typ max fa= TBD kHz, fb= TBD kHz fa= TBD kHz, fb= TBD kHz @ 3 dB @ 0.1dB Guaranteed No Missed Codes to 10 Bits Volts µA max pF typ V min V min V max V max µA max µA max pF max VDD - 0.2 V min 0.2 V max ±1 µA max 10 pF max Straight (Natural) Binary 230 50 3 ns max ns max MSPS max 2.35/3.6 V min/max 2.35V⭐Vdd⭐2.7V 2.7V <Vdd⭐ 3.6V 2.35V⭐Vdd< 2.7V 2.7V ⭐Vdd⭐ 3.6V Typically TBD nA, VIN= 0 V or VDD ISOURCE= 200 µA,VDD= 2.35 V to 3.6 V I SINK = 200µA 12 SCLK cycles with SCLK at 52 MHz 2.5 4.5 1 TBD mA typ mA max µA max mA typ Digital I/Ps 0V or VDD VDD= 2.35V to 3.6V, SCLK On or Off VDD= 2.35V to 3.6V, fSAMPLE = 3MSPS SCLK On or Off, typically TBD nA V DD= 3V, f SAMPLE = 1MSPS 13.5 3 mW max µW max V DD= 3V, f SAMPLE = 3MSPS V DD = 3 V NOTES 1 Temperature range from –40°C to +85°C. 2 See Terminology. 3 Guaranteed by Characterization. 4 See Power Versus Throughput Rate section. Specifications subject to change without notice. REV. PrF Test Conditions/Comments –3– PRELIMINARY TECHNICAL DATA AD7276-SPECIFICATIONS Parameter (VDD=+2.35 V to +3.6 V, fSCLK=52 MHz, fSAMPLE=3MSPS unless otherwise noted; TA=TMIN to TMAX, unless otherwise noted.) B Grade1 Units fIN = 1 MHz Sine Wave DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD) 2 Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) 2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD) 2 Second Order Terms Third Order Term Aperture Delay Aperture Jitter Full Power Bandwidth Full Power Bandwidth 70 71 -80 -82 dB dB dB dB -84 -84 TBD TBD TBD TBD dB typ dB typ ns typ ps typ MHz typ MHz typ DC ACCURACY Resolution Integral Nonlinearity 2 Differential Nonlinearity 2 Offset Error2 Gain Error 2 Total Unadjusted Error (TUE)2 12 ±1 ±1 ±TBD ±TBD ±TBD Bits LSB LSB LSB LSB LSB ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN,SCLK Pin Input Current, IIN, CS Pin Input Capacitance, CIN3 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding CONVERSION RATE Conversion Time Track/Hold Acquisition Time 2 Throughput Rate POWER REQUIREMENTS VDD I DD Normal Mode(Static) Normal Mode (Operational) Full Power-Down Mode(Static) Full Power-Down Mode(Dynamic) Power Dissipation4 Normal Mode (Operational) Full Power-Down Test Conditions/Comments 0 to VDD ±0.5 TBD 0.7(VDD) 2 0.2(VDD) 0.8 ±0.5 ±TBD 10 min min typ typ fa= TBD kHz, fb= TBD kHz fa= TBD kHz, fb= TBD kHz @ 3 dB @ 0.1dB max max Guaranteed No Missed Codes to 12 Bits max max max Volts µA max pF typ V min V min V max V max µA max µA max pF max 2.35V⭐Vdd⭐2.7V 2.7V < Vdd⭐ 3.6V 2.35V⭐Vdd< 2.7V 2.7V ⭐Vdd⭐ 3.6V Typically TBDnA, VIN= 0 V or VDD VDD - 0.2 V min ISOURCE= 200 µA;VDD= 2.35 V to 3.6V 0.2 V max I SINK =200 µA ±1 µA max 10 pF max Straight (Natural) Binary 270 50 3 2.35/3.6 ns max 14 SCLK Cycles with SCLK at 52 MHz ns max MSPS max See Serial Interface Section V min/max Digital I/Ps 0V or VDD mA typ VDD= 2.35V to 3.6V, SCLK On or Off mA max VDD= 2.35V to 3.6V, fSAMPLE = 3MSPS µA max SCLK On or Off, typically TBD nA mA typ VDD= 3V, fSAMPLE = 1MSPS 2.5 4.5 1 TBD 13.5 3 mW max VDD= 3V, fSAMPLE = 3MSPS µW max VDD=3V NOTES 1 Temperature range from –40°C to +85°C. 2 See Terminology. 3 Guranteed by Characterization. 4 See Power Versus Throughput Rate section. Specifications subject to change without notice. –4– REV. PrF PRELIMINARY TECHNICAL DATA Preliminary Technical Data TIMING SPECIFICATIONS1 AD7276/AD7277/AD7278 (VDD= +2.35 V to +3.6 V; TA= TMIN to TMAX, unless otherwise noted.) Limit at TMIN, TMAX AD7276/AD7277/AD7278 Parameter 2 Units KHz min 3 MHz max t CONVERT 20 52 14 x tSCLK 12 x tSCLK 10 x tSCLK t QUIET TBD ns min t1 t2 t34 t44 t5 t6 t74 t85 10 TBD TBD TBD 0.4t SCLK 0.4t SCLK TBD TBD TBD TBD ns ns ns ns ns ns ns ns ns µs fSCLK t power-up 6 Description AD7276 AD7277 AD7278 Minimum Quiet Time required between Bus Relinquish and start of Next Conversion Minimum CS Pulse Width CS to SCLK Setup Time Delay from CS Until SDATA Three-State Disabled Data Access Time After SCLK Falling Edge SCLK Low Pulse Width SCLK High Pulse Width SCLK to Data Valid Hold Time SCLK Falling Edge to SDATA Three-State SCLK Falling Edge to SDATA Three-State Power Up Time from Full Power-down min min max max min min min max min max NOTES 1 Guaranteed by Characterization. All input signals are specified with tr=tf=5ns (10% to 90% of VDD) and timed from a voltage level of 1.6 Volts. 2 Mark/Space ratio for the SCLK input is 40/60 to 60/40. 3 Minimum f sclk at which specifications are guaranteed. 4 Measured with the load circuit of Figure 1 and defined as the time required for the output to cross the Vih or Vil voltage. 5 t8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 6 See Power-up Time section. Specifications subject to change without notice. 200µA IOL t7 SCLK TO OUTPUT PIN +1.6V CL 25pF SDATA 200µA V IH V IL IOH Figure 1. Load Circuit for Digital Output Timing Specifications Figure 3. Hold time after SCLK falling edge t8 t4 SCLK SCLK SDATA SDATA 1.4 V V IH V IL Figure 4. SCLK falling edge to SDATA Three-State Figure 2. Access time after SCLK falling edge REV. PrF –5– PRELIMINARY TECHNICAL DATA Preliminary Technical Data AD7276/AD7277/AD7278 Figures 5 and 6 show some of the timing parameters from the Timing Specifications table. t1 &6 tconvert t2 t6 SCLK 1 3 2 4 THREESTATE 13 15 14 t7 t3 SDATA B 5 16 t8 t5 tquiet t4 Z ZERO DB11 DB10 DB1 DB9 DB0 ZERO ZERO THREE-STATE 2 TRAILING ZERO’S 2 LEADING ZERO’S 1/ THROUGHPUT Figure 5. AD7276 Serial Interface Timing Diagram Timing Example 1 From Figure 6, having fSCLK = 52 MHz and a throughput of 3MSPS, gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 333 ns. With t2 = TBD ns min, this leaves tACQ to be TBD ns. This TBD ns satisfies the requirement of TBD ns for tACQ. Figure 6 shows that, tACQ comprises of 2.5(1/fSCLK) + t8 + tQUIET, where t8 = TBD ns max. This allows a value of TBD ns for tQUIET satisfying the minimum requirement of TBD ns. Timing Example 2 Having fSCLK = 20 MHz and a throughput of 1.5 MSPS, gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 666 ns. With t2 = TBD ns min, this leaves tACQ to be TBD ns. This TBD ns satisfies the requirement of TBD ns for tACQ. From Figure 6, tACQ comprises of 2.5(1/fSCLK) + t8 + tQUIET, where t8 = TBD ns max. This allows a values of TBD ns for tQUIET satisfying the minimum requirement of TBD ns. t1 &6 tconvert t2 SCLK B 1 2 3 4 5 12 13 14 15 16 t8 12.5(1/fSCLK) tquiet tacquisition 1/THROUGHPUT Figure 6. Serial Interface Timing Example –6– REV. PrF PRELIMINARY TECHNICAL DATA Preliminary Technical Data AD7276/AD7277/AD7278 ABSOLUTE MAXIMUM RATINGS 1 (TA = +25°C unless otherwise noted) V DD to GND......................................-0.3 V to TBD V Analog Input Voltage to GND......–0.3 V to VDD + 0.3 V Digital Input Voltage to GND..............–0.3 V to TBD V Digital Output Voltage to GND....–0.3 V to VDD + 0.3 V Input Current to Any Pin Except Supplies2..........±10 mA 8-lead MSOP Package θJA Thermal Impedance.................................205.9°C/W θJC Thermal Impedance...............................43.74°C/W Lead Temperature Soldering Reflow (10- 30 sec) ...................................+TBD°C ESD................................................................. TBD KV Operating Temperature Range Commercial (B Grade)......................–40°C to +85°C Storage Temperature Range..............–65°C to +150°C Junction Temperature..........................................150°C NOTES 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch up. 6-lead TSOT Package θJA Thermal Impedance..................................TBD°C/W θJC Thermal Impedance................................TBD°C/W PIN CONFIGURATION AD7276/AD7277/AD7278 VDD 1 GND VIN 2 3 AD7276/ AD7277/ AD7278 TOP VIEW 6 &6 5 SDATA 4 SCLK VDD 1 SDATA 2 &6 3 NC 4 (Not to Scale) 6-Lead TSOT AD7276/ AD7277/ AD7278 TOP VIEW (Not to Scale) 8 V IN 7 GND 6 SCLK 5 NC 8-Lead MSOP ORDERING GUIDE Model AD7276BUJ-REEL AD7276BRM AD7277BUJ-REEL AD7277BRM AD7278BUJ-REEL AD7278BRMJ Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Linearity Error (LSB)1 Package Option Package Description ±1 max ±1 max ±0.5 max ±0.5 max ±0.3 max ±0.3 max UJ-6 RM-8 UJ-6 RM-8 UJ-6 RM-8 TSOT MSOP TSOT MSOP TSOT MSOP NOTES 1 Linearity error here refers to integral nonlinearity. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7276/AD7277/AD7278 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. PrF –7– Branding Information TBD TBD TBD TBD TBD TBD PRELIMINARY TECHNICAL DATA Preliminary Technical Data AD7276/AD7277/AD7278 PIN FUNCTION DESCRIPTION Pin Mnemonic CS V DD GND VIN SDATA SCLK Function Chip Select. Active low logic input. This input provides the dual function of initiating conversion on the AD7276/AD7277/AD7278 and also frames the serial data transfer. Power Supply Input. The VDD range for the AD7276/AD7277/AD7278 is from +2.35V to +3.6V. Analog Ground. Ground reference point for all circuitry on the AD7276/AD7277/AD7278. All analog input signals should be referred to this GND voltage. Analog Input. Single-ended analog input channel. The input range is 0 to VDD. Data Out. Logic Output. The conversion result from the AD7276/AD7277/AD7278 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7276 consists of two leading zeros followed by the 12 bits of conversion data followed by two trailing zeros, which is provided MSB first. The data stream from the AD7277 consists of two leading zeros followed by the 10 bits of conversion data followed by four trailing zeros, which is provided MSB first. The data stream from the AD7278 consists of two leading zeros followed by the 8 bits of conversion data followed by six trailing zeros, which is provided MSB first. Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the AD7276/AD7277/AD7278's conversion process. –8– REV. PrF PRELIMINARY TECHNICAL DATA Preliminary Technical Data AD7276/AD7277/AD7278 TERMINOLOGY Integral Nonlinearity Total Harmonic Distortion This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7276/AD7277/AD7278, the endpoints of the transfer function are zero scale, a point 1/2 LSB below the first code transition, and full scale, a point 1/2 LSB above the last code transition. Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. It is defined as: 2 THD (dB ) = 20 log 2 2 2 2 V2 + V3 + V 4 + V5 + V 6 V1 Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. where V1 is the rms amplitude of the fundamental and V2, V3, V4 , V5 and V6 are the rms amplitudes of the second through the sixth harmonics. Offset Error Peak Harmonic or Spurious Noise This is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e, AGND + 0.5 LSB. Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it will be a noise peak. Gain Error This is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal, i.e, VREF – 1.5LSB after the offset error has been adjusted out. Total Unadjusted Error Intermodulation Distortion This is a comprehensive specification which includes gain, linearity and offset errors. With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa – fb), while the third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). Track/Hold Acquisition Time The Track/Hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within ±0.5 LSB, after the end of conversion. See Serial Interface section for more details. The AD7276/AD7277/AD7278 are tested using the CCIF standard where two input frequencies are used (see fa and fb in the specification page). In this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs. Signal to Noise Ratio (SNR) This is the measured ratio of signal to noise at the output to the A/D converter. The signal is the rms value of the sine wave input. Noise is the rms quantization error within the Nyquist bandwitdh (fs/2). The rms value of a sine wave is one half its peak to peak value divided by √2 and the rms value for the quantization noise is q/√12. The ratio is dependant on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. For an ideal N-bit converter, the SNR is defined as: Aperture Delay SNR = 6.02 N + 1.76 dB This is the measured interval between the leading edge of the sampling clock and the point at which the ADC actually takes the sample. Thus for a 12-bit converter this is 74 dB, for a 10-bit converter it is 62dB and for an 8-bit converter it is 50dB. Practically, though, various error sources in the ADC cause the measured SNR to be less than the theoretical value. These errors occur due to integral and differential nonlinearities, internal AC noise sources, etc. Aperture Jitter This is the sample-to-sample variation in the effective point in time at which the sample is taken. Signal-to- (Noise + Distortion) Ratio (SINAD) This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms value of the sine wave and noise is the rms sum of all nonfundamentals signals up to half the sampling frequency (fs/2), including harmonics but excluding dc. REV. PrF –9– PRELIMINARY TECHNICAL DATA Preliminary Technical Data AD7276/AD7277/AD7278 PERFORMANCE CURVES Dynamic Performance curves DC Accuracy curves TPC 1, TPC 2 and TPC 3 show typical FFT plots for the AD7276, AD7277 and AD7278 respectively, at 3 MSPS sample rate and TBD KHz input tone. TPC 8 and TPC 9 show typical INL and DNL performance for the AD7276. TPC 4 shows the Signal-to-(Noise+Distortion) Ratio performance versus Input frequency for various supply voltages while sampling at 3 MSPS with a SCLK frequency of 52 MHz for the AD7276. TPC10 shows Maximum current versus Supply voltage for the AD7276 with different SCLK frequencies. Power Requirements curves See also Power versus Throughput Rate section. TPC 5 shows the Signal to Noise Ratio (SNR) performance versus Input frequency for various supply voltages while sampling at 3 MSPS with a SCLK frequency of 52 MHz for the AD7276. TPC 6 shows a graph of the Total Harmonic Distortion versus Analog input signal frequency for various supply voltages while sampling at 3 MSPS with a SCLK frequency of 52 MHz for the AD7276. TPC 7 shows a graph of the Total Harmonic Distortion versus Analog input frequency for different source impedances when using a supply voltage of TBD V, SCLK frequency of 52 MHz and sampling at a rate of 3 MSPS for the AD7276. See Analog Input section. Typical Performance Characteristics 0 TBD TITLE TITLE TBD 0 0 TITLE 0 TITLE TPC 2. AD7277 Dynamic performance at 3 MSPS TPC 1. AD7276 Dynamic performance at 3 MSPS –10– REV. PrF PRELIMINARY TECHNICAL DATA Preliminary Technical Data AD7276/AD7277/AD7278 0 TBD TITLE TITLE TBD 0 0 0 TITLE TITLE TPC 6. THD vs. Analog Input Frequency at 3 MSPS for various Supply Voltages TPC 3. AD7278 Dynamic performance at 3 MSPS 0 TBD TITLE TITLE TBD 0 0 0 TITLE TITLE TPC 4. AD7276 SINAD vs Analog Input Frequency at 3 MSPS for various Supply Voltages TPC 7. THD vs. Analog Input Frequency for various Source Impedance 0 0 0 TITLE 0 TITLE TPC 5. AD7276 SNR vs Analog Input Frequency at 3 MSPS for various Supply Voltages REV. PrF TBD TITLE TITLE TBD TPC 8. AD7276 INL performance –11– PRELIMINARY TECHNICAL DATA Preliminary Technical Data AD7276/AD7277/AD7278 0 TBD TITLE TITLE TBD 0 0 TITLE 0 TITLE TPC 10. Maximum current vs Supply voltage for different SCLK frequencies. TPC 9. AD7276 DNL performance –12– REV. PrF PRELIMINARY TECHNICAL DATA Preliminary Technical Data AD7276/AD7277/AD7278 CIRCUIT INFORMATION The AD7276/AD7277/AD7278 are fast, micropower, 12-/ 10-/8-Bit, single supply, A/D converters respectively. The parts can be operated from a +2.35V to +3.6V supply. When operated from any supply voltage within this range, the AD7276/AD7277/AD7278 are capable of throughput rates of 3 MSPS when provided with a 52 MHz clock. When the ADC starts a conversion, see Figure 8, SW2 will open and SW1 will move to position B causing the comparator to become unbalanced. The Control Logic and the Charge Redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced the conversion is complete. The Control Logic generates the ADC output code. Figure 9 shows the ADC transfer function. The AD7276/AD7277/AD7278 provide the user with an on-chip track/hold, A/D converter, and a serial interface housed in a tiny 6-lead TSOT or 8-lead MSOP package, which offers the user considerable space saving advantages over alternative solutions. The serial clock input accesses data from the part but also provides the clock source for the successive-approximation A/D converter. The analog input range is 0 to VDD. An external reference is not required for the ADC and neither is there a reference onchip. The reference for the AD7276/AD7277/AD7278 is derived from the power supply and thus gives the widest dynamic input range. CHARGE REDISTRIBUTION DAC V IN SW1 CONVERSION PHASE V DD / 2 Figure 8. ADC Conversion Phase ADC TRANSFER FUNCTION The AD7276/AD7277/AD7278 is a successiveapproximation analog-to-digital converter based around a charge redistribution DAC. Figures 7 and 8 show simplified schematics of the ADC. Figure 7 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in position A, the comparator is held in a balanced condition and the sampling capacitor acquires the signal on V IN . The output coding of the AD7276/AD7277/AD7278 is straight binary. The designed code transitions occur midway between succesive integer LSB values, i.e, 0.5LSB, 1.5LSBs, etc. The LSB size is VDD/4096 for the AD7276, VDD/1024 for the AD7277 and VDD/256 for the AD7278. The ideal transfer characteristic for the AD7276/ AD7277/AD7278 is shown in Figure 9. CHA R GE RE DI ST R I B UT I ON DAC 111...111 111...110 ADC CODE SA MP LI NG CAP AC I TOR VI N CON T RO L LO GI C SW1 ACQUI SI TI ON PH AS E COMPARATOR AGND CONVERTER OPERATION B CONTROL LOGIC SW2 B The AD7276/AD7277/AD7278 also feature a power down option to allow power saving between conversions. The Power-Down feature is implemented across the standard serial interface as described in the Modes of Operation section. A SAMPLING CAPACITOR A SW2 1LSB = VDD /4096 (AD7276) 111...000 1LSB = VDD/1024 (AD7277) 011...111 1LSB = VDD /256 (AD7278) COMPA R AT OR 000...010 000...001 000...000 AG N D V DD / 2 0V 0.5LSB +VDD-1.5LSB ANALOG INPUT Figure 7. ADC Acquisition Phase Figure 9. AD7276/AD7277/AD7278 Transfer Characteristic REV. PrF –13– PRELIMINARY TECHNICAL DATA Preliminary Technical Data AD7276/AD7277/AD7278 TYPICAL CONNECTION DIAGRAM Figure 10 shows a typical connection diagram for the AD7276/AD7277/AD7278. VREF is taken internally from VDD and as such VDD should be well decoupled. This provides an analog input range of 0V to VDD. The conversion result is output in a 16-bit word with two leading zeros followed by the 12-bit, 10-bit or 8-bit result. The 12-bit result from the AD7276 will be followed by two trailing zeros and the 10-bit and 8-bit result from the AD7277 and AD7278 will be followed by four and six trailing zeros respectively. Alternatively, because the supply current required by the AD7276/AD7277/AD7278 is so low, a presision reference can be used as the supply source to the AD7276/AD7277/ AD7278. A REF19x voltage reference (REF193 for 3V) can be used to supply the required voltage to the ADC -see Figure 10. This configuration is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 3V (e.g. 5V or 15V). The REF19x will output a steady voltage to the AD7276/ 7277/7278. If the low dropout REF193 is used, the current it needs to supply to the AD7276/AD7277/ AD7278 is typically TBD mA. When the ADC is converting at a rate of 3 MSPS the REF193 will need to supply a maximum of TBD mA to the AD7276/AD7277/ AD7278. The load regulation of the REF193 is typically 10 ppm/mA (REF193, VS= 5V), which results in an error of TBD ppm (TBD µV) for the TBD mA drawn from it. This corresponds to a TBD LSB error for the AD7276 with VDD= 3V from the REF193, a TBD LSB error for the AD7277, and a TBD LSB error for the AD7278. For applications where power consumption is of concern, the Power-Down mode of the ADC and the sleep mode of the REF19x reference should be used to improve power performance. See Modes of Operation section. +3V TBD mA 0.1µF REF193 1µF 10µF TANT 680nF 0V toVDD INPUT 0.1µF +5V SUPPLY VDD VIN GND AD7276/ AD7277/ AD7278 SCLK DSP/ µC/µP SDATA Table I provides some typical performance data with various references used as a VDD source under the same set-up conditions. Reference Tied To VDD AD7276 SNR Performance TBD kHz Input AD780@3V ADR423 TBD dB TBD dB [email protected] REF192 ADR421 ADR291 TBD TBD TBD TBD dB dB dB dB Table I. AD7276 performance for various Voltage References IC Analog Input Figure 11 shows an equivalent circuit of the analog input structure of the AD7276/AD7277/AD7278. The two diodes D1 and D2 provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 300mV. This will cause these diodes to become forward biased and start conducting current into the substrate. 10mA is the maximum current these diodes can conduct without causing irreversable damage to the part. The capacitor C1 in Figure 11 is typically about 4pF and can primarily be attributed to pin capacitance. The resistor R1 is a lumped component made up of the on resistance of a switch. This resistor is typically about TBDΩ. The capacitor C2 is the ADC sampling capacitor and has a capacitance of TBD pF typically. For ac applications, removing high frequency components from the analog input signal is recommended by use of a bandpass filter on the relevant analog input pin. In applications where harmonic distortion and signal to noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances will significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op-amp will be a function of the particular application. VDD &6 SERIAL INTERFACE D1 C2 TBD PF R1 VIN Figure 10. REF193 as Power Supply to AD7276/ AD7277/AD7278 C1 4pF D2 CONVERSION PHASE - SWITCH OPEN TRACK PHASE - SWITCH CLOSED Figure 11. Equivalent Analog Input Circuit –14– REV. PrF PRELIMINARY TECHNICAL DATA Preliminary Technical Data AD7276/AD7277/AD7278 Table II provides some typical performance data with various op-amps used as the input buffer under the same set-up conditions. Op-amp in the input buffer MODES OF OPERATION AD7276 SNR Performance TBD kHz Input AD8510 TBD dB AD8610 TBD dB AD8038 TBD dB AD8519 TBD dB Table II. AD7276 performance for various Input Buffers The mode of operation of the AD7276/AD7277/AD7278 is selected by controlling the logic state of the CS signal during a conversion. There are two possible modes of operation, Normal Mode and Power-Down Mode. The point at which CS is pulled high after the conversion has been initiated will determine whether the AD7276/ AD7277/AD7278 will enter Power-Down Mode or not. Similarly, if already in Power-Down then CS can control whether the device will return to Normal operation or remain in Power-Down. These modes of operation are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for different application requirements. Normal Mode When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance will depend on the amount of total harmonic distortion (THD) that can be tolerated. The THD will increase as the source impedance increases and performance will degrade. TPC 7 shows a graph of the Total Harmonic Distortion versus Analog input frequency for different source impedances when using a supply voltage of TBD V and sampling at a rate of 3 MSPS. Digital Inputs The digital inputs applied to the AD7276/AD7277/ AD7278 are not limited by the maximum ratings which limit the analog inputs. Instead, the digitals inputs applied can go to TBDV and are not restricted by the VDD + 0.3V limit as on the analog inputs. For example, if the AD7276/AD7277/AD7278 were operated with a VDD of 3V then 5V logic levels could be used on the digital inputs. However, it is important to note that the data output on SDATA will still have 3V logic levels when VDD= 3V. Another advantage of SCLK and CS not being restricted by the VDD + 0.3V limit is the fact that power supply sequencing issues are avoided. If CS or SCLK are applied before VDD then there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3V was applied prior to VDD. This mode is intended for fastest throughput rate performance as the user does not have to worry about any power-up times with the AD7276/AD7277/AD7278 remaining fully powered all the time. Figure 12 shows the general diagram of the operation of the AD7276/AD7277/ AD7278 in this mode. The conversion is iniated on the falling edge of CS as described in the Serial Interface section. To ensure the part remains fully powered up at all times CS must remain low until at least 10 SCLK falling edges have elapsed after the falling edge of CS. If CS is brought high any time after the 10th SCLK falling, the part will remain powered up but the conversion will be terminated and SDATA will go back into three-state. For the AD7276 a minimum of 14 serial clock cycles are required to complete the conversion and access the complete conversion result. For the AD7277 and AD7278 a minimum of 12 and 10 serial clock cycles are required to complete the conversion and access the complete conversion result, respectively. CS may idle high until the next conversion or may idle low until CS returns high sometime prior to the next conversion (effectively idling CS low). Once a data transfer is complete (SDATA has returned to three-state), another conversion can be initiated after the quiet time, tQUIET, has elapsed by bringing CS low again. &6 SCLK SDATA AD7276/77/78 10 1 12 14 VALID DATA Figure 12. Normal Mode Operation REV. PrF –15– 16 PRELIMINARY TECHNICAL DATA Preliminary Technical Data AD7276/AD7277/AD7278 Power-Down Mode In order to exit this mode of operation and power the AD7276/AD7277/AD7278 up again, a dummy conversion is performed. On the falling edge of CS the device will begin to power up, and will continue to power up as long as CS is held low until after the falling edge of the 10th SCLK. The device will be fully powered up once 16 SCLKs have elapsed and valid data will result from the next conversion as shown in Figure 14. If CS is brought high before the 10th falling edge of SCLK, then the AD7276/AD7277/AD7278 will go back into PowerDown again. This avoids accidental power up due to glitches on the CS line or an inadvertent burst of 8 SCLK cycles while CS is low. So, although the device may begin to power up on the falling edge of CS, it will power down again on the rising edge of CS as long as it occurs before the 10th SCLK falling edge. This mode is intended for use in applications where slower throughput rates are required; either the ADC is powered down between each conversion, or a series of conversions may be performed at a high throughput rate and then the ADC is powered down for a relatively long duration between these bursts of several conversions. When the AD7276/AD7277/AD7278 is in Power-Down, all analog circuitry is powered down. To enter Power-Down, the conversion process must be interrupted by bringing CS high anywhere after the second falling edge of SCLK and before the 10th falling edge of SCLK as shown in Figure 13. Once CS has been brought high in this window of SCLKs, then the part will enter Power-Down and the conversion that was intiated by the falling edge of CS will be terminated and SDATA will go back into three-state. If CS is brought high before the second SCLK falling edge, then the part will remain in Normal Mode and will not power-down. This will avoid accidental power-down due to glitches on the CS line. &6 SCLK 1 2 16 10 SDATA THREE-STATE INVALID DATA Figure 13. Entering Power Down Mode THE PART IS FULLY POWERED UP WITH VIN THE PART BEGINS TO POWER UP FULLY ACQUIRED &6 SCLK SDATA A 1 10 16 16 1 INVALID DATA VALID DATA Figure 14. Exiting Power Down Mode –16– REV. PrF PRELIMINARY TECHNICAL DATA Preliminary Technical Data AD7276/AD7277/AD7278 Power-up Time The power-up time of the AD7276/AD7277/AD7278 is TBD ns, which means that with any frequency of SCLK up to 52 MHz, one dummy cycle will always be sufficient to allow the device to power up. Once the dummy cycle is complete, the ADC will be fully powered up and the input signal will be acquired properly. The quite time tQUIET must still be allowed from the point where the bus goes back into three-state after the dummy conversion, to the next falling edge of CS. When running at 3 MSPS throughput rate, the AD7276/AD7277/AD7278 will power up and acquire a signal within ±0.5LSB in one dummy cycle, i.e. TBD ns. When powering up from the Power-Down mode with a dummy cycle, as in Figure 14, the track and hold which was in hold mode while the part was powered down, returns to track mode after the first SCLK edge the part receives after the falling edge of CS. This is shown as point A in Figure 14. Although at any SCLK frequency one dummy cycle is sufficient to power the device up and acquire VIN, it does not necessarily mean that a full dummy cycle of 16 SCLKs must always elapse to power up the device and acquire VIN fully; TBD ns will be sufficient to power the device up and acquire the input signal. If, for example, a 25 MHz SCLK frequency was applied to the ADC, the cycle time would be 640 ns. In one dummy cycle, 640 ns, the part would be powered up and VIN acquired fully. However after TBD ns with a 25 MHz SCLK only TBD SCLK cycles would have elapsed. At this stage, the ADC would be fully powered up and the signal acquired. So, in this case the CS can be brought high after the 10th SCLK falling edge and brought low again after a time tQUIET to initiate the conversion. current, if the ADC powers up in the desired mode of operation and thus a dummy cycle is not required to change mode, then neither is a dummy cycle required to place the track and hold into track. POWER VERSUS THROUGHPUT RATE By using the Power-Down mode on the AD7276/AD7277/ AD7278 when not converting, the average power consumption of the ADC decreases at lower throughput rates. Figure 15 shows how as the throughput rate is reduced, the device remains in its Power-Down state longer and the average power consumption over time drops accordingly. For example, if the AD7276/AD7277/AD7278 is operated in a continuous sampling mode with a throughput rate of 500KSPS and a SCLK of 52MHz (VDD= 3V), and the device is placed in the Power-Down mode between conversions, then the power consumption is calculated as follows. The power dissipation during normal operation is 13.5 mW (VDD= 3V). If the power up time is one dummy cycle, i.e. 333ns, and the remaining conversion time is another cycle, i.e. 333ns, then the AD7276/AD7277/ AD7278 can be said to dissipate 13.5mW for 666ns during each conversion cycle.If the throughput rate is 500KSPS, the cycle time is 2µs and the average power dissipated during each cycle is (666/2000) x (13.5 mW)= 4.5mW. Figure 15 shows the Power vs. Throughput Rate when using the Power-Down mode between conversions at 3V. The Power-Down mode is intended for use with throughput rates of approximately TBD MSPS and under as at higher sampling rates there is no power saving made by using the Power-Down mode. REV. PrF TBD TITLE When power supplies are first applied to the AD7276/ AD7277/AD7278, the ADC may either power up in the Power-Down mode or in Normal mode. Because of this, it is best to allow a dummy cycle to elapse to ensure the part is fully powered up before attempting a valid conversion. Likewise, if it is intended to keep the part in the Power-Down mode while not in use and the user wishes the part to power up in Power-Down mode, then the dummy cycle may be used to ensure the device is in Power-Down by executing a cycle such as that shown in Figure 13. Once supplies are applied to the AD7276/ AD7277/AD7278, the power up time is the same as that when powering up from the Power-Down mode. It takes approximately TBD ns to power up fully if the part powers up in Normal mode. It is not necessary to wait TBD ns before executing a dummy cycle to ensure the desired mode of operation. Instead, the dummy cycle can occur directly after power is supplied to the ADC. If the first valid conversion is then performed directly after the dummy conversion, care must be taken to ensure that adequate acquisition time has been allowed. As mentioned earlier, when powering up from the Power-Down mode, the part will return to track upon the first SCLK edge applied after the falling edge of CS. However, when the ADC powers up initially after supplies are applied, the track and hold will already be in track. This means, assuming one has the facility to monitor the ADC supply 0 0 TITLE Figure 15. Power vs Throughput –17– PRELIMINARY TECHNICAL DATA Preliminary Technical Data AD7276/AD7277/AD7278 SERIAL INTERFACE Figures 16, 17 and 18 show the detailed timing diagram for serial interfacing to the AD7276, AD7277 and AD7278 respectively. The serial clock provides the conversion clock and also controls the transfer of information from the AD7276/AD7277/AD7278 during conversion. The CS signal initiates the data transfer and conversion process. The falling edge of CS puts the track and hold into hold mode, takes the bus out of three-state and the analog input is sampled at this point. The conversion is also initiated at this point. For the AD7276 the conversion will require 14 SCLK cycles to complete. Once 13 SCLK falling edges have elapsed the track and hold will go back into track on the next SCLK rising edge as shown in Figure 16 at point B. If the rising edge of CS occurs before 14 SCLKs have elapsed then the conversion will be terminated and the SDATA line will go back into three-state. If 16 SCLKs are considered in the cycle, the last two bits will be zeros and SDATA will return to three-state on the 16th SCLK falling edge as shown in Figure 16. For the AD7277 the conversion will require 12 SCLK cycles to complete. Once 11 SCLK falling edges have elapsed, the track and hold will go back into track on the next SCLK rising edge, as shown in Figure 17 at point B. If the rising edge of CS occurs before 12 SCLKs have elapsed then the conversion will be terminated and the SDATA line will go back into three-state. If 16 SCLKs are considered in the cycle, the AD7277 will clock out four trailing zeros for the last four bits and SDATA will return to three-state on the 16th SCLK falling edge, as shown in Figure 17. For the AD7278 the conversion will require 10 SCLK cycles to complete. Once 9 SCLK falling edges have elapsed, the track and hold will go back into track on the next rising edge. If the rising edge of CS occurs before 10 SCLKs have elapsed then the part will enter Power-Down mode. If 16 SCLKs are considered in the cycle, the AD7278 will clock out six trailing zeros for the last six bits and SDATA will return to three-state on the 16th SCLK falling edge, as shown in Figure 18. If the user considers a 14 SCLKs cycle serial interface for the AD7276/AD7277/AD7278, CS needs to be brought high after the 14th SCLK falling edge, the last two trailing zeros will be ignored and SDATA will go back into three-state. In this case, the 3MSPS throughput could be achieved using a 45MHz clock frequency. CS going low clocks out the first leading zero to be read in by the microcontroller or DSP. The remaining data is then clocked out by subsequent SCLK falling edges beginning with the 2nd leading zero. Thus the first falling clock edge on the serial clock has the first leading zero provided and also clocks out the second leading zero. The final bit in the data transfer is valid on the 16th falling edge, having being clocked out on the previous (15th) falling edge. In applications with a slower SCLK, it is possible to read in data on each SCLK rising edge. In that case, the first falling edge of SCLK will clock out the second leading zero and it could be read in the first rising edge. However, the first leading zero that was clocked out when CS went low will be missed unless it was not read in the first falling edge. The 15th falling edge of SCLK will clock out the last bit and it could be read in the 15th rising SCLK edge. If CS goes low just after one the SCLK falling edge has elapsed, CS will clock out the first leading zero as before and it may be read in the SCLK rising edge. The next SCLK falling edge will clock out the second leading zero and it could be read in the following rising edge. t1 &6 tconvert t2 t6 SCLK 1 2 3 4 THREESTATE Z 13 15 14 t7 t3 SDATA B 5 16 t8 t5 t4 ZERO DB11 DB10 DB9 DB1 DB0 ZERO ZERO tquiet THREE-STATE 2 TRAILING ZERO ’S 2 LEADING ZERO’S 1/ THROUGHPUT Figure 16. AD7276 Serial Interface Timing Diagram –18– REV. PrF PRELIMINARY TECHNICAL DATA Preliminary Technical Data AD7276/AD7277/AD7278 t1 &6 tconvert t2 1 3 2 4 t3 SDATA Z THREESTATE t6 B SCLK DB9 11 12 13 15 14 16 t7 t5 t4 ZERO 10 DB1 DB8 DB0 ZERO t8 ZERO ZERO tquiet ZERO THREE-STATE 4TRAILING ZERO’S 2 LEADI NG ZERO’S 1/ THROUGHPUT Figure 17. AD7277 Serial Interface Timing Diagram t1 &6 tconvert t2 1 2 3 t3 SDATA THREESTATE B t6 SCLK Z 4 DB7 9 10 11 14 t7 t5 t4 ZERO 8 DB6 DB1 DB0 2 LEADI NG ZERO’S 15 16 t8 ZERO ZERO tq uiet ZERO THREE-STATE 6TRAILING ZERO’S 1/ THROUGHPUT Figure 18. AD7278 Serial Interface Timing Diagram AD7278 in a 10 SCLK’s cycle Serial Interface From Figure 19, tACQ comprises of 0.5(1/fSCLK) + t8 + tQUIET, where t8 = TBDns max. This allows a value of TBDns for tQUIET satisfying the minimum requirement of TBDns. For the AD7278, if CS is brought high in the 10th rising edge after the 2 leading zeros and the 8 bits of the conversion have been provided, the part can achieve a 4.2MSPS throughput rate. For the AD7278, the track and hold goes back into track in the 9th rising edge. In that case, a fSCLK = 52 MHz and a throughput of 4.2MSPS, gives a cycle time of t2 + 8.5(1/fSCLK) + tACQ = 238ns. With t2 = TBDns min, this leaves tACQ to be TBDns. This TBDns satisfies the requirement of 50 ns for tACQ. t1 &6 tconvert t2 t6 SCLK 1 2 3 4 B 5 9 10 tQUIET t8 tACQ 8.5 (1/ fSCLK) SDATA Z 3-STATE ZERO DB7 DB6 DB5 DB1 DB0 3-STATE 2 LEADING ZERO’S 1/ THROUGHPUT Figure 19. AD7278 in a 10 SCLK Cycle Serial Interface REV. PrF –19– PRELIMINARY TECHNICAL DATA Preliminary Technical Data AD7276/AD7277/AD7278 OUTLINE DIMENSIONS Dimensions shown in millimeters 6-Lead Thin Small Outline Transistor Package [TSOT] (UJ-6) PR04903-0-6/04(PrF) Dimensions shown in millimeters 2 .9 0 BSC 6 5 4 2 .8 0 BSC 1 .6 0 BSC 2 1 3 PIN 1 0.95 BSC 1.90 BSC 0 .9 0 0 .8 7 0 .8 4 1 .0 0 MAX 0 .5 0 0 .3 0 0 .10 MAX 0.22 0.08 1 0° 4° 0° SEATING PLANE 0 .6 0 0 .4 5 0 .3 0 COMPLIANT TO JEDEC STANDARDS MO-193AA 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 0.122 (3.10) 0.114 (2.90) & # 0.199 (5.05) 0.122 (3.10) 0.187 (4.75) 0.114 (2.90) " PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.120 (3.05) 0.112 (2.84) 0.112 (2.84) 0.043 (1.09) 0.006 (0.15) 0.037 (0.94) 0.002 (0.05) 0.018 (0.46) SEATING PLANE 0.008 (0.20) 0.011 (0.28) 0.003 (0.08) 33° 27° 0.028 (0.71) 0.016 (0.41) COMPLIANT TO JEDEC STANDARDS MO-187AA –20– REV. PrA