19-2715; Rev 0; 1/03 16-Bit DACs with 16-Channel Sample-and-Hold Outputs ________________________Applications MEMS Mirror Servo Control Industrial Process Control Automatic Test Equipment Instrumentation Ordering Information PART TEMP RANGE PIN-PACKAGE MAX5621AECB -40oC to +85oC 64 TQFP MAX5621AETK -40oC to +85oC 68 Thin QFN-EP* MAX5622AECB -40oC to +85oC 64 TQFP o o MAX5622AETK -40 C to +85 C 68 Thin QFN-EP* MAX5623AECB -40oC to +85oC 64 TQFP o MAX5623AETK 68 Thin QFN-EP* o -40 C to +85 C *EP = Exposed pad. 53 N.C. 52 CL 54 OUT11 56 OUT12 55 N.C. 57 N.C. 58 AGND 60 N.C. 59 OUT13 62 N.C. 61 OUT14 63 OUT15 65 AGND 64 N.C. 66 VREF TOP VIEW 67 CH Pin Configurations 68 N.C. Each device features an output clamp and output resistors for filtering. The MAX5621 features a 50Ω output impedance and is capable of driving up to 250pF of output capacitance. The MAX5622 features a 500Ω output impedance and is capable of driving up to 10nF of output capacitance. The MAX5623 features a 1kΩ output impedance and is capable of driving up to 10nF of output capacitance. The MAX5621/MAX5622/MAX5623 are available in 64-pin TQFP (10mm x 10mm) and 68-pin thin QFN (10mm x 10mm) packages. Features ♦ Integrated 16-Bit DAC and 16-Channel SHA with SRAM and Sequencer ♦ 16 Voltage Outputs ♦ 0.005% Output Linearity ♦ 200µV Output Resolution ♦ Flexible Output Voltage Range ♦ Remote Ground Sensing ♦ Fast Sequential Loading: 1.3µs per Register ♦ Burst and Immediate Mode Addressing ♦ No External Components Required for Setting Gain and Offset ♦ Integrated Output Clamp Diodes ♦ Three Output Impedance Options MAX5621 (50Ω), MAX5622 (500Ω), and MAX5623 (1kΩ) N.C. 1 N.C. 2 GS 3 51 N.C. 50 VDD 49 CH 48 VSS VLDAC 4 RST CS DIN SCLK 5 47 OUT10 6 46 N.C. 45 OUT9 VLOGIC IMMED ECLK CLKSEL 9 7 8 44 N.C. 43 OUT8 MAX5621 MAX5622 MAX5623 10 11 42 AGND 41 VDD 12 40 N.C. DGND 13 39 OUT7 VLSHA 14 38 N.C. 37 OUT6 AGND 15 VSS 16 N.C. 17 36 N.C. 34 33 32 31 OUT5 CH VSS N.C. N.C. 28 OUT4 29 N.C. 30 N.C. 25 AGND 26 OUT3 27 OUT1 22 N.C. 23 OUT2 24 CL 19 OUT0 20 N.C. 21 VDD 18 35 CL THIN QFN SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor, Corp. Pin Configurations continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5621/MAX5622/MAX5623 General Description The MAX5621/MAX5622/MAX5623 are 16-bit digital-toanalog converters (DACs) with 16 sample-and-hold (SHA) outputs for applications where a high number of programmable voltages are required. These devices include a clock oscillator and a sequencer that updates the DAC with codes from an internal SRAM. No external components are required to set offset and gain. The MAX5621/MAX5622/MAX5623 feature a -4.5V to +9.2V output voltage range. Other features include a 200µV/step resolution, with output linearity error, typically 0.005% of full-scale range (FSR). The 100kHz refresh rate updates each SHA every 320µs, resulting in negligible output droop. Remote ground sensing allows the outputs to be referenced to the local ground of a separate device. These devices are controlled through a 20MHz SPI™/QSPI™/MICROWIRE™-compatible 3-wire serial interface. Immediate update mode allows any channel’s output to be updated within 20µs. Burst mode allows multiple values to be loaded into memory in a single, high-speed data burst. All channels are updated within 330µs after data has been loaded. MAX5621/MAX5622/MAX5623 16-Bit DACs with 16-Channel Sample-and-Hold Outputs ABSOLUTE MAXIMUM RATINGS VDD to AGND.......................................................-0.3V to +12.2V VSS to AGND .........................................................-6.0V to +0.3V VDD to VSS ...........................................................................+15V VLDAC, VLOGIC, VLSHA to AGND or DGND ..............-0.3V to +6V REF to AGND............................................................-0.3V to +6V GS to AGND................................................................VSS to VDD CL and CH to AGND...................................................VSS to VDD Logic Inputs to DGND ..............................................-0.3V to +6V DGND to AGND........................................................-0.3V to +2V Maximum Current into OUT_ ............................................±10mA Maximum Current into Logic Inputs .................................±20mA Continuous Power Dissipation (TA = +70°C) 64-Pin TQFP (derate 13.3mW/°C above +70°C) ............1066mW 68-Pin Thin QFN (derate 28.6mW/°C above +70°C) ......2285mW Operating Temperature Range ...........................-40°C to +85°C Maximum Junction Temperature .....................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +10V, VSS = -4V, VLOGIC = VLDAC = VLSHA = +5V, VREF = +2.5V, AGND = DGND = VGS = 0V, RL ≥ 10MΩ, CL = 50pF, CLKSEL = +5V, fECLK = 400kHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC CHARACTERISTICS Resolution Output Range N 16 VOUT_ VSS + 0.75 Offset Voltage (Note 1) ±15 Code = 4F2C hex Gain Error (Note 2) ±5 Integral Linearity Error INL VOUT_ = -3.25V to +7.6V Differential Linearity Error DNL VOUT_ = -3.25V to +7.6V; monotonicity guaranteed to 14 bits Maximum Output Drive Current IOUT Sinking and sourcing ±2 MAX5621 ROUT Maximum Capacitive Load DC Crosstalk 2 PSRR V mV µV/°C ±1 Gain Tempco Power-Supply Rejection Ratio ±200 ±50 Offset Voltage Tempco DC Output Impedance Bits VDD 2.4 % ppm/°C 0.005 0.015 %FSR ±1 ±4 LSB 35 50 65 MAX5622 350 500 650 MAX5623 700 1000 1300 mA Ω MAX5621 250 MAX5622 10 MAX5623 10 Internal oscillator enabled (Note 3) -90 dB Internal oscillator enabled -80 dB _______________________________________________________________________________________ pF nF 16-Bit DACs with 16-Channel Sample-and-Hold Outputs (VDD = +10V, VSS = -4V, VLOGIC = VLDAC = VLSHA = +5V, VREF = +2.5V, AGND = DGND = VGS = 0V, RL ≥ 10MΩ, CL = 50pF, CLKSEL = +5V, fECLK = 400kHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC CHARACTERISTICS Sample-and-Hold Settling (Note 4) 0.08 SCLK Feedthrough 0.5 % nV-s fSEQ Feedthrough 0.5 Hold-Step 0.25 1 mV 1 40 mV/s Droop Rate VOUT_ = 0V (Note 5), TA = +25°C Output Noise nV-s µVRMS 250 REFERENCE INPUT Input Resistance 7 Reference Input Voltage VREF kΩ 2.5 V GROUND-SENSE INPUT Input Voltage Range VGS Input Bias Current IGS GS Gain -0.5 -0.5V ≤ VGS ≤ +0.5V (Note 6) +0.5 -60 0.998 1 V 0 µA 1.002 V/V DIGITAL INTERFACE DC CHARACTERISTICS Input High Voltage VIH Input Low Voltage VIL 2.0 V Input Current 0.8 V ±1 µA 120 kHz 480 kHz 20 MHz TIMING CHARACTERISTICS (Figure 2) Sequencer Clock Frequency fSEQ Internal oscillator External Clock Frequency fECLK (Note 7) SCLK Frequency fSCLK 80 100 SCLK Pulse Width High tCH 15 ns SCLK Pulse Width Low tCL 15 ns CS Low to SCLK High Setup Time tCSSO 15 ns CS High to SCLK High Setup Time tCSS1 15 ns SCLK High to CS Low Hold Time tCSH0 10 ns _______________________________________________________________________________________ 3 MAX5621/MAX5622/MAX5623 ELECTRICAL CHARACTERISTICS (continued) MAX5621/MAX5622/MAX5623 16-Bit DACs with 16-Channel Sample-and-Hold Outputs ELECTRICAL CHARACTERISTICS (continued) (VDD = +10V, VSS = -4V, VLOGIC = VLDAC = VLSHA = +5V, VREF = +2.5V, AGND = DGND = VGS = 0V, RL ≥ 10MΩ, CL = 50pF, CLKSEL = +5V, fECLK = 400kHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL SCLK High to CS High Hold Time tCSH1 0 ns DIN to SCLK High Setup Time tDS 15 ns DIN to SCLK High Hold Time tDH 0 RST to CS Low CONDITIONS MIN TYP MAX UNITS ns (Note 8) 500 µs POWER SUPPLIES Positive Supply Voltage VDD (Note 9) 8.55 10 11.60 V Negative Supply Voltage VSS (Note 9) -5.25 -4 -2.75 V 14.5 V 5 5.25 V Supply Difference Logic Supply Voltage VDD - VSS (Note 9) VLOGIC, VLDAC, VLSHA 4.75 Positive Supply Current IDD 32 42 mA Negative Supply Current ISS 32 40 mA 1 2 1.5 3 mA Logic Supply Current ILOGIC (Note 10) fSCLK = 20MHz (Note 11) Note 1: The nominal zero-scale (code = 0) voltage is -4.0535V. The nominal full-scale (code = FFFF hex) voltage is +9.0535V. The output voltage is limited by the Output Range specification, restricting the usable range of DAC codes. The nominal zeroscale voltage can be achieved when VSS < -4.9V, and the nominal full-scale voltage can be achieved when VDD > +11.5V. Note 2: Gain is calculated from measurements: for voltages VDD = 10V and VSS = -4V at codes C000 hex and 4F2C hex for voltages VDD = 11.6V and VSS = -2.9V at codes FFFF hex and 252E hex for voltages VDD = 9.25V and VSS = -5.25V at codes D4F6 hex and 0 hex for voltages VDD = 8.55V and VSS = -2.75V at codes C74A hex and 281C hex Note 3: Steady-state change in any output with an 8V change in an adjacent output. Note 4: Settling during the first update for an 8V step. The output settles to within the linearity specification on subsequent updates. Tested with an external sequencer clock frequency of 480kHz. Note 5: External clock mode with the external clock not toggling. Note 6: The output voltage is the sum of the DAC output and the voltage at GS. GS gain is measured at 4F2C hex. Note 7: The sequencer runs at fSEQ = fECLK/4. Maximum speed is limited by settling of the DAC and SHAs. Minimum speed is limited by acceptable droop and update time after a Burst Mode Update. Note 8: VDD rise to CS low = 500µs maximum. Note 9: Guaranteed by gain-error test. Note 10: The serial interface is inactive. VIH = VLOGIC, VIL = 0V. Note 11: The serial interface is active. VIH = VLOGIC, VIL = 0V. 4 _______________________________________________________________________________________ 16-Bit DACs with 16-Channel Sample-and-Hold Outputs 0.001 -0.001 -0.003 -0.005 -0.007 -0.2 -0.6 -1.0 0.008 0.006 0.004 0.002 -1.4 4018 11769 19520 27271 35021 42723 58268 INPUT CODE INPUT CODE DIFFERENTIAL NONLINEARITY VS. TEMPERATURE VS. TEMPERATURE 0 -40 0.6 MAX5621 toc05 -14 -16 -18 0.5 10 35 60 85 1 0.100 0.010 0.0001 -40 -15 10 35 60 -40 85 -15 10 35 60 TEMPERATURE (°C) TEMPERATURE (°C) GAIN ERROR VS. TEMPERATURE POSITIVE SUPPLY PSRR VS. FREQUENCY NEGATIVE SUPPLY PSRR VS. FREQUENCY -80 -90 -70 -80 -70 -60 PSRR (dB) 0.02 0.01 CODE = C168 hex OFFSET CODE = 4F2C hex 0 PSRR (dB) -60 0.03 -50 -40 10 35 TEMPERATURE (°C) 60 85 -50 -40 -30 -30 -20 -20 -10 -10 0 -15 85 MAX5621 toc09 -90 MAX5621 toc07 0.04 -40 CODE = 4F2C hex EXTERNAL CLOCK MODE NO CLOCK APPLIED 10 TEMPERATURE (°C) 0.05 85 0.001 -20 -15 60 100 DROOP RATE (mV/s) 0.7 35 DROOP RATE vs. TEMPERATURE VDD = +8.55V VSS = -4V CODE = 4F2C hex -12 10 TEMPERATURE (°C) -10 OFFSET VOLTAGE (mV) 0.8 -40 -15 OFFSET VOLTAGE MAX5621 toc04 0.9 MAX5621 toc03 MAX5621 toc02 0.2 4018 11769 19520 27271 35021 42723 58268 1.0 DIFFERENTIAL NONLINEARITY (LSB) 0.6 MAX5621 toc06 0.003 1.0 0.010 MAX5621 toc08 INTEGRAL NONLINEARITY (%) 0.005 1.4 DIFFERENTIAL NONLINEARITY (LSB) MAX5621 toc01 0.007 GAIN ERROR (%) INTEGRAL NONLINEARITY VS. TEMPERATURE DIFFERENTIAL NONLINEARITY vs. CODE INTEGRAL NONLINEARITY (%) INTEGRAL NONLINEARITY vs. CODE 0.01 0.1 1 FREQUENCY (kHz) 10 100 0 0.001 0.01 0.1 1 10 100 FREQUENCY (kHz) _______________________________________________________________________________________ 5 MAX5621/MAX5622/MAX5623 Typical Operating Characteristics (VDD = +10V, VSS = -4V, VREF = +2.5V, VGS = 0V, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = +10V, VSS = -4V, VREF = +2.5V, VGS = 0V, TA = +25°C, unless otherwise noted.) LOGIC SUPPLY CURRENT SUPPLY CURRENT vs. TEMPERATURE VS. LOGIC INPUT HIGH VOLTAGE 600 500 1000 800 600 400 5.25 28 ISS 26 INTERFACE INACTIVE fSCLK = 20MHz 20 0 5.00 30 22 INTERFACE INACTIVE 400 IDD 32 24 200 4.75 34 SUPPLY CURRENT (mA) 700 36 MAX5621 toc11 800 1200 LOGIC SUPPLY CURRENT (µA) MAX5621 toc10 900 MAX5621 toc12 LOGIC SUPPLY CURRENT vs. LOGIC SUPPLY VOLTAGE LOGIC SUPPLY CURRENT (µA) MAX5621/MAX5622/MAX5623 16-Bit DACs with 16-Channel Sample-and-Hold Outputs 2.0 5.50 2.5 3.0 3.5 4.0 4.5 -40 5.0 -15 10 35 60 LOGIC SUPPLY VOLTAGE (V) LOGIC INPUT HIGH VOLTAGE (V) TEMPERATURE (°C) POSITIVE SETTLING TIME (8V STEP) NEGATIVE SETTLING TIME (8V STEP) POSITIVE SETTLING TIME (100mV STEP) MAX5621 toc13 MAX5621 toc14 MAX5621 toc15 3.5V 3.5V 3.5V ECLK ECLK ECLK 85 0V 0V 0V 5V/div VOUT_ 50mV/div AC-COUPLED VOUT_ 5V/div VOUT_ 1µs/div 1µs/div 1µs/div NEGATIVE SETTLING TIME (100mV STEP) OUTPUT NOISE MAX5621 toc16 MAX5621 toc17 3.5V ECLK 0V OUT_ 50mV/div AC-COUPLED VOUT_ 1µs/div 6 1mV/div 250µs/div _______________________________________________________________________________________ 16-Bit DACs with 16-Channel Sample-and-Hold Outputs PIN NAME FUNCTION TQFP THIN QFN 1, 2, 20, 22, 24, 27, 29, 34, 36, 38, 42, 44, 50, 52, 54, 57, 59, 61 1, 2, 17, 21, 23, 25, 28, 30, 34, 36, 38, 40, 44, 46, 51, 53, 55, 57, 60, 62, 64, 68 N.C. 3 3 GS 4 4 VLDAC 5 5 RST Reset Input 6 6 CS Chip-Select Input 7 7 DIN Serial Data Input 8 8 SCLK 9 9 VLOGIC +5V Logic Power Supply 10 10 IMMED Immediate Update Mode 11 11 ECLK 12 12 CLKSEL 13 13 DGND No Connection. Not internally connected. Ground-Sensing Input +5V DAC Power Supply Serial Clock Input External Sequencer Clock Input Clock-Select Input Digital Ground 14 14 VLSHA +5V Sample-and-Hold Power Supply 15, 25, 40, 55, 62 15, 26, 42, 58, 65 AGND Analog Ground 16, 32, 46 16, 33, 48 VSS Negative Power Supply 17, 39, 48 18, 41, 50 VDD Positive Power Supply 18, 33, 49 19, 35, 52 CL 19 20 OUT0 Output 0 21 22 OUT1 Output 1 23 24 OUT2 Output 2 26 27 OUT3 Output 3 28 29 OUT4 Output 4 30 31 OUT5 Output 5 35 37 OUT6 Output 6 37 39 OUT7 Output 7 41 43 OUT8 Output 8 43 45 OUT9 Output 9 Output Clamp Low Voltage 45 47 OUT10 31, 47, 64 32, 49, 67 CH Output 10 51 54 OUT11 Output 11 53 56 OUT12 Output 12 56 59 OUT13 Output 13 58 61 OUT14 Output 14 60 63 OUT15 Output 15 63 66 REF Output Clamp High Voltage Reference Voltage Input _______________________________________________________________________________________ 7 MAX5621/MAX5622/MAX5623 Pin Description MAX5621/MAX5622/MAX5623 16-Bit DACs with 16-Channel Sample-and-Hold Outputs CH OUT0 ECLK CLKSEL CLOCK SAMPLEAND-HOLD ARRAY R E G I S T E R SAMPLE DATA READY SEQUENCER OUT15 CL READ ENABLE SEQUENTIAL ADDRESS LAST ADDRESS CS SCLK DIN 16 x 16 SRAM 2:1 M U X R E G I S T E R MAX5621 MAX5622 MAX5623 WRITE ENABLE IMMED RST GS REF ADDR SELECT SERIAL INTERFACE GAIN AND OFFSET CORRECTION 16-BIT DAC D[15:0] Figure 1. Functional Diagram tCSH1 CS tCSHO tCSSO tCH tCSS1 tCL SCLK tDH tDS DIN B23 B22 B0 Figure 2. Serial Interface Timing Diagram 8 _______________________________________________________________________________________ 16-Bit DACs with 16-Channel Sample-and-Hold Outputs (VSS Digital-to-Analog Converter The MAX5621/MAX5622/MAX5623 16-bit digital-to-analog converters (DACs) are composed of two matched sections. The four MSBs are derived through 15 identical matched resistors and the lower 12 bits are derived through a 12-bit inverted R-2R ladder. The device has a fixed theoretical output range determined by the reference voltage, gain, and midscale offset. The output voltage for a given input code is calculated with the following: Sample-and-Hold Amplifiers The MAX5621/MAX5622/MAX5623 contain 16 buffered sample/hold circuits with internal hold capacitors. Internal hold capacitors minimize leakage current, dielectric absorption, feedthrough, and required board space. The MAX5621/MAX5622/MAX5623 provide a very low 1mV/s droop rate. Output The MAX5621/MAX5622/MAX5623 include output buffers on each channel. The device contains output resistors in series with the buffer output (Figure 3) for ease of output filtering and capacitive load driving stability. Output loads increase the analog supply current (IDD and ISS). Excessively loading the outputs drastically increases power dissipation. Do not exceed the maximum power dissipation specified in the Absolute Maximum Ratings. The maximum output voltage range depends on the analog supply voltages available and the output clamp voltages (see the Output Clamp section): + 0.75V ) ≤ VOUT _ ≤ (VDD - 2.4V ) code VOUT = × VREF × 5.2428 65535 (1.6214 × VREF ) + VGS where code is the decimal value of the DAC input code, VREF is the reference voltage, and VGS is the voltage at the ground-sense input. With a 2.5V reference, the nominal end points are -4.0535V and +9.0535V (Table 1). Note that these are “virtual” internal end-point voltages and cannot be reached with all combinations of negative and positive power-supply voltages. The nominal, usable DAC end-point codes for the selected power supplies can be calculated as: Lower end-point code = 32768 - ((2.5V - (VSS+0.75)) / 200µV) (result ≥ 0) Upper end-point code = 32768 + ((VDD - 2.4 - 2.5V) / 200µV) (result ≤ 65535) VREF DAC DATA CH 16-BIT DAC GAIN AND OFFSET RO CHOLD RL ONE OF 16 SHA CHANNELS GS OUT_ AV = 1 CL Figure 3. Analog Block Diagram Table 1. Code Table DAC INPUT CODE MSB LSB 1111 1111 1111 1111 NOMINAL OUTPUT VOLTAGE (V) 1100 0111 0100 1010 6.15 1000 0000 0000 0000 2.5 0100 1111 0010 1100 0 9.0535 0010 1000 0001 1100 -2.0 0000 0000 0000 0000 -4.0535 VREF = +2.5V Full-scale output Maximum output with VDD = 8.55V Midscale output VOUT_ = 0; all outputs default to this code after power-up Minimum output with VSS = -2.75V Zero-scale output _______________________________________________________________________________________ 9 MAX5621/MAX5622/MAX5623 Detailed Description MAX5621/MAX5622/MAX5623 16-Bit DACs with 16-Channel Sample-and-Hold Outputs The resistive voltage-divider formed by the output resistor (RO) and the load impedance (RL), scales the output voltage. Determine VOUT_ as follows: Scaling Factor = VOUT _ = VCHOLD RL RL + RO × scaling factor Ground Sense The MAX5621/MAX5622/MAX5623 include a groundsense input (GS), which allows the output voltages to be referenced to a remote ground. The voltage at GS is added to the output voltage with unity gain. Note that the resulting output voltage must be within the valid output voltage range set by the power supplies. Output Clamp The MAX5621/MAX5622/MAX5623 clamp the output between two externally applied voltages. Internal diodes at each channel restrict the output voltage to: (VCH + 0.7V ) ≥ VOUT _ ≥ (VCL − 0.7V ) The clamping diodes allow the MAX5621/MAX5622/ MAX5623 to drive devices with restricted input ranges. The diodes also allow the outputs to be clamped during power-up or fault conditions. To disable output clamping, connect CH to VDD and CL to VSS, setting the clamping voltages beyond the maximum output voltage range. Serial Interface The MAX5621/MAX5622/MAX5623 are controlled by an SPI/QSPI/MICROWIRE-compatible 3-wire interface. Serial data is clocked into the 24-bit shift register in an MSB-first format, with the 16-bit DAC data preceding the 4-bit SRAM address, required zero bit, 2-bit control, and a fill 0 (Figure 4). The input word is framed by CS. The first rising edge of SCLK after CS goes low clocks in the MSB of the input word. When each serial word is complete, the value is stored in the SRAM at the address indicated and the control bits are saved. Note that data can be corrupted if CS is not held low for an integer multiple of 24 bits. All of the digital inputs include Schmitt-trigger buffers to accept slow-transition interfaces. Their switching threshold is compatible with TTL and most CMOS logic levels. Table 2. Channel/Output Selection A3 0 A2 0 A1 0 A0 0 OUTPUT OUT0 selected 0 0 0 1 OUT1 selected 0 0 1 0 OUT2 selected 0 0 1 1 OUT3 selected 0 1 0 0 OUT4 selected 0 1 0 1 OUT5 selected 0 1 1 0 OUT6 selected 0 1 1 1 OUT7 selected 1 0 0 0 OUT8 selected 1 0 0 1 OUT9 selected 1 0 1 0 OUT10 selected 1 0 1 1 OUT11 selected 1 1 0 0 OUT12 selected 1 1 0 1 OUT13 selected 1 1 1 0 OUT14 selected 1 1 1 1 OUT15 selected Serial Input Data Format and Control Codes The 24-bit serial input format, shown in Figure 4, comprises 16 data bits (D15–D0), 4 address bits (A3–A0), 1 required zero bit after the address bits, 2 control bits (C1, C0), and a fill zero. The address code selects the output channel as shown in Table 2. The control code configures the device as follows: 1) If C1 = 1, immediate update mode is selected. If C1 = 0, burst mode is selected. 2) If C0 = 0, the internal sequencer clock is selected. If C0 = 1, the external sequencer clock is selected. This must be repeated with each data word to maintain external input. The operating modes can also be selected externally through CLKSEL and IMMED. In the case where the control bit in the serial word and the external signal conflict, the signal that is a logic 1 is dominant. DATA D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 MSB ADDRESS D0 A3 A2 A1 CONTROL A0 Figure 4. Input Word Sequence 10 ______________________________________________________________________________________ 0 C1 C0 0 LSB 16-Bit DACs with 16-Channel Sample-and-Hold Outputs 2/fSEQ UPDATE MODE Immediate update mode UPDATE TIME 2/fSEQ Burst mode 33/fSEQ Modes of Operation The MAX5621/MAX5622/MAX5623 feature three modes of operation: • Sequence mode • Immediate update mode • Burst mode Sequence Mode Sequence mode is the default operating mode. The internal sequencer continuously scrolls through the SRAM, updating each of the 16 SHAs. At each SRAM address location, the stored 16-bit DAC code is loaded to the DAC. Once settled, the DAC output is acquired by the corresponding SHA. Using the internal sequencer clock, the process typically takes 320µs to update all 16 SHAs (20µs per channel). Using an external sequencer clock the update process takes 128 clock cycles (eight clock cycles per channel). Immediate Update Mode Immediate update mode is used to change the contents of a single SRAM location, and update the corresponding SHA output. In immediate update mode, the selected output is updated before the sequencer resumes operation. Select immediate update mode by driving either IMMED or C1 high. The sequencer is interrupted when CS is taken low. The input word is then stored in the proper SRAM address. The DAC conversion and SHA sample in progress are completed transparent to the serial bus activity. The SRAM location of the addressed channel is then modified with the new data. The DAC and SHA are updated with the new voltage. The sequencer then resumes scrolling at the interrupted SRAM address. This operation can take up to two cycles of the sequencer clock. Up to one cycle is needed to allow the sequencer to complete the operation in progress before it is freed to update the new channel. An additional cycle is required to read the new data from memory, update the DAC, and strobe the sample-and-hold. The sequencer resumes scrolling from the location at which it was interrupted. Normal sequencing is suppressed while loading data, thus preventing other channels from SHA ARRAY UPDATE SEQUENCE 1 2 3 7 SKIP 12 7 8 9 CHANNEL 12 UPDATED CS INTERRUPTED CHANNEL REFRESHED LOAD ADDRESS 12 DIN 24-BIT WORD Figure 5. Immediate Update Mode Timing Example being refreshed. Under conditions of extremely frequent immediate updates (i.e., 1000 successive updates), unacceptable droop can result. Figure 5 shows an example of an immediate update operation. In this example, data for channel 12 is loaded while channel 7 is being refreshed. The sequencer operation is interrupted, and no other channels are refreshed as long as CS is held low. Once CS returns high, and the remainder of an fSEQ period (if any) has expired, channel 12 is updated to the new data. Once channel 12 has been updated, the sequencer resumes normal operation at the interrupted channel 7. Burst Mode Burst mode allows multiple SRAM locations to be loaded at high speed. During burst mode, the output voltages are not updated until the data burst is complete and control returns to the sequencer. Select burst mode by driving both IMMED and C1 low. The sequencer is interrupted when CS is taken low. All or part of the memory can be loaded while CS is low. Each data word is loaded into its specified SRAM address. The DAC conversion and SHA sample in progress are completely transparent to the serial bus activity. When CS is taken high, the sequencer resumes scrolling at the interrupted SRAM address. New values are updated when their turn comes up in the sequence. After burst mode is used, it is recommended that at least one full sequencer loop (320µs) is allowed to occur before the serial port is accessed again. This ensures that all outputs are updated before the sequencer is interrupted. ______________________________________________________________________________________ 11 MAX5621/MAX5622/MAX5623 Table 3. Update Mode MAX5621/MAX5622/MAX5623 16-Bit DACs with 16-Channel Sample-and-Hold Outputs 6 7 SKIP +10V +5V 2/fSEQ SHA ARRAY UPDATE SEQUENCE SKIP SKIP 7 8 5 6 7 VLOGIC VLDAC VLSHA CS LOAD MULTIPLE ADDRESSES 0.1µF 0.1µF 33/fSEQ TO UPDATE ALL CHANNELS +2.5V VDD REF OUT0 GS DIN CS OUT1 DIN SCLK Figure 6. Burst Mode Timing Example IMMED Figure 6 shows an example of a burst mode operation. As with the immediate update example, CS falls while channel 7 is being refreshed. Data for multiple channels is loaded, and no channels are refreshed as long as CS remains low. Once CS returns high, sequencing resumes with channel 7 and continues normal refresh operation. Thirty-three fSEQ cycles are required before all channels have been updated. MAX5621 MAX5622 MAX5623 CLKSEL ECLK RST DGND AGND VSS OUT15 CL 0.1µF -4V External Sequencer Clock An external clock can be used to control the sequencer, altering the output update rate. The sequencer runs at 1/4 the frequency of the supplied clock (ECLK). The external clock option is selected by driving either C0 or CLKSEL high. When CLKSEL is asserted, the internal clock oscillator is disabled. This feature allows synchronizing the sequencer to other system operations, or shutting down of the sequencer altogether during high-accuracy system measurements. The low 1mV/s droop of these devices ensures that no appreciable degradation of the output voltages occurs, even during extended periods of time when the sequencer is disabled. Power-On Reset A power-on reset (POR) circuit sets all channels to 0V (code 4F2C hex) in sequence, requiring 320µs. This prevents damage to downstream ICs due to arbitrary reference levels being presented following system power-up. This same function is available by driving RST low. During the reset operation, the sequencer is run by the internal clock, regardless of the state of CLKSEL. The reset process cannot be interrupted, and serial inputs are ignored until the entire reset process is complete. 12 Figure 7. Typical Operating Circuit Applications Information Power Supplies and Bypassing Grounding and power-supply decoupling strongly influence device performance. Digital signals may couple through the reference input, power supplies, and ground connection. Proper grounding and layout can reduce digital feedthrough and crosstalk. At the device level, a 0.1µF capacitor is required for the VDD, VSS, and VL_ pins. They should be placed as close to the pins as possible. More substantial decoupling at the board level is recommended and is dependent on the number of devices on the board (Figure 7). The MAX5621/MAX5622/MAX5623 have three separate +5V logic power supplies, VLDAC, VLOGIC, and VLSHA. VLDAC powers the 16-bit digital-to-analog converter, VLSHA powers the control logic of the SHA array, and VLOGIC powers the serial interface, sequencer, internal clock and SRAM. Additional filtering of V LDAC and VLSHA improves the overall performance of the device. ______________________________________________________________________________________ 16-Bit DACs with 16-Channel Sample-and-Hold Outputs Chip Information CL N.C. OUT11 OUT12 N.C. N.C. AGND OUT13 N.C. 63 62 61 60 59 58 N.C. OUT14 OUT15 VREF 64 N.C. CH TOP VIEW AGND TRANSISTOR COUNT: 16,229 PROCESS: BiCMOS 57 56 55 54 53 52 51 50 49 N.C. 1 48 VDD N.C. 2 47 CH GS 3 46 VSS VLDAC 4 45 OUT10 RST 5 44 N.C. CS 6 43 OUT9 DIN 7 42 N.C. SCLK 8 41 OUT8 VLOGIC 9 MAX5621 MAX5622 MAX5623 IMMED 10 40 AGND 39 VDD ECLK 11 38 N.C. CLKSEL 12 37 OUT7 DGND 13 36 N.C. VLSHA 14 35 OUT6 AGND 15 34 N.C. VSS 16 33 CL VSS CH OUT5 N.C. OUT4 N.C. OUT3 AGND N.C. OUT2 N.C. N.C. OUT1 OUT0 CL VDD 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 TQFP ______________________________________________________________________________________ 13 MAX5621/MAX5622/MAX5623 Pin Configurations (continued) MAX5621/MAX5622/MAX5623 16-Bit DACs with 16-Channel Sample-and-Hold Outputs Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 14 ______________________________________________________________________________________ 16-Bit DACs with 16-Channel Sample-and-Hold Outputs 68L QFN THIN.EPS PACKAGE OUTLINE 68L QFN THIN, 10x10x0.8 MM 21-0142 A ______________________________________________________________________________________ 15 MAX5621/MAX5622/MAX5623 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) MAX5621/MAX5622/MAX5623 16-Bit DACs with 16-Channel Sample-and-Hold Outputs Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) PACKAGE OUTLINE 68L QFN THIN, 10x10x0.8 MM 21-0142 A Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.