MAXIM MAX2150ETI

19-2389; Rev 3; 3/06
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
The MAX2150 is a complete wideband direct upconversion quadrature modulator IC incorporating a 28-bit
sigma-delta fractional-N synthesizer. The device is targeted for applications in the 700MHz to 2300MHz frequency range.
The super-high-resolution sigma-delta fractional-N synthesizer is capable of better than 50mHz resolution
when used with a 10MHz reference. Other features:
fully differential I/Q modulation inputs, an internal LO
buffer, and a 50Ω wideband output driver amplifier.
A standard 3-wire interface is provided for synthesizer
programming and overall device configuration. An onchip low-noise crystal oscillator amplifier is also included and can be configured as a buffer when an external
reference oscillator is used.
The device typically achieves 34dBc of carrier and sideband suppression at a -1dBm output level. The wideband, internally matched RF output can also
be disabled while the synthesizer and 3-wire bus remain
powered up for continuous programming.
The device consumes 72mA from a single +3.0V supply and is packaged in an ultra-compact 28-pin QFN
package (5mm ✕ 5mm) with an exposed pad.
Applications
Wireless Broadband
Features
♦ Single Voltage Supply (2.7V to 3.6V)
♦ 75MHz 3dB I/Q Input Bandwidth
♦ Wideband 50Ω RF Output: 700MHz to 2300MHz
♦ Ultra-Fine Frequency Resolution: 100mHz
♦ High Reference Frequency for Fast-Switching
Applications
♦ Ultra-Low Phase Noise
♦ Low Spurious and Reference Emissions
♦ -1dBm RMS Output Power
♦ 60dB RF Muting Control
♦ 34dBc Typical Carrier Suppression
♦ 34dBc Typical Sideband Suppression
♦ Software- and Hardware-Controlled Shutdown
Modes
Ordering Information
TEMP RANGE
PIN-PACKAGE
MAX2150ETI
PART
-40°C to +85°C
28 Thin QFN-EP*
MAX2150ETI+
-40°C to +85°C
28 Thin QFN-EP*
*EP = Exposed paddle.
+Denotes lead-free package.
Satellite Uplink
Pin Configuration/
Functional Diagram
LMDS
Wireless Base Station
VCC_RF
I+
I-
Q+
Q-
28
27
26
25
24
BUFEN BUFOUT
23
22
TXEN
1
21 LO+
VCC_PA
2
20 LO-
RFOUT
3
N.C.
4
N.C.
5
LOCK
6
VCC_SD
0
19 VCC_LO
90
18 VCC_D
1/N
MAX2150
∑ ∆ – MOD
PFD
CHP
16 CHP
1/R
PROGRAMMING
AND CONTROL
7
17 VCC_A
15 VCC_CHP
8
9
10
11
CLK
DATA
EN
SHDN
12
13
14
SYNEN OSCIN VCC_XTAL
QFN
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX2150
General Description
MAX2150
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +6.0V
RF Signals: LO+, LO-, OSCIN ........................................+10dBm
I+ to I-, Q+ to Q-.......................................................................2V
LO+, LO-, I+, I-, Q+, Q-, BUFEN, TXEN, CLK, DATA,
EN, SYNEN, OSCIN, OSCOUT, BUFOUT, CHP,
SHDN, LOCK, VCC_CP to GND..............-0.3V to (VCC + 0.3V)
Digital Input Current .........................................................±10mA
Short-Circuit Duration RFOUT, BUFOUT, OSCOUT,
Lock, CHP...........................................................................10s
Continuous Power Dissipation
28-Pin TQFN (TA = +70°C)..................................................2W
(derate 28.5mW/°C above +70°C)
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature Range ..........................................+150°C
Storage Temperature.........................................-65°C to +150°C
Lead Temperature (soldering 10s) ..................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION! ESD SENSITIVE DEVICE
DC ELECTRICAL CHARACTERISTICS
(MAX2150 EV kit. VCC = +2.7V to +3.6V, GND = 0V, SHDN = PLLEN = TXEN = high, BUFEN= low. No AC input signals. RFOUT and
BUFOUT output ports are terminated in 50Ω. TA = -40°C to +85°C. Typical values are at VCC = +3V, TA = +25°C, unless otherwise
noted.) (Note 1)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
2.7
3
3.6
V
TX mode, SHDN = PLLEN = TXEN = high
BUFEN = low
72
107
SYNTH mode, SHDN = PLLEN = high, TXEN =
BUFEN = low
25
38
MOD mode, SHDN = TXEN = high, SYNEN =
BUFEN = low
46
69
SUPPLY
Supply Voltage
Supply Current
LO Buffer Supply Current
Shutdown Supply Current
Additional current in all modes for BUFEN = high
3.3
5.5
HW_SHDN mode, SHDN = low
0.3
600
SW_SHDN mode, PWDN bit at logic low
35
600
mA
mA
µA
CONTROL INPUT/OUTPUTS (SHDN, TXEN, SYNEN, BUFEN)
Input Logic High
2
V
Input Logic Low
Input Logic High Current
Input Logic Low Current
-1
Lock Detect High (Locked)
2
0.5
V
1
µA
µA
V
Lock Detect Low (Unlocked)
0.5
V
Power-Up Time
MOD mode
25
µs
Power-Down Time
MOD mode
1
µs
3-WIRE CONTROL INPUT (CLK, DATA, EN)
Input Logic High
VCC 0.5
Input Logic Low
Input Logic High Current
Input Logic Low Current
2
-1
_______________________________________________________________________________________
V
0.5
V
1
µA
µA
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
(MAX2150 EV kit. VCC = +2.7V to +3.6V, SHDN = PLLEN = TXEN = high, BUFEN =low. Input I/Q signals: FI/Q = 500kHz, VI/Q = 1VP-P.
I+, Q+ single-ended input, driven from AC-coupled source. I-, Q- single-ended inputs are AC-coupled to GND. RFOUT and BUFOUT
output ports are terminated in 50Ω loads. fLO =1750MHz, PLO = -10dBm, typical values are at VCC = +3V, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
MODULATION INPUT
I/Q Input Bandwidth
I/Q Differential Input Level
BW (-1dB)
26
BW (-3dB)
75
Assumes a sine-wave input to achieve the RFOUT output
power specified below
1
I/Q DC Input Resistance
I/Q Common-Mode Input Range
MHz
VP-P
200
(Note 2)
1.5
1.6
kΩ
1.7
V
2300
MHz
RF OUTPUT
Frequency Range
700
TXEN = high, fRF = 1750MHz
Output Power
-7
TXEN = low, fRF = 1750MHz
Output 1dB Compression Point
Output IP3
Carrier Suppression
fRF = 1750MHz
Sideband Suppression
fLO - fI/Q, fRF = 1750MHz
RF Output Noise Floor
fOFFSET > 40MHz (Note 2)
Output Return Loss
(Note 3)
-1
dBm
-60
25
1
dBm
14
dBm
34
dBc
34
dBc
-148
-143
-9
dBm/Hz
dB
LO INPUT/OUTPUT
Frequency Range
700
LO Input Power
(Note 2)
LO Input Return Loss
fLO =2000MHz
LO Buffer Output Level
BUFEN = high (Note 2)
-12
-14
-10
2300
MHz
-7
dBm
-15
dB
-9.5
dBm
SIGMA-DELTA FRACTIONAL-N SYNTHESIZER
SYSTEM REQUIREMENTS
Frequency Range
(Note 2)
Phase-Detector Input-Referred
Phase Noise Floor
fCOMP = fREF = 20MHz, CP0 = CP1 = CPX = 1 (Note 4)
-138
dBc/Hz
In-Loop Spurious Emissions
fLO = 1740.005MHz, fCOMP = fREF = 20MHz, CP0 = CP1
= CPX = 1 (Note 5)
-40
dBc
700
2300
MHz
MAIN DIVIDER AND PHASE DETECTOR
Minimum Fractional-N Step Size
fCOMP/
228
Phase-Detector Comparison
Frequency
20
Maximum N Division
251
Minimum N Division
35
30
MHz
_______________________________________________________________________________________
3
MAX2150
AC ELECTRICAL CHARACTERISTICS
MAX2150
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX2150 EV kit. VCC = +2.7V to +3.6V, SHDN = PLLEN = TXEN = high, BUFEN = low. Input I/Q signals: FI/Q = 500kHz, VI/Q = 1VP-P.
I+, Q+ single-ended input, driven from AC-coupled source. I-, Q- single-ended inputs are AC-coupled to GND. RFOUT and BUFOUT
output ports are terminated in 50Ω loads. fLO =1750MHz, PLO = -10dBm, typical values are at VCC = +3V, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
REFERENCE OSCILLATOR AND DIVIDER
Input Frequency Range
AC-Coupled Input Sensitivity
AC-coupled, single ended (Note 2)
Reference Division Ratio
(Notes 2, 6)
10
50
MHz
0.4
2.3
VP-P
1
4
CHARGE-PUMP OUTPUT
CP1, CP0 = 00
CP1, CP0 = 01
Charge-Pump Current (Note 7)
CP1, CP0 = 10
CP1, CP0 = 11
Charge-Pump Voltage
Compliance
Sink/source currents match within ±5%
CPX = 0
0.12
0.17
0.22
CPX = 1
0.23
0.34
0.44
CPX = 0
0.23
0.35
0.46
CPX = 1
0.47
0.67
0.88
CPX = 0
0.36
0.52
0.68
CPX = 1
0.70
1.00
1.30
CPX = 0
0.48
0.69
0.90
CPX = 1
0.91
1.31
0.5
mA
1.70
VCC 0.5
V
Note 1: Parameters are guaranteed by production testing at +25°C and +85°C. Minimum and maximum values over the temperature and supply voltage range are guaranteed by design and characterization.
Note 2: Guaranteed by design and characterization.
Note 3: Measured with MAX2150 EV kit.
Note 4: Measured with an on-chip crystal oscillator.
Note 5: In-loop spurious emissions occur when synthesizing a frequency at an integer multiple of the comparison frequency with
fractional offset within the PLL loop BW.
Note 6: If an on-chip oscillator is used, a fundamental tone crystal is needed.
Note 7: Minimum and maximum values at CPX = 1 are guaranteed by production testing. Values at CPX = 0 are guaranteed by
design and characterization.
4
_______________________________________________________________________________________
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
60
-40°C
40
20
+85°C
-4
+25°C
-6
-8
-10
-12
2.7
3.0
3.6
3.3
1100
1500
1900
OUTPUT POWER vs. LO POWER
CARRIER AND SIDEBAND
SUPPRESSIONS vs. LO POWER
MAX2150 toc04
-1.2
-1.3
-1.4
-1.5
-1.6
-1.7
-1.8
-1.9
CARRIER AND SIDEBAND SUPPRESSIONS (dB)
FREQUENCY (MHz)
-1.1
7
8
9
10
LO POWER (dBm)
11
12
-58
-40°C
-61
+25°C
-64
+85°C
-67
2300
700
1100
1500
1900
2300
FREQUENCY (MHz)
38
MODULATOR OUTPUT POWER
vs. I/Q INPUT LEVEL
37
36
SIDEBAND SUPPRESSION
35
34
CARRIER SUPPRESSION
33
32
-2.0
TXEN = LOW
-70
700
SUPPLY VOLTAGE (V)
-1.0
OUTPUT POWER (dBm)
-2
4
MODULATOR OUTPUT POWER (dBm)
0
-40°C
0
-55
MAX2150 toc06
+25°C
MAX2150 toc05
SUPPLY CURRENT (mA)
80
TXEN = HIGH
2
MODULATION OUTPUT POWER (dBm)
+85°C
4
MODULATION OUTPUT POWER
vs. FREQUENCY
MAX2150 toc02
TX MODE
MODULATION OUTPUT POWER (dBm)
MAX2150 toc01
100
MODULATION OUTPUT POWER
vs. FREQUENCY
MAX2150 toc03
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
0
-40°C
-4
+25°C
-8
-12
+85°C
-16
-20
-24
7
8
9
10
LO POWER (dBm)
11
12
0
200
400
600
800 1000 1200 1400
I/Q INPUT LEVEL (mV)
_______________________________________________________________________________________
5
MAX2150
Typical Operating Characteristics
(MAX2150 EV kit. VCC = +3V, SHDN = PLLEN = TXEN = high, BUFEN = low. Input I/Q signals: FI/Q = 500kHz, VI/Q = 1VP-P. I+, Q+ single-ended input, driven from AC-coupled source. I-, Q- single-ended inputs are AC-coupled to GND. RFOUT and BUFOUT output ports
are terminated in 50Ω loads. fLO =1750MHz, PLO = -10dBm, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(MAX2150 EV kit. VCC = +3V, SHDN = PLLEN = TXEN = high, BUFEN = low. Input I/Q signals: FI/Q = 500kHz, VI/Q = 1VP-P. I+, Q+
single-ended input, driven from AC-coupled source. I-, Q- single-ended inputs are AC-coupled to GND. RFOUT and BUFOUT output
ports are terminated in 50Ω loads. fLO =1750MHz, PLO = -10dBm, TA = +25°C, unless otherwise noted.)
MODULATOR OUTPUT IP3 vs. VCC
+25°C
13
12
-40°C
11
+85°C
2.0
+25°C
1.5
1.0
0.5
0
10
3.0
3.6
3.3
-10
-15
-20
-30
-1.0
2.7
-5
-25
-40°C
-0.5
MAX2150 toc09
2.5
0
LO PORT RETURN LOSS (dB)
14
MAX2150 toc08
15
3.0
MODULATOR OUTPUT P1dB (dBm)
+85°C
LO PORT INPUT RETURN LOSS
vs. FREQUENCY
MODULATOR OUTPUT P1dB vs. VCC
MAX2150 toc07
2.7
3.0
700
3.6
3.3
1100
1500
1900
VCC (V)
VCC (V)
FREQUENCY (MHz)
BUFOUT PORT RETURN LOSS
vs. FREQUENCY
LO BUFFER OUTPUT POWER
vs. FREQUENCY
LO BUFFER OUTPUT POWER
vs. FREQUENCY
-10
-15
-20
-25
-6
+85°C
-7
-8
+25°C
-9
-10
-40°C
-11
-12
-40
2300
MAX2150 toc12
BUFEN = HIGH
-5
BUFEN = LOW
LO BUFFER OUTPUT POWER (dBm)
-5
-4
LO BUFFER OUTPUT POWER (dBm)
MAX2150 toc10
0
MAX2150 toc11
MODULATOR OUTPUT IP3 (dBm)
16
BUFOUT PORT RETURN LOSS (dB)
MAX2150
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
-43
-46
+25°C
+85°C
-49
-52
-40°C
-13
-14
-30
700
1100
1500
FREQUENCY (MHz)
6
1900
2300
-55
700
1100
1500
FREQUENCY (MHz)
1900
2300
700
1100
1500
FREQUENCY (MHz)
_______________________________________________________________________________________
1900
2300
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
OSCIN PORT SENSITIVITY
(SYNTHESIZER) vs. FREQUENCY
OSCIN IMPEDANCE vs. FREQUENCY
0.60
0
REAL
0.50
4
+25°C
0.40
+85°C
0.30
3
+25°C
0.20
2
+85°C
0.10
1
0
0
15
-200
-300
IMAGINARY
-400
-500
-600
-700
-800
-900
-40°C
10
OSCIN PORT IMPEDANCE (Ω)
-40°C
20
25
30
35
40
45
-1000
50
10
15
FREQUENCY (MHz)
SYNTHESIZER PHASE NOISE
0
-10
-8.5dBm
-20
30
35
40
45
50
I/Q MODULATOR OUTPUT SPURS
-20
-30
-40
-50
-50
N/C = -99dBc/Hz
1 AVG
CARRIER
SUPPRESSION
-34dBc SIDEBAND
SUPPRESSION
-36dBc
-60
-70
-70
-80
-80
-90
-90
-100
-100
SPAN = 20kHz
MAX2150 toc16
-10
-40
CENTER = 1.75MHz
25
0
-30
-60
20
FREQUENCY (MHz)
MAX2150 toc15
OSCIN PORT SENSITIVITY (V)
-100
5
MAX2150 toc14
MAX2150 toc13
6
CENTER = 1.75 GHz
SPAN = 2 MHz
_______________________________________________________________________________________
7
MAX2150
Typical Operating Characteristics (continued)
(MAX2150 EV kit. VCC = +3V, SHDN = PLLEN = TXEN = high, BUFEN = low. Input I/Q signals: FI/Q = 500kHz, VI/Q = 1VP-P. I+, Q+
single-ended input, driven from AC-coupled source. I-, Q- single-ended inputs are AC-coupled to GND. RFOUT and BUFOUT output
ports are terminated in 50Ω loads. fLO =1750MHz, PLO = -10dBm, TA = +25°C, unless otherwise noted.)
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
MAX2150
Pin Description
PIN
8
NAME
FUNCTION
Modulator Enable Input. Set TXEN low to inhibit the RF and modulator circuits. This mode can be used
for quiet frequency synthesis.
1
TXEN
2
VCC_PA
Supply Voltage Input for RFOUT Output Driver Circuits. Bypass as close to the pin as possible. The
bypass capacitor should not share ground vias with other branches.
3
RFOUT
Modulator RF Output. This is a wideband, internally matched 50Ω output. A DC-blocking capacitor is
required.
4, 5
N.C.
6
LOCK
Do Not Connect. (These pins must be left floating.)
7
VCC_SD
Supply Voltage Input for Sigma-Delta Modulator Circuits. Bypass as close to the pin as possible. The
bypass capacitor should not share ground vias with other branches.
8, 9, 10
CLK, DATA,
EN
Input Pins from 3-Wire Serial Bus. An RC lowpass filter on each of these pins can be used to reduce
digital noise.
11
SHDN
Shutdown Control. Set SHDN low to disable all internal circuits for lowest power consumption. An RC
lowpass filter can be used to reduce digital noise.
12
SYNEN
Synthesizer Enable Input. Set SYNTH low to disable the internal frequency synthesizer. An RC lowpass
filter can be used to reduce digital noise.
13
OSCIN
Reference Oscillator Input. Connect a parallel, resonant, fundamental-tone crystal between this pin and
ground to facilitate a crystal oscillator circuit. For applications with an external reference oscillator, the
OSCIN input can be driven through a large-value series capacitor.
14
VCC_XTAL
Supply Voltage Input for Crystal Oscillator. Bypass as close to the pin as possible. The bypass capacitor
should not share ground vias with other branches.
15
VCC_CHP
Supply Voltage Input for Charge Pump. Bypass as close to the pin as possible. The bypass capacitor
should not share ground vias with other branches.
16
CHP
17
VCC_A
Supply Voltage Input for PLL. Bypass as close to the pin as possible. The bypass capacitor should not
share ground vias with other branches.
18
VCC_D
Supply Voltage Input for PLL. Bypass as close to the pin as possible. The bypass capacitor should not
share ground vias with other branches.
19
VCC_LO
Supply Voltage Input for Internal LO Circuits. Bypass as close to the pin as possible. The bypass
capacitor should not share ground vias with other branches.
20, 21
LO-, LO+
Differential Local-Oscillator Input. These inputs require DC-blocking capacitors. The LO can be applied
with a single-ended input to the LO+/LO- pin. In this mode, the other pin should be AC-grounded.
22
BUFOUT
Lock Status of the PLL. A static logic-level high indicates that the PLL is in the locked condition.
High-Impedance Charge-Pump Output. Connect to the tune input of the VCO through the PLL loop filter.
Keep the line from this pin to the tune input as short as possible to prevent spurious pickup, and
connect the loop filter as close to the tune input as possible.
Buffered LO Output. Internally matched to 50Ω, requires a DC-blocking capacitor.
23
BUFEN
LO Output Buffer Amplifier Enable. Set BUFEN high to enable the on-chip output LO buffer for driving
external circuits. An RC lowpass filter can be used to reduce digital noise.
24, 25
Q-, Q+
Differential Q-Channel Baseband Inputs to the Modulator. These pins connect directly to the bases of
a differential pair and require an external common-mode bias voltage of 1.6V.
_______________________________________________________________________________________
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
PIN
NAME
FUNCTION
26, 27
I-, I+
Differential I-Channel Baseband Inputs to the Modulator. These pins connect directly to the bases of a
differential pair and require an external common-mode bias voltage of 1.6V.
28
VCC_RF
Supply Voltage Input for RF Circuits. Bypass as close to pin as possible. The bypass capacitor should
not share ground vias with other branches.
—
Exposed pad Ground
Detailed Description
Internally, the MAX2150 includes a broadband I/Q
modulator, internally matched broadband output driver
amplifier, fine-resolution fractional-N frequency synthesizer, an LO buffer amplifier, and an on-chip low-noise
crystal oscillator circuit.
A simple 3-wire interface is provided for synthesizer
programming and device configuration and control.
Independent hardware and software power-down control of the I/Q modulator, frequency synthesizer, and LO
buffer amplifier is provided, as well as the ability to shut
down the entire chip.
I/Q Modulator
The MAX2150 modulator is composed of a pair of
matched double-balanced mixers, a broadband passive LO quadrature generator, and a summing amplifier. The mixers accept differential I/Q baseband signals
that directly modulate the internal 0° and 90° LO signals applied to the I/Q mixers. An external LO source
drives an internal LO quadrature generator that shifts
the phase of the LO signal applied to the Q mixer by
90° relative to the LO signal applied to the I-channel
mixer. The modulated output of the I/Q mixers is
summed together, and the undesired sideband is suppressed.
The I+, I-, Q+, and Q- input ports feature high-linearity
buffer amplifiers with a typical -3dB bandwidth of
75MHz and accept differential input voltages up to
1VP-P. The ports require external biasing and have an
input common-mode requirement of 1.6V. For singleended operation, bypass the I and Q ports to ground.
See the Typical Application Circuit for recommended
component values.
The broadband output driver amplifier is matched on
chip across the entire operating frequency range and
requires an output DC-blocking capacitor. For optimum
performance, the output match can be improved with
simple L-section and/or PI-section matching networks.
Always ensure that DC blocking is provided, because
internal bias voltages are present at this output.
The modulator can be shut down with both hardware
(pin 1) and software (TE bit). This mode is useful for
quiet synthesizer programming or to mute the RF output signal. The hardware pin and software bits must be
set to logic-1 to enable the modulator. If the hardware
pin or software bit is set to logic-0, or if both are set to
logic-0, the modulator is disabled.
LO Buffer Amplifier
The broadband buffer amplifier output is internally
matched and requires a DC-blocking capacitor to isolate on-chip bias voltages. Power-down of the LO buffer
can be controlled by both BUFEN (pin 23), as well as
BUFEN by software by setting the BUFEN (BE) bit
through the 3-wire interface. The hardware pin and the
software bit must be a logic-1 to enable the buffer. If
the hardware or software bit is set to logic-0, the LO
buffer is disabled.
Frequency Synthesizer
The MAX2150 features an internal 28-bit sigma-delta
frequency synthesizer. This architecture enables the
use of very high (30MHz) comparison frequencies,
which significantly reduces the in-loop phase noise as
a result of reduced division ratios. The high comparison
frequency also allows significantly increased PLL
bandwidths for very fast switching speed applications.
Divider Programming
The MAX2150 frequency programming is determined
as follows. The overall division ratio (D) has an integer
value (N), as well as a fractional component (F):
D = N.F = N +F / 228
The N and F values are encoded as straight binary
numbers. Determination of these values is illustrated by
the following example:
FLO = 1721.125MHz, FCOMP = 20MHz
Then:
D = 1721.125 / 20 = 86.05625
Therefore:
N = 86 and F = 0.05625 x 228 = 15,099,494
_______________________________________________________________________________________
9
MAX2150
Pin Description (continued)
MAX2150
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
Converting each to binary representation results in the
following:
N register = 86 = 0101,0110
F register value =
0000,1110,0110,0110,0110,0110,0110
The F-register value is then split between an upper 14
bits and a lower 14 bits as follows:
Upper 14 bits + address 00 = 0000,1110,0110,0100
Lower 14 bits + address 01 = 1001,1001,1001,1001
Synthesizer Shutdown
The synthesizer can be disabled by setting SYNEN (pin
12) to a logic low. This mode is useful when an external
frequency synthesizer is employed.
Applications Information
Serial Interface and Register Definition
3-Wire Interface and Registers
The MAX2150 is programmed through a simple
3-wire (CLK, DATA, EN) interface. The programming
data is contained within 16-bit words loaded into four
unique address locations. Each location contains programming information for setting operational modes
and device configuration. Two words (address 00, 01)
control the fractional divide number in the sigma-delta
synthesizer. The third word (address 10) sets the integer divide value, reference divide value, charge-pump
current, and charge-pump compensation DAC settings.
The fourth and final word (address 11) contains various
device configuration registers and test registers, as
well as additional charge-pump compensation registers. See Tables 1 through 11 for details.
3-Wire Interface Timing Diagram
Figure 1 shows the programming logic. The 16-bit shift
register is programmed by clocking in data at the rising
edge of CLK. Pulling enable low allows data to be
clocked into the shift register; pulling enable high loads
the register addressed.
DATA
B19 (MSB)
B18
B0
Fractional Spurs
When synthesizing a frequency that is an integer multiple of the reference divider and having a fractional offset with a value less than the PLL filter bandwidth,
fractional spurs can be observed at a typical level of
-40dBc. For example, to synthesize 1640.005MHz
when using a 20MHz reference and a PLL bandwidth of
25kHz, spurious products offset from the LO by 5kHz
can be observed. The 1640MHz is an integer multiple
of 20MHz, and the fractional offset of 5kHz is within the
PLL bandwidth.
It is possible to avoid the above-mentioned spurious
products by using two reference oscillators with slightly
offset frequencies or by using a higher reference frequency and changing the comparison frequency of the
reference divider.
Crystal Oscillator
The MAX2150 includes a simple-to-use on-chip lownoise reference oscillator circuit. The oscillator is
formed by connecting a fundamental mode parallel resonant crystal from OSCIN to ground. The oscillator circuit is useful from 10MHz to 50MHz.
The phase noise of the MAX2150 can be improved by
using a precision high-frequency external reference
oscillator (TCXO). The external oscillator is connected
through a DC-blocking capacitor directly to the OSCIN
pin.
Layout Considerations
A properly designed PC board is an essential part of
any RF circuit. A ground plane is essential. Keep RF
signal lines as short as possible to reduce losses, radiation, and inductance. The exposed pad on the underside of the MAX2150 must be adequately grounded by
ensuring that the exposed paddle of the device package is soldered evenly to the board ground plane. Use
multiple, low-inductance vias to ground the exposed
paddle.
A3
A1
A0 (LSB)
CLK
tCWL
tCS
tCH
tCWH
tCS > 50ns
tCH > 10ns
tCWH > 50ns
tES > 50ns
tCWL > 50ns
tEW > 50ns
tES
EN
tEW
Figure 1. 3-Wire Interface Timing Diagram
10
______________________________________________________________________________________
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
MAX2150
Table 1. Register Tables
MSB
SHIFT REGISTER DATA
LSB
ADDRESS
Upper (MSBs) Fractional Divider Value (F) 14 Bits (Default = 8192, 10000000000000)
27
26
25
24
23
22
21
20
19
18
17
16
Address
15
14
0
Lower (LSBs) Fractional Divider Value (F)14 Bits (Default 0 DEC, 00000000000000
13
12
11
R Divider
Default = 00
R1
R0
10
8
CP Bleed
Default = 00
CP Current
Default = 11
LIN1
CP1
LIN0
Reset Delay
Default = 00
BL1
9
7
6
5
4
T5
T4
CP0
T3
2
1
0
0
Integer Divide Value (N) 8 Bits
Default = 177 DEC
7
6
5
4
Test Registers 6 Bits
Default = 0 DEC
BL0
3
3
T1
T0
INT
PD
2
TE
1
BE
1
Address
0
1
Control Register 6 Bits
Default = 15 DEC
T2
0
Address
0
Address
XX
CPX
1
1
Table 2. Reference Divider
R1
R0
REFERENCE DIVIDE VALUE
0
0
1
0
1
2
1
0
3
1
1
4
Table 3. Integer Divider-N*
N7
N6
N5
N4
N3
N2
N1
N0
INTEGER DIVIDE VALUE
0
0
1
0
0
0
1
1
35
0
0
1
0
0
1
0
0
36
—
—
—
—
—
—
—
—
—
1
1
1
1
1
0
1
0
250
1
1
1
1
1
0
1
1
251
*N divider is limited to 35 < N < 251.
Table 4. Fractional Divider-F (Upper 14 Bits)
F27
F26
F25
F24
F23
F22
F21
F20
F19
F18
F17
F16
F15
F14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table 5. Fractional Divider-F (Lower 14 Bits)
F13
F12
F11
F10
F9
F8
F7
F6
F5
F4
F3
F2
F1
F0
INTEGER DIVIDE
VALUE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
1
1
1
1
1
1
1
1
1
1
1
1
0
268435454
1
1
1
1
1
1
1
1
1
1
1
1
1
1
268435455
______________________________________________________________________________________
11
MAX2150
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
Table 6. Control Register
BIT ID
BIT
NAME
PWR-UP
STATE
BIT LOCATION
0 = LSB
CPX
CP_MULT
1
0
FUNCTION
XX
XX
XX
1
A logic high doubles the charge pump current selected through registers
CP1 and CP0. Logic low sets the charge-pump current to the value
selected by registers CP1 and CP0.
Unused.
BE
BUFEN
1
2
High enables the VCO buffer. Low disables this output.
TE
TXEN
1
3
Low enables SW_MUTE mode, which shuts down the RF circuits while
leaving the 3-wire interface, register, and PLL circuits active.
PD
PWDN
0
4
Low enables register-based shutdown. This mode shuts down all circuits
except the 3-wire interface and internal registers.
INT
INT_MODE
0
5
Logic high disables the sigma-delta modulator. Logic low enables the
sigma-delta modulator for normal operation.
Table 7. Device Modes
HW PINS
MODE
SOFTWARE CONTROL
BITS
PWDN
TXEN
BUFEN
DESCRIPTION
SHDN
TXEN
SYNEN
BUFEN
TX
H
H
H
H/L
H
H
H/L
All circuits active.
MOD
H
H
L
H/L
H
H
H/L
Modulator circuits active. Synthesizer
blocks disabled. Mode is used with external
PLL circuit.
H/L
Serial interface and synthesizer blocks
active. RF and modulator blocks disabled.
Mode is used to gate RF ON/OFF with
external logic control.
SYNTH
H
L
H
H/L
H
X
SW_MUTE
H
H
H
H/L
H
L
H/L
Serial interface and synthesizer blocks all
active. Modulator blocks disabled. Mode is
used to gate RF ON/OFF with software
control.
HW_SHDN
L
X
X
X
X
X
X
All circuits disabled. Lowest current mode
of operation.
X
Serial interface and registers active, all
other circuits inactive regardless of the
state of the HW pins with the exception of
HW_SHDN.
SW_SHDN
H
X
X
X
L
Power-Supply (VCC) Bypassing
Proper voltage-supply bypassing is essential to reduce
the spurious emissions mentioned above. It is recommended that each VCC pin be bypassed independently
12
X
and share no common vias with any other ground connection. See the Typical Operating Circuit for suggested bypass component values.
______________________________________________________________________________________
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
TXEN
PIN
0
0
1
1
Table 11. BUFEN Pin and Software Bit
Definitions
BUFEN
TX MODE
BIT
0
1
0
1
PIN
0
0
1
1
TX off
TX off
TX off
TX enabled
Table 9. Charge-Pump Registers
CPX
0
0
0
0
1
1
1
1
CP1
0
0
1
1
0
0
1
1
CP0
0
1
0
1
0
1
0
1
MAX2150
Table 8. TXEN Pin and Software Bit
Definitions
BUF MODE
BIT
0
1
0
1
Buffer off
Buffer off
Buffer off
Buffer on
Chip Information
TRANSISTOR COUNT: 16,321
ICP (µA)
170
350
520
690
340
670
1000
1310
Table 10. Test Register Definition
(Default 0 Dec)*
TEST MODE
T5
T4
T3
T2
T1
T0
TEST PIN
Normal
Operating
Mode
0
0
0
0
0
0
—
Charge Pump
Forced to
Source Icp
0
0
0
0
0
1
CP
Charge Pump
Forced to Sink
Icp
0
0
0
0
1
0
CP
Reference
Divider Output
0
1
0
0
0
0
Lock
Main Divider
Output
0
1
1
0
0
0
Lock
*All other logic states are undefined.
______________________________________________________________________________________
13
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
MAX2150
Typical Operating Circuit
J1
31-5239-52RFX
J2
31-5239-52RFX
I
IN
Q
C50
0.1µF
R31
3.3kΩ
VCC
C52
0.1µF
R1
OPEN
R32
3.3kΩ
R29
OPEN
R2
OPEN
VCC
R33
3.3kΩ
DCIN
C28
0.1µF
QN
BUFEN
R4
OPEN
R3
OPEN
C1
0.1µF
R34
3.3kΩ
VCC
J6
C3
0.1µF
VCC
C25
1µF
J7
R12
0Ω
C2
100pF
VCC
28
VCC_RF
GND
1
27
I+
26
I-
25
Q+
24
Q-
23
BUFEN
C5
OPEN
22
BUFOUT
LO+
TXEN
C33
0.1µF
2
LO-
C18
0.1µF
J15
VCC
3
RFOUT
VCC_LO
LO
20
C8
22pF
RFOUT
C15
OPEN
VCC_PA
LOn
C20
0.1µF
C12
100pF
U1
J16
4
TEST2
VCC
VCC_D
MAX2150
C4
100pF
2
18
3
C10
100pF
VCC
J17
LOCK
J20
5
VCC_A
TEST1
VT
GND
GND
VCC GND OUT
8
5
4
17
C11
100pF
VCC_VCO
J19
6
CHP
LOCK
16
VCC
7
C27
1.0µF
VCC_CHP
VCC_SD
C14
100pF
CLK
8
DATA
9
EN
JUMP_PAD
EN
10
SHDN
SYNEN
OSCIN
11
12
13
R18
0Ω
J10–15
J10–17
J10–19
J10–16
J10–18
J10–20
VCOSEL
J10–13
SYNEN
J10–11
J10–12
J10–14
SHDNn
J10–9
J10–10
TXEN
J10–7
J10–8
FILTVCC
J10–5
J10–6
DATA
J10–3
J10–4
ENn
C21
0.1µF
C13
100pF
J10–1
CLK
C19
0.1µF
14
R24
1.1kΩ
R23
245Ω
J10–2
C36
0.1µF
C30
0.1µF
VCCVCO
GND
VCC
L1
OPEN
J5
J11
15
VCC_XTAL
C37 VCC
0.1µF
LOCK
C9
100pF
SHDN
VCCSD
C34
0.1µF
C35
100pF
C22
6800pF
VCC
14
U2 VC3R0A230967/
1750B350FUJI
7
6
GND VSW
19
1
C16
OPEN
J14
C32
0.1µF
C7
OPEN
VCC
R13
0Ω
C6
OPEN
21
C17
100pF
J8
J13
BUFOUT
C31
0.1µF
C23
.068µF
R25
1.1kΩ
C24
680pF
C26
470pF
VTUNE_OUT
TUNEOUT
Y1
J18 REFL In
______________________________________________________________________________________
R35
OPEN
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
32L QFN.EPS
______________________________________________________________________________________
15
MAX2150
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX2150
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.