SN65512C, SN75512C VACUUM FLUORESCENT DISPLAY DRIVERS SLDS054 – D3516, MAY 1990 • • • • • • Each Device Drives 12 Lines 60-V Output Voltage Swing Capability 25-mA Output Source Current Capability High-Speed Serially-Shifted Data Input TTL-Compatible Inputs Latches on All Driver Outputs description The SN65512C and SN75512C are monolithic BIDFET † integrated circuits designed to drive a dot matrix or segmented vacuum fluorescent display. All device inputs are diode-clamped pnp inputs and assume a high logic level when open circuited. The nominal input threshold is 1.5 V. Outputs are totem-pole structures formed by an npn emitter follower and double-diffused MOS (DMOS) transistors. The device consists of a 12-bit shift register, 12 latches, and 12 output AND gates. Serial data is entered into the shift register on the low-to-high transition of CLOCK. When high, LATCH ENABLE transfers the shift register contents to the outputs of the 12 latches. The active-low STROBE input enables all Q outputs. Serial data output from the shift register can be used to cascade shift registers. This output is not affected by LATCH ENABLE or STROBE. DW OR N PACKAGE (TOP VIEW) Q11 Q12 STROBE SERIAL OUT DATA IN VCC1 CLOCK LATCH ENABLE Q1 Q2 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 Q10 Q9 Q8 Q7 VCC2 GND Q6 Q5 Q4 Q3 logic symbol‡ LATCH ENABLE STROBE 8 TTL / VAC FLUOR DISPLAY 3 SRG12 CLOCK DATA IN 7 C1/ 5 2D 2D The SN65512C is characterized for operation from – 40°C to 85°C. The SN75512C is characterized for operation from 0°C to 70°C. 3 3 2D 3 2D 3 2D 3 2D 3 2D 3 2D 3 2D 3 2D 3 2D 3 2D 3 9 10 11 12 13 14 17 18 19 20 1 2 4 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 SERIAL OUT ‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. † BIDFET – Bipolar, double-diffused, N-channel and P-channel MOS transistors on same chip. This is a patented process. Copyright 1990, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4–1 SN65512C, SN75512C VACUUM FLUORESCENT DISPLAY DRIVERS SLDS054 – D3516, MAY 1990 logic diagram (positive logic) STROBE LATCH ENABLE Shift Register DATA IN CLOCK Latches C2 1D C1 R1 2D LC1 Q1 LC2 Q2 C2 1D R2 2D C1 8 Stages (Q3 thru Q10) Not Shown C2 1D R11 2D C1 1D C1 LC11 Q11 LC12 Q12 C2 R12 2D SERIAL OUT FUNCTION TABLE CONTROL INPUTS FUNCTION SHIFT REGISTER R1 THRU R12 LATCHES LC1 THRU LC12 OUTPUTS CLOCK LATCH ENABLE STROBE Load ↑ No ↑ X X Load and shift† No change Determined by y LATCH ENABLE‡ R12 Determined by STROBE Latch X L H X As determined above Stored data New data R12 Determined by STROBE Strobe X X H L As determined above Determined by y LATCH ENABLE‡ R12 All L LC1 thru LC12, respectively SERIAL Q1 THRU Q12 H = high level, L = low level, X = irrelevant, ↑ = low-to-high-level transition † R12 takes on the state of R11, R11 takes on the state of R10, . . . R2 takes on the state of R1, and R1 takes on the state of the data input. ‡ New data enter the latches while LATCH ENABLE is high. These data are stored while LATCH ENABLE is low. 4–2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65512C, SN75512C VACUUM FLUORESCENT DISPLAY DRIVERS SLDS054 – D3516, MAY 1990 typical operating sequence CLOCK DATA IN Valid Irrelevant SR Contents Invalid Valid LATCH ENABLE New Data Valid Previously Stored Data Latch Contents STROBE Valid Q Outputs schematics of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS VCC1 OUT VCC2 for Q Outputs VCC1 for Serial Output Output Input GND POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4–3 SN65512C, SN75512C VACUUM FLUORESCENT DISPLAY DRIVERS SLDS054 – D3516, MAY 1990 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V Supply voltage, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC1 Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range: SN65512C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C SN75512C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C NOTES: 1. Voltage values are with respect to network GND. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING DW 1125 mW 9.0 mW/°C 720 mW 585 mW N 1150 mW 9.2 mW/°C 736 mW 598 mW recommended operating conditions SN65512C SN75512C MIN MAX MIN MAX Supply voltage, VCC1 5 15 5 15 V Supply voltage, VCC2 0 60 0 60 V High-level input voltage, VIH 2 Low-level input voltage, VIL High-level output current, IOH Low-level output current, IOL VCC1 = 5 V VCC1 = 15 V, Clock frequency, frequency fclock l k VCC1 = 5 V, VCC1 = 15 V, duration CLOCK high or low, low tw Pulse duration, Setup time, time DATA IN before CLOCK ↑ ↑, tsu (see Figure 1) Hold time, time DATA IN after CLOCK ↑, ↑ th (see Figure 1) VCC1 = 5 V, VCC1 = 15 V, VCC1 = 5 V, VCC1 = 15 V, VCC1 = 5 V, 0.8 V – 25 – 25 mA 5 5 mA 0 4 MHz 0 1 MHz 0 4 0 1 TA = 25°C TA = 25°C 100 100 ns 500 500 ns TA = 25°C TA = 25°C 100 100 ns 250 250 ns TA = 25°C TA = 25°C 50 50 ns 250 – 40 POST OFFICE BOX 655303 V 0.8 TA = 25°C TA = 25°C Operating free-air temperature, TA 4–4 2 UNIT • DALLAS, TEXAS 75265 250 85 0 ns 70 °C SN65512C, SN75512C VACUUM FLUORESCENT DISPLAY DRIVERS SLDS054 – D3516, MAY 1990 electrical characteristics over recommended operating free-air temperature range, VCC2 = 60 V PARAMETER TEST CONDITIONS VIK Input clamp voltage II = – 12 mA IOH = – 25 mA, VOH High level output voltage High-level VOL Low level output voltage Low-level IIH IIL High-level input current IOL = 200 µA, VCC1 = 15 V, Low-level input current VCC1 = 15 V, Q outputs SERIAL OUT Q outputs SERIAL OUT IOH = – 200 µA, IOL = 1 mA, ICC1 Supply current from VCC1 VCC1 = 15 V ICC2 Supply current from VCC2 VCC1 = 15 V VCC1 = 5 V VCC1 = 5 V VCC1 = 5 V VCC1 = 5 V MIN TYP† 57.5 58 4.5 4.7 MAX UNIT – 1.5 V V 2.8 5 0.05 0.2 VI = 5 V VI = 0.8 V 0.01 10 µA – 25 – 150 µA VI = 5 V VI = 0.8 V 500 800 µA 2 6 mA V All outputs high 6 12 mA STROBE at 2 V 100 500 µA MIN MAX UNIT † All typical values are at VCC1 = 5 V, TA = 25°C. switching characteristics, VCC1 = 5 V, VCC2 = 60 V, TA = 25°C PARAMETER TEST CONDITIONS tDHL tDLH Delay time, high-to-low level output 300 ns Delay time, low-to-high level output 300 ns tTHL tTLH Transition time, high-to-low level output 500 ns 500 ns pF CL = 30 pF, Transition time, low-to-high level output POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 See Figure 2 4–5 SN65512C, SN75512C VACUUM FLUORESCENT DISPLAY DRIVERS SLDS054 – D3516, MAY 1990 PARAMETER MEASUREMENT INFORMATION tw VIH 1.5 V VIL CLOCK tw th tsu VIH Valid DATA IN VIL Figure 1. Input Timing Voltage Waveforms ≤ 30 ns ≤ 30 ns STROBE 10% tDLH VIH 90% 1.5 V VIL tDLH 90% Q Outputs 10% tTHL tTLH Figure 2. Switching Time Voltage Waveforms 4–6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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