19-3151; Rev 1; 7/04 14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC The MAX1338 14-bit, analog-to-digital converter (ADC) offers four simultaneously sampled, fully differential input channels, with independent track-and-hold (T/H) circuitry for each channel. The input channels are individually software programmable for input ranges of ±10V, ±5V, ±2.5V, and ±1.25V. The input channels feature fault tolerance to ±17V. The internal T/H circuits have a 16ns aperture delay and 100ps aperture-delay matching. A 14-bit parallel bus provides the conversion result with a maximum per-channel output rate of 150ksps (600ksps for all four channels). The MAX1338 has an on-board oscillator and 2.5V internal reference. An external clock and/or reference can also be used. The MAX1338 operates from a +5V supply for analog inputs and digital core. The device operates from a +2.7V to +5.25V supply for the digital I/O lines. The MAX1338 features two power-saving modes: standby mode and shutdown mode. Standby mode allows rapid wake-up and reduces quiescent current to 4mA (typ), and shutdown mode reduces sleep current to less than 10µA (typ). The MAX1338 is available in an 8mm x 8mm x 0.8mm, 56-pin, thin QFN package. The device operates over the extended -40°C to +85°C temperature range. Applications Multiple-Channel Data Recorders Vibration Analysis Features ♦ 150ksps Sample Rate per Channel ♦ All Four Input Channels Simultaneously Sampled 16ns Aperture Delay 100ps Aperture-Delay Matching ♦ Channel-Independent Software-Selectable Input Range: ±10V, ±5V, ±2.5V, ±1.25V ♦ ±17V Fault-Tolerant Inputs ♦ Dynamic Performance at 10kHz Input SNR: 77dB SINAD: 76dB SFDR: 98dBc THD: -83dBc ♦ DC Performance INL: ±2 LSB DNL: ±1 LSB Offset Error: ±4 LSB Gain Error: ±0.1% FSR ♦ 14-Bit Parallel Interface ♦ Internal Clock and Reference Voltage ♦ +5V Analog and Digital Supplies ♦ +2.7V to +5.25V Digital I/O Supply ♦ 56-Pin Thin QFN Package (8mm x 8mm x 0.8mm) Motor Control: 3-Phase Voltage, Current, and Power Measurement Optical Communication Equipment Ordering Information PART MAX1338ETN TEMP RANGE PIN-PACKAGE -40°C to +85°C 56 Thin QFN-EP* *EP = Exposed pad. Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1338 General Description MAX1338 14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC ABSOLUTE MAXIMUM RATINGS CS, RD, WR, CONVST, to DRGND........-0.3V to (DRVDD + 0.3V) SHDN, STANDBY, CLK, EOC, EOLC to DRGND ................................-0.3V to (DRVDD + 0.3V) Maximum Current into Any Pin .........................................±50mA Continuous Power Dissipation (TA = +70°C) 56-Pin Thin QFN (derate 31.3mW /°C above +70°C)....2500mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Maximum Junction Temperature .....................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Junction to Ambient Thermal Resistance θJA ..................32°C/W Junction to Case Thermal Resistance θJC .........................2°C/W AVDD to AGND .........................................................-0.3V to +6V DVDD to DGND.........................................................-0.3V to +6V DRVDD to DRGND ....................................................-0.3V to +6V AVDD to DVDD .......................................................-0.3V to +0.3V DGND to DRGND ..................................................-0.3V to +0.3V AGND to DGND.....................................................-0.3V to +0.3V AGND to DRGND ..................................................-0.3V to +0.3V AIN0+, AIN0-, AIN1+, AIN1-, AIN2+, AIN2-, AIN3+, AIN3- to AGND .....................................................-17V to +17V D0–D13 to DRGND................................-0.3V to (DRVDD + 0.3V) REFADC, REFP1, REFP2, REFN1, REFN2, COM1, COM2 to AGND....................................................-0.3V to (AVDD + 0.3V) INTCLK/EXTCLK to AGND.......................-0.3V to (AVDD + 0.3V) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = DVDD = +5.0V, DRVDD = +3.0V, AGND = DGND = DRGND = 0, INTCLK/EXTCLK = AGND, fCLK = 5MHz, input range = ±10V, REFP2 = REFP1, REFN2 = REFN1, COM1 = COM2, 1.0nF from REFADC to AGND, 1.0µF and 0.1µF from COM1 to AGND, 0.1µF from REFP1 to AGND, 0.1µF from REFN1 to AGND, 1.0µF from REFP1 to REFN1. Typical values are at TA = +25°C. TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ±1 ±3 LSB ±0.25 ±1 LSB ±4 ±16 LSB STATIC PERFORMANCE Resolution N 14 Integral Nonlinearity INL (Note 1) Differential Nonlinearity DNL No missing codes (Note 1) Offset Error (Note 1) Offset-Error Temperature Coefficient Bits ppm/°C 5 ±10 Offset-Error Matching LSB Gain Error Offset nulled (Notes 1, 2) ±0.1 ±0.35 Channel Gain-Error Matching Offset nulled ±20 LSB Gain-Error Temperature Coefficient Offset nulled 10 ppm/°C %FSR DYNAMIC PERFORMANCE (at fIN = 10kHz, AIN = -0.2dBFS) Sampling Rate Per Channel Signal-to-Noise Ratio Signal-to-Noise Plus Distortion Simultaneous on all channels SNR 150 (Note 1) 75 74 77 ksps dB SINAD (Note 1) Total Harmonic Distortion THD (Note 1) Spurious-Free Dynamic Range SFDR Range 0 (Note 1) 85 dBc (Note 1) 80 dB Range set bits = (0,0) -10 Channel-to-Channel Isolation 76 -83 dB -80 dBc ANALOG INPUTS (AIN_) Input Differential Voltage Range 2 +10 Range set bits = (0,1) -5 +5 Range set bits = (1,0) -2.5 +2.5 Range set bits = (1,1) -1.25 +1.25 _______________________________________________________________________________________ V 14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC (AVDD = DVDD = +5.0V, DRVDD = +3.0V, AGND = DGND = DRGND = 0, INTCLK/EXTCLK = AGND, fCLK = 5MHz, input range = ±10V, REFP2 = REFP1, REFN2 = REFN1, COM1 = COM2, 1.0nF from REFADC to AGND, 1.0µF and 0.1µF from COM1 to AGND, 0.1µF from REFP1 to AGND, 0.1µF from REFN1 to AGND, 1.0µF from REFP1 to REFN1. Typical values are at TA = +25°C. TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS Range set bits = (0,0) Input Common-Mode Range Input Resistance MIN TYP -5 MAX Range set bits = (0,1) -2.5 +2.5 Range set bits = (1,0) -1.25 +1.25 Range set bits = (1,1) -0.625 All settings Input Capacitance UNITS +5 V +0.625 6.25 kΩ 15 pF Small-Signal Bandwidth SSBW (Note 1) 1 MHz Full-Power Bandwidth FPBW (Note 1) 75 kHz INTERNAL REFERENCE (REFADC) Output Voltage 2.475 Differential Reference Voltage REFP– REFN 2.5 2.525 V 2.5 V Output-Voltage Temperature Coefficient 50 ppm/°C Load Regulation 5 V/mA EXTERNAL REFERENCE REFADC Voltage Input Range 2.0 REFADC Input Current REFADC Input Resistance (Note 3) 2.5 -250 RREF REFADC Input Capacitance 3.0 V +250 µA 5 kΩ 15 pF TRACK/HOLD (T/H) Aperture Delay tAD (Note 1) Aperture-Delay Matching Aperture Jitter tAJ (Note 1) 16 ns 100 ps 50 psRMS CLOCK-SELECT INPUT (INTCLK/EXTCLK) Input-Voltage High VIH Input-Voltage Low VIL 0.7 x AVDD V 0.3 x AVDD V DIGITAL INTERFACE AND CONTROL INPUTS (CS, RD, WR, CONVST, SHDN, CLK, STANDBY) Input-Voltage High VIH Input-Voltage Low VIL Input Hysteresis Input Capacitance CIN 0.7 x DRVDD V 0.3 x DRVDD V 50 mV 15 pF _______________________________________________________________________________________ 3 MAX1338 ELECTRICAL CHARACTERISTICS (continued) MAX1338 14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = +5.0V, DRVDD = +3.0V, AGND = DGND = DRGND = 0, INTCLK/EXTCLK = AGND, fCLK = 5MHz, input range = ±10V, REFP2 = REFP1, REFN2 = REFN1, COM1 = COM2, 1.0nF from REFADC to AGND, 1.0µF and 0.1µF from COM1 to AGND, 0.1µF from REFP1 to AGND, 0.1µF from REFN1 to AGND, 1.0µF from REFP1 to REFN1. Typical values are at TA = +25°C. TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Input Current SYMBOL IIN CONDITIONS MIN TYP VIN = 0 or DRVDD MAX UNITS ±1 µA DIGITAL INTERFACE AND CONTROL OUTPUTS (EOC, EOLC) Output-Voltage High VOH Sourcing 0.8mA Output-Voltage Low VOL Sinking 1.6mA Output-Voltage High VOH Sourcing 0.8mA Output-Voltage Low VOL Sinking 1.6mA DRVDD - 0.6 V 0.4 V PARALLEL DIGITAL I/O (D0–D7) DRVDD 0.6 V 0.4 Leakage Current 1 RD = 1 or CS = 1 Tristate Output Capacitance Input-Voltage High VIH Input-Voltage Low VIL 15 V 0.3 x DRVDD 50 Input Capacitance CIN Input Current IIN µA pF 0.7 x DRVDD Input Hysteresis V mV 15 VIN = 0 or DRVDD V pF ±1 µA PARALLEL DIGITAL OUTPUTS (D8–D13) Output-Voltage High VOH Sourcing 0.8mA Output-Voltage Low VOL Sinking 1.6mA DRVDD 0.6 V Leakage Current Tristate Output Capacitance 0.4 V 1 µA 15 pF POWER SUPPLIES Analog Supply Voltage Digital Supply Voltage Parallel Digital I/O Supply Voltage Analog Supply Current AVDD 4.75 5 5.25 V DVDD 4.75 5 5.25 V DRVDD 2.70 5.25 V AIDD SHDN = 1 STANDBY = 1, SHDN = 0 41 60 0.005 0.1 4.2 5 mA 3 Digital Supply Current Digital Driver Supply Current Analog Power-Supply Rejection 4 DIDD DRIDD SHDN = 1 0.001 0.05 STANDBY = 1, SHDN = 0 0.001 0.05 0 3 0.05 STANDBY = 1, SHDN = 0 0 0.05 4.75V to 5.25V (Note 1) 75 SHDN = 1 _______________________________________________________________________________________ mA mA dB 14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC (AVDD = DVDD = +5.0V, DRVDD = +3.0V, AGND = DGND = DRGND = 0, INTCLK/EXTCLK = AGND, fCLK = 5MHz, input range = ±10V, REFP2 = REFP1, REFN2 = REFN1, COM1 = COM2, 1.0nF from REFADC to AGND, 1.0µF and 0.1µF from COM1 to AGND, 0.1µF from REFP1 to AGND, 0.1µF from REFN1 to AGND, 1.0µF from REFP1 to REFN1. Typical values are at TA = +25°C. TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX 2.9 3.2 3.5 UNITS TIMING CHARACTERISTICS (Figures 4, 5, and 6) Internal clock Time to First Conversion Result tEOC1 Time to Subsequent Conversions tNEXT CONVST Pulse-Width Low CS Pulse Width tCONVST µs CLK Cycles External clock 16 Internal clock 600 ns 3 CLK Cycles External clock Internal clock 0.2 External clock 0.1 µs tCS 30 ns RD Pulse-Width Low tRDL 30 ns RD Pulse-Width High tRDH 30 ns WR Pulse-Width Low tWRL 30 ns CS to WR Setup Time tCTW 0 ns WR to CS Hold Time tWTC 0 ns CS to RD Setup Time tCTR 0 ns RD to CS Hold Time tRTC 0 ns Data Access Time (RD Low to Valid Data) tACC Figure 1 Bus Relinquish Time (RD High to D_ High-Z) tREQ Figure 1 5 30 ns 30 ns CLK Rise to End-of-Conversion (EOC) Rise/Fall Delay tEOCD 20 ns CLK Rise to End-of-LastConversion (EOLC) Fall Delay tEOLCD 20 ns CONVST Rise to EOLC Fall Delay tCVEOLCD Internal clock EOC Pulse-Width Low tEOC External clock Wake-Up Time From Standby Wake-Up Time From Shutdown All bypass capacitors discharged 180 20 ns 200 ns 1 CLK Cycle 7 µs 5 ns _______________________________________________________________________________________ 5 MAX1338 ELECTRICAL CHARACTERISTICS (continued) MAX1338 14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = +5.0V, DRVDD = +3.0V, AGND = DGND = DRGND = 0, INTCLK/EXTCLK = AGND, fCLK = 5MHz, input range = ±10V, REFP2 = REFP1, REFN2 = REFN1, COM1 = COM2, 1.0nF from REFADC to AGND, 1.0µF and 0.1µF from COM1 to AGND, 0.1µF from REFP1 to AGND, 0.1µF from REFN1 to AGND, 1.0µF from REFP1 to REFN1. Typical values are at TA = +25°C. TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL EOC Fall to RD Fall Setup Time tEOCRD EOLC Fall to RD Fall Setup Time CONDITIONS MIN TYP MAX UNITS 0 ns tEOLCRD 0 ns Input Data Setup Time tDTW 10 ns Input Data Hold Time tWTD 10 ns External CLK Period tCLK 166 200 ns External CLK High Period tCLKH Logic sensitive to rising edges 60 ns External CLK Low Period tCLKL Logic sensitive to rising edges 60 ns External Clock Frequency fCLK (Note 4) Internal Clock Frequency fINT 5.0 CONVST High to CLK Edge tCNTC 30 ns Quiet Time tQUIET 600 ns Note 1: Note 2: Note 3: Note 4: 1 5.25 MHz MHz See definition for this parameter in the Definitions section. Differential reference voltage (REFP–REFN) error nulled. This is the load the MAX1338 presents to an external reference at REFADC. Minimum CLK frequency is limited only by the internal T/H droop rate. Limit the time between the rising edge of CONVST to the falling edge of EOLC to a maximum of 0.25ms. 1.6mA 1.6V TO OUTPUT PIN 50pF 0.8mA Figure 1. Load Circuit for Data Access Time and BusRelinquish Time 6 6 5.5 _______________________________________________________________________________________ 14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC (AVDD = DVDD = +5.0V, DRVDD = +3.0V, AGND = DGND = DRGND = 0, INTCLK/EXTCLK = AGND, fCLK = 5MHz, input range = ±10V, REFP2 = REFP1, REFN2 = REFN1, COM1 = COM2, 1.0nF from REFADC to AGND, 1.0µF and 0.1µF from COM1 to AGND, 0.1µF from REFP1 to AGND, 0.1µF from REFN1 to AGND, 1.0µF from REFP1 to REFN1.) INTEGRAL NONLINEARITY vs. OUTPUT CODE OFFSET ERROR vs. SUPPLY VOLTAGE DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE 0.4 -1 0 -0.2 CHANNEL 0 OFFSET ERROR (LSB) 0.2 DNL (LSB) INL (LSB) 0.4 0.2 MAX1338 toc03 0.6 0 MAX1338 toc02 0.6 MAX1338 toc01 0.8 0 -0.2 -2 CHANNEL 2 -3 CHANNEL 1 -4 -0.4 -4096 0 4096 -6 -0.6 -8192 8192 -4096 OUTPUT CODE (DECIMAL) 4096 4.75 8192 4.85 4.95 GAIN ERROR vs. SUPPLY VOLTAGE 0 -5 CH1 -0.16 CH2 -0.17 0.10 GAIN ERROR (%FS) 5 -0.15 5.25 0.15 MAX1338 toc05 -0.14 GAIN ERROR (%FS) 10 5.15 GAIN ERROR vs. TEMPERATURE -0.13 MAX1338 toc04 15 5.05 AVDD (V) OUTPUT CODE (DECIMAL) OFFSET ERROR vs. TEMPERATURE CH3 -0.18 0.05 0 -0.05 -0.19 -10 -0.10 CH0 -0.20 REFERENCE ERROR NULLED -0.21 -15 -15 10 35 60 -0.15 4.75 85 4.85 4.95 5.05 5.25 5.15 -15 60 85 0.1 4584.25 MAX1338 toc08 OFFSET NORMALIZED 0 ATTENUATION (dB) -0.1 4000 3000 1802.75 35 ANALOG INPUT BANDWIDTH 6000 5000 10 TEMPERATURE (°C) OUTPUT HISTOGRAM (DC INPUT) 2000 -40 SUPPLY VOLTAGE (V) TEMPERATURE (°C) MAX1338 toc07 -40 COUNTS OFFSET (LSB) 0 MAX1338 toc06 -0.8 -8192 CHANNEL 3 -5 -0.4 -0.6 1646.25 -0.2 -0.3 -0.4 -0.5 -0.6 1000 97.25 61 0 -0.7 -0.8 -2 -1 0 1 DIGITAL OUTPUT CODE 2 0 50 100 150 200 fIN (kHz) _______________________________________________________________________________________ 7 MAX1338 Typical Operating Characteristics Typical Operating Characteristics (continued) (AVDD = DVDD = +5.0V, DRVDD = +3.0V, AGND = DGND = DRGND = 0, INTCLK/EXTCLK = AGND, fCLK = 5MHz, input range = ±10V, REFP2 = REFP1, REFN2 = REFN1, COM1 = COM2, 1.0nF from REFADC to AGND, 1.0µF and 0.1µF from COM1 to AGND, 0.1µF from REFP1 to AGND, 0.1µF from REFN1 to AGND, 1.0µF from REFP1 to REFN1.) SIGNAL-TO-NOISE RATIO vs. CLOCK FREQUENCY 78 -75 -100 78 77 77 76 76 75 74 0 15 30 45 60 74 73 72 72 71 71 70 1 75 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 FREQUENCY (kHz) fCLK (MHz) fCLK (MHz) TOTAL HARMONIC DISTORTION vs. CLOCK FREQUENCY SPURIOUS-FREE DYNAMIC RANGE vs. CLOCK FREQUENCY SIGNAL-TO-NOISE RATIO vs. REFERENCE VOLTAGE -94 105 -96 80 79 78 -102 SNR (dB) SFDR (dB) -100 95 90 -104 -106 10 77 100 -98 9 MAX1338 toc15 -92 MAX1338 toc14 110 MAX1338 toc13 -90 76 75 74 73 72 85 -108 71 -110 70 80 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 2.2 2.4 2.6 2.8 fCLK (MHz) fCLK (MHz) VREFADC (V) SIGNAL-TO-NOISE PLUS DISTORTION vs. REFERENCE VOLTAGE TOTAL HARMONIC DISTORTION vs. REFERENCE VOLTAGE SPURIOUS-FREE DYNAMIC RANGE vs. REFERENCE VOLTAGE 78 -87 -89 -91 76 -93 THD (dB) 77 75 74 -97 -99 72 -101 71 -103 70 2.4 2.6 VREFADC (V) 2.8 3.0 95 90 85 80 -105 2.2 105 100 -95 73 110 SFDR (dB) 79 3.0 MAX1338 toc18 -85 MAX1338 toc16 80 2.0 2.0 10 MAX1338 toc17 1 8 75 73 70 -125 THD (dB) 79 SNR (dB) -50 80 MAX1338 toc11 79 SNR (dB) -25 AMPLITUDE (dB) 80 MAX1338 toc10 0 SIGNAL-TO-NOISE PLUS DISTORTION vs. CLOCK FREQUENCY MAX1338 toc12 FFT AT fSAMPLE = 150ksps, fIN = 10kHz SINAD (dB) MAX1338 14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC 2.0 2.2 2.4 2.6 VREFADC (V) 2.8 3.0 2.0 2.2 2.4 2.6 VREFADC (V) _______________________________________________________________________________________ 2.8 3.0 14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC (AVDD = DVDD = +5.0V, DRVDD = +3.0V, AGND = DGND = DRGND = 0, INTCLK/EXTCLK = AGND, fCLK = 5MHz, input range = ±10V, REFP2 = REFP1, REFN2 = REFN1, COM1 = COM2, 1.0nF from REFADC to AGND, 1.0µF and 0.1µF from COM1 to AGND, 0.1µF from REFP1 to AGND, 0.1µF from REFN1 to AGND, 1.0µF from REFP1 to REFN1.) SUPPLY CURRENT vs. SUPPLY VOLTAGE DRIVER SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. TEMPERATURE EXCLUDES DRIVER CURRENT 4.0 45 3.5 43.6 43.4 43.2 43.0 44 DR|DD (mA) A|DD + D|DD (mA) 3.0 43 2.5 2.0 1.5 42 42.8 1.0 41 42.6 42.4 0.5 40 4.95 5.05 5.15 5.25 0 -40 AVDD (V) -15 10 35 60 2.75 85 3.25 TEMPERATURE (°C) 5.25 2.4987 MAX1338 toc23 0.97 4.75 REFERENCE VOLTAGE vs. SUPPLY VOLTAGE MAX1338 toc22 DRVDD = 3V 4.25 DRVDD (V) DRIVER SUPPLY CURRENT vs. TEMPERATURE 0.98 3.75 2.4986 2.4985 0.96 2.4984 VREFADC (V) 0.95 0.94 0.93 2.4983 2.4982 2.4981 0.92 2.4980 0.91 2.4979 0.90 2.4978 -40 -15 10 35 60 4.75 85 4.85 4.95 5.05 5.15 TEMPERATURE (°C) AVDD (V) REFERENCE VOLTAGE vs. TEMPERATURE SHUTDOWN CURRENT vs. SUPPLY VOLTAGE 70 MAX1338 toc24 2.504 2.502 SHDN = AVDD 65 2.500 5.25 MAX1338 toc25 4.85 DR|DD (mA) 60 A|DD (µA) 4.75 VREFADC (V) A|DD + D|DD (mA) MAX1338 toc21 EXCLUDES DRIVER CURRENT 43.8 MAX1338 toc20 46 MAX1338 toc19 44.0 2.498 2.496 55 50 2.494 45 2.492 40 2.490 -40 -15 10 35 TEMPERATURE (°C) 60 85 4.75 4.85 4.95 5.05 5.15 5.25 AVDD (V) _______________________________________________________________________________________ 9 MAX1338 Typical Operating Characteristics (continued) Typical Operating Characteristics (continued) (AVDD = DVDD = +5.0V, DRVDD = +3.0V, AGND = DGND = DRGND = 0, INTCLK/EXTCLK = AGND, fCLK = 5MHz, input range = ±10V, REFP2 = REFP1, REFN2 = REFN1, COM1 = COM2, 1.0nF from REFADC to AGND, 1.0µF and 0.1µF from COM1 to AGND, 0.1µF from REFP1 to AGND, 0.1µF from REFN1 to AGND, 1.0µF from REFP1 to REFN1.) SHUTDOWN CURRENT vs. TEMPERATURE STANDBY CURRENT vs. SUPPLY VOLTAGE SHDN = AVDD 65 STANDBY = AVDD 4.25 4.20 A|DD (mA) 55 4.15 50 4.10 45 4.05 40 4.00 -15 10 35 60 85 4.75 4.85 4.95 5.05 5.15 TEMPERATURE (°C) AVDD (V) STANDBY CURRENT vs. TEMPERATURE CONVERSION TIME vs. SUPPLY VOLTAGE 5.8 MAX1338 toc28 4.30 STANDBY = AVDD INTERNAL CLOCK 5.6 CONVERSION TIME (µs) 4.25 4.20 4.15 4.10 5.25 MAX1338 toc29 -40 5.4 5.2 5.0 4.05 4.00 4.8 -40 -15 10 35 60 85 4.75 4.85 4.95 5.05 5.15 TEMPERATURE (°C) AVDD (V) CONVERSION TIME vs. TEMPERATURE ANALOG INPUT CURRENT vs. ANALOG INPUT VOLTAGE 4 MAX1338 toc30 5.8 INTERNAL CLOCK 3 INPUT CURRENT (mA) 5.6 5.4 5.2 5.25 MAX1338 toc31 A|DD (µA) 60 A|DD (mA) MAX1338 toc27 4.30 MAX1338 toc26 70 CONVERSION TIME (µs) MAX1338 14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC 2 1 0 -1 -2 5.0 -3 -4 4.8 -40 -15 10 35 TEMPERATURE (°C) 10 60 85 -17.0 -8.5 0 8.5 INPUT VOLTAGE (V) ______________________________________________________________________________________ 17.0 14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC PIN NAME FUNCTION 1, 7, 9, 17, 19 AVDD Analog Power Input. AVDD is the power input for the analog section of the converter. Connect a +4.75V to +5.25V power supply to AVDD. Bypass each AVDD to AGND with a 0.1µF capacitor very close to the device. Bypass AVDD to AGND with a bulk capacitor of at least 4.7µF where power enters the board. Connect all AVDD pins to the same potential. 2 AIN0+ Channel 0 Differential Analog Input 3 AIN0- Channel 0 Differential Analog Input 4 AIN1+ Channel 1 Differential Analog Input 5 AIN1- Channel 1 Differential Analog Input 6, 8, 14, 16, 18, 20, 28 AGND Analog Ground. AGND is the power return for AVDD. Connect all AGNDs to the same potential. 10 AIN2+ Channel 2 Differential Analog Input 11 AIN2- Channel 2 Differential Analog Input 12 AIN3+ Channel 3 Differential Analog Input 13 AIN3- Channel 3 Differential Analog Input 15 INTCLK/ EXTCLK Clock-Select Input. Force INTCLK/EXTCLK high for internal clock mode. Force INTCLK/EXTCLK low for external clock mode. 21 REFADC ADC Reference Bypass or Input. REFADC is the bypass point for an internally generated reference voltage. Bypass REFADC with a 1.0nF capacitor to AGND. REFADC can be driven externally by a precision external voltage reference. See the Reference section and the Typical Operating Circuit. 22 REFP1 Positive Differential Reference Bypass Point 1. Connect REFP1 to REFP2. 23 REFP2 Positive Differential Reference Bypass Point 2. Connect REFP2 to REFP1. Bypass REFP2 with a 0.1µF capacitor to AGND. Also bypass REFP2 to REFN2 with a 0.1µF capacitor. 24 COM1 Common-Mode Voltage Bypass Point 1. Connect COM1 to COM2. 25 COM2 Common-Mode Voltage Bypass Point 2. Connect COM2 to COM1. Connect a 1.0µF capacitor from COM2 to AGND. 26 REFN1 Negative Differential Reference Bypass Point 1. Connect REFN1 to REFN2. 27 REFN2 Negative Differential Reference Bypass Point 2. Connect REFN2 to REFN1. Bypass REFN2 with a 0.1µF capacitor to AGND. Also bypass REFN2 to REFP2 with a 0.1µF capacitor. 29 D0 Data Input/Output Bit 0 (LSB) 30 D1 Data Input/Output Bit 1 31 D2 Data Input/Output Bit 2 32 D3 Data Input/Output Bit 3 33 D4 Data Input/Output Bit 4 34 D5 Data Input/Output Bit 5 35 D6 Data Input/Output Bit 6 36 D7 Data Input/Output Bit 7 37 D8 Data Output Bit 8 38 D9 Data Output Bit 9 39 D10 Data Output Bit 10 40 D11 Data Output Bit 11 ______________________________________________________________________________________ 11 MAX1338 Pin Description 14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC MAX1338 Pin Description (continued) PIN NAME FUNCTION 41 D12 Data Output Bit 12 42 D13 Data Output Bit 13 (MSB) 43 DRVDD Digital I/O Power-Supply Input. DRVDD is the power input for the digital I/O buffers and drivers. Connect a +2.7V to +5.25V power supply to DRVDD. Bypass DRVDD to DRGND with a 0.1µF capacitor very close to the device. 44 DRGND Driver Ground. DRGND is the power-supply return for DRVDD. 45 EOC End-of-Conversion Output. EOC goes low to indicate the end of a conversion. EOC returns high after one clock period. 46 EOLC End-of-Last-Conversion Output. EOLC goes low to indicate the end of the last conversion. EOLC returns high when CONVST goes low for the next conversion sequence. 47 RD Read Input. Forcing RD low initiates a read command of the parallel data bus, D0–D13. D0–D13 are high impedance while either RD or CS is high. 48 WR Write Input. Forcing WR low initiates a write command for configuring the device through D0–D7. 49 CS Chip-Select Input. Forcing CS low activates the digital interface. D0–D13 are high impedance while either CS or RD is high. 50 CONVST Convert Start Input. CONVST initiates the conversion process. The analog inputs are sampled on the rising edge of CONVST. 51 CLK External-Clock Input. CLK accepts a 1MHz to 6MHz external clock signal. For externally clocked conversions, apply the clock signal to CLK and force INTCLK/EXTCLK low. For internally clocked conversions, connect CLK to DGND and force INTCLK/EXTCLK high. 52 STANDBY Standby-Control Input. Forcing STANDBY high partially powers down the device but leaves all the reference-related circuitry alive. Use STANDBY instead of SHDN when quick wake-up is required. 53 SHDN Shutdown-Control Input. Force SHDN high to place the device into full shutdown. When in full shutdown, all circuitry within the device is powered down and all reference capacitors are allowed to discharge. Allow 1ms for wake-up from full shutdown before starting a conversion. 54 DVDD Digital Power-Supply Input. DVDD is the power input for the digital circuitry. Connect a +4.75V to +5.25V power supply to DVDD. Bypass DVDD to DGND with a 0.1µF capacitor very close to the device. 55, 56 DGND — EP Digital Ground. Power return for DVDD. Exposed Pad. Connect to AGND. Detailed Description The MAX1338 simultaneously samples four differential analog inputs with internal T/H circuits, and sequentially converts them to a digital code with a 14-bit ADC. Output data is provided by a 14-bit parallel interface. At power-up, all channels default to a ±10V input range. Program different input ranges (±10V, ±5V, ±2.5V, or ±1.25V) using the configuration register. Different input ranges between ±12V and ±1.0V are realized using an 12 external reference. All channels offer input protection to ±17V, independent of the selected input range. The internal clock operates the ADC at 5MHz, or uses an external conversion clock from 1MHz to 6MHz. EOC goes low when the result of each conversion is available, and EOLC goes low when the last conversion result is available. Standby and shutdown modes, selectable through logic-control inputs, save power between conversions. Figure 2 shows a block diagram of the MAX1338. ______________________________________________________________________________________ 14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC MAX1338 DVDD DRVDD AVDD AIN0+ MAX1338 D13 S/H AIN0- 4x1 MUX AIN3+ 14-BIT ADC S/H 4 x 14 SRAM OUTPUT DRIVERS D8 D7 AIN3D0 REFP2 REFP1 COM2 COM1 CONFIGURATION REGISTER REFN2 REFN1 INTERFACE AND CONTROL WR CS RD CONVST SHDN CLK 5kΩ REFADC STANDBY 2.500V EOC EOLC INTCLK/EXTCLK AGND DRGND DGND Figure 2. Functional Diagram Power-Supply Inputs Three separate power supplies power the MAX1338. A +5V analog supply, AVDD, powers the analog input and converter sections. A +5V digital supply, DVDD, powers the internal logic circuitry, and a +2.7V to +5V digital supply (DRVDD), powers the parallel I/O and the control I/O (see the Typical Operating Circuit). Bypass the power supplies as indicated in the Layout, Grounding, and Bypassing section. Power-supply sequencing is not required for the MAX1338. Analog Inputs Software-Selectable Input Range The MAX1338 provides four independent, softwareselectable, analog input voltage ranges for each channel. The selectable input ranges are ±VREF x 4 (the power-up default condition), ±VREF x 2, ±VREF, and ±V REF x 0.5. Using the 2.5V internal reference, the selectable input ranges are ±10V (power-up default), ±5V, ±2.5V, and ±1.25V. Program the analog input ranges with the configuration register through the parallel I/O. See the Configuration Register section for programming details. Input Protection Protection at the analog inputs provides ±17V fault immunity for the MAX1338. This protection circuit limits the current at the analog inputs to less than ±2mA. Input fault protection is active in standby, in shutdown, during normal operation, and over all input ranges. Track and Hold (T/H) To preserve relative phase information between input channels, each input channel has a dedicated T/H amplifier. The rising edge of CONVST represents the sampling instant for all channels. All samples are taken within an aperture delay (tAD) of 16ns. The aperture delay of all channels is matched to within 100ps. ______________________________________________________________________________________ 13 MAX1338 14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC Figure 3 shows the equivalent analog input T/H circuit for one analog input. As conversion begins, the T/H circuits hold the analog signals. After the 12th clock cycle (or 2.4µs in internal clock mode) into the conversion process, the last analog input sample begins shifting through the converter, and the T/H circuits begin to track the analog inputs again in preparation for the next CONVST rising edge. Due to the resistive load presented by the analog inputs, any significant analog input source resistance, RSOURCE, increases gain error. Limit R SOURCE to a maximum of 20Ω to limit the effect to less than 0.1%. Drive the input with a wideband buffer (>1MHz) that can drive the ADC’s input impedance. Selecting an Input Buffer Most applications require an input buffer to achieve 14bit accuracy. Although slew rate and bandwidth are important, the most critical specification is output impedance. Use a low-noise, low-distortion amplifier with low output impedance, for best gain-accuracy performance. Input Bandwidth The input-tracking circuitry has a 1MHz small-signal bandwidth. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. R1 || R2 = 6.25kΩ R1 CHOLD AIN_ R2 1.9V Figure 3. Simplified Typical Input Circuit CONVST CONFIGURATION REGISTER ACTIVATES RD tCS CS Data Throughput The data throughput (fTH) of the MAX1338 is a function of the clock speed (fCLK). The MAX1338 operates from a 5MHz internal clock or an external clock between 1MHz and 6MHz. For fastest throughput, read the conversion result during conversion (Figure 5), and calculate data throughput using: tCTW tWRL tWTC WR tDTW D0–D7 fTH = MAX1338 DATA IN 1 t QUIET + tWTD 26 fCLK Figure 4. Write Timing where tQUIET is the period of bus inactivity before the rising edge of CONVST. Clock Modes The MAX1338 provides an internal clock of 5MHz. Alternatively, use an external clock of 1MHz to 6MHz. 14 Internal Clock Internal clock mode frees the microprocessor from the burden of running the ADC conversion clock. For internal-clock operation, connect INTCLK/EXTCLK to AVDD and CLK to DRGND. Note that INTCLK/EXTCLK is referenced to the analog power supply, AVDD. Total conversion time for all four channels using the internal clock is 6µs (typ). ______________________________________________________________________________________ 14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC Applications Sections Power-On Reset At power-up, all channels default to a ±10V input range. After applying power, allow a 1ms wake-up time to elapse and perform one dummy conversion before initiating first conversion. Power Saving Full Shutdown During shutdown, the analog and digital circuits in the MAX1338 power down and the device draws less than 0.06mA from AVDD, and less than 10µA from DVDD. Select shutdown mode using the SHDN input. Force SHDN high to enter shutdown mode. When coming out of shutdown, allow the 1ms wake-up and then perform one dummy conversion before making the first conversion. Standby Standby is similar to shutdown but the reference circuits remain powered up, allowing faster wake-up. Enter standby by forcing STANDBY high. After coming out of standby, perform a dummy conversion before making the first conversion. Digital Interface The digital interface consists of two sections: a control I/O section and a parallel I/O section. The control I/O section includes the following control signals: chip select (CS), read (RD), write (WR), end of conversion (EOC), end of last conversion (EOLC), convert start (CONVST), power-down (SHDN), standby (STANDBY), and external-clock input (CLK). The bidirectional parallel I/O section sets the 8-bit input range configuration register using D0–D7 (see the Configuration Register section) and outputs the 14-bit conversion result using D0–D13. The I/O operations are controlled by the control I/O signals RD, WR, and CS. All parallel I/O bits are high impedance when either RD = 1 or CS = 1. Figures 4, 5, and 6 and the Timing Characteristics section detail the operation of the digital interface. Table 1. Configuration Register I/O LINE REGISTER NAME FUNCTION D0 CH0R0 Channel 0 input range setting bit 0 D1 CH0R1 Channel 0 input range setting bit 1 D2 CH1R0 Channel 1 input range setting bit 0 D3 CH1R1 Channel 1 input range setting bit 1 D4 CH2R0 Channel 2 input range setting bit 0 D5 CH2R1 Channel 2 input range setting bit 1 D6 CH3R0 Channel 3 input range setting bit 0 D7 CH3R1 Channel 3 input range setting bit 1 Table 2. Input-Range Register Settings REGISTER SETTING SELECTED INPUT RANGE ALLOWABLE COMMON-MODE RANGE CH_R0 CH_R1 0 0 -10V to +10V ±5V 0 1 -5V to +5V ±2.5V 1 0 -2.5V to +2.5V ±1.25V 1 1 -1.25V to +1.25V ±0.625V Configuration Register The MAX1338 uses an 8-bit configuration word to set the input range for each channel. Table 1 and Table 2 describe the configuration word and the input-range settings. Write to the configuration register by forcing CS and WR low, loading bits D0–D7 onto the parallel bus, and then forcing WR high. The configuration bits are latched on the rising edge of WR (Figure 4). It is possible to write to the configuration register at any point during the conversion sequence. However, it will not be active until the next convert-start signal. At power-up, the configuration register contains all zeros, making all channels default to the maximum input range, -10V to +10V. Shutdown and standby do not change the configuration register, but the configuration register can be programmed while the MAX1338 is in shutdown or standby modes. ______________________________________________________________________________________ 15 MAX1338 External Clock For external clock operation, force INTCLK/EXTCLK low and connect an external clock source to CLK. Use an external clock frequency from 1MHz to 6MHz with a duty cycle between 40% and 60%. Choose a minimum clock frequency of 1MHz to prevent linearity errors caused by excessive droop in the T/H circuits. MAX1338 14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC SAMPLE tCONVST CONVST 17 CLK 18 tEOC1 19 20 21 22 24 23 25 26 29 27 tNEXT EOC tEOC EOLC tQUIET RD tACC tRDL D0–D13 CH0 CH1 CH2 CH3 tREQ Figure 5. Reading During a Conversion—Internal or External Clock Starting a Conversion Reading a Conversion Result Internal Clock For internal clock operation, force INTCLK/EXTCLK high. To start a conversion using internal clock mode, pull CONVST low for at least tCONVST. The T/H acquires the signal while CONVST is low. An EOC signal pulses low when the first result becomes available, and for each subsequent result until the end of the conversion cycle. The EOLC signal goes low when the last conversion result becomes available (Figure 6). Reading During a Conversion Figure 5 shows the interface signals to initiate a read operation during a conversion cycle. CS can be held low permanently, low during the RD cycles, or it can be the same as RD. After initiating a conversion by bringing CONVST high, wait for EOC to go low (about 3.4µs in internal clock mode) or 17 clock cycles (external clock mode) before reading the first conversion result. Read the conversion result by bringing RD low, which latches the data to the parallel digital output bus. Bring RD high to release the digital bus. Wait for the next falling edge of EOC (about 600ns in internal clock mode or three clock cycles in external clock mode) before reading the next result. When the last result is available, EOLC goes low, along with EOC. Wait three clock cycles, tQUIET, before starting the next conversion cycle. External Clock For external clock operation, force INTCLK/EXTCLK low. To start a conversion using external clock mode, pull CONVST low for at least tCONVST. The T/H circuits track the input signal while CONVST is low. Conversion begins on the rising edge of CONVST. Apply an external clock to CLK. To avoid T/H droop degrading the sampled analog input signals, the first CLK pulse must occur within 10µs after the rising edge of CONVST and have a minimum 1MHz clock frequency. The first conversion result is available for read on the rising edge of the 17th clock cycle, and subsequent conversions on every 3rd clock cycle thereafter, as indicated by EOC and EOLC. 16 Reading After a Conversion Figure 6 shows the interface signals for a read operation after a conversion using an external clock. At the falling of EOLC, on the 26th clock pulse after the initiation of a conversion, driving CS and RD low places the first conversion result onto the parallel I/O bus. Read the conversion result on the rising edge of RD. Successive low pulses of RD place the successive conversion results ______________________________________________________________________________________ 14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC MAX1338 SAMPLE tCONVST CONVST tCLKH tCNTC 27 26 2 1 28 31 30 29 CLK tCLK EOC tCLKL ONLY LAST PULSE SHOWN tEOC EOLC tRTC CS tCTR tQUIET tRDH tRDL RD tEOCRD tEOLCRD D0–D13 CH0 tACC CH1 CH2 CH3 tREQ Figure 6. Reading After a Conversion—External Clock onto the bus. After reading all four channels, bring CS high to release the parallel I/O. After waiting tQUIET, pulse CONVST low to initiate the next conversion. Table 3. Reference Bypass Capacitors BYPASS CAPACITORS LOCATION Reference Bypass the reference inputs as indicated in Table 3. Internal Reference The internal reference supports all input ranges for the MAX1338. External Reference Implement external-reference operation by overdriving the internal reference voltage. Override the internal reference voltage by connecting a 2.0V to 3.0V external reference at REF. The REF input impedance is typically 5kΩ. For more information about using an external reference, see the Transfer Functions section. REFADC bypass capacitor to AGND REFP1 bypass capacitor to AGND 1nF 0.1µF REFN1 bypass capacitor to AGND 0.1µF REFP1 to REFN1 capacitor 1.0µF COM1 bypass capacitor to AGND 1.0µF || 0.1µF Transfer Functions Digital Correction Factory trim procedures digitally shift the transfer function to reduce bipolar zero-code offset to less than ±4 LSBs (typ). Depending on initial conditions, the transfer function is shifted up or down, as required. The maximum shift that any transfer function experiences is 64 codes, which can have a small effect at the extremes of the transfer function, as shown in Figure 7. ______________________________________________________________________________________ 17 8 x VREFADC INITIAL TRANSFER FUNCTION ADJUSTED TRANSFER FUNCTION 0x0000 MAXIMUM 64 CODES 0x2000 -8192 +8191 0 Figure 7. Example of Digitally Adjusted Transfer Function— Shifted Down to Minimize Zero-Code Offset Input Range Settings Table 4 shows the two’s complement output for a selection of inputs. The full-scale input range (FSR) depends on the selected range, and the voltage at REF, as shown in Table 5. Also shown in Table 5 are the allowable common-mode ranges for the differential inputs. Calculate the LSB size using: A × VREFADC 214 where A = gain multiplier for the selected input range, from Table 6. Determine the input voltage as a function of VREF, and the output code using: VAIN _ + − VAIN _ − = VREFADC × A × CODE 214 where A = gain multiplier for the selected input range, from Table 6. Figures 8, 9, 10, and 11 show the transfer functions for the four selectable input ranges. 18 0x1FFF 0x1FFE 0x1FFD 0x1FFC 0x0001 0x0000 0x3FFF 0x2003 0x2002 0x2001 0x2000 1 LSB = -8192 -8190 -1 0 +1 8 x VREF 214 +8189 +8191 INPUT VOLTAGE (VAIN_+ - VAIN_- IN LSBs) INPUT VOLTAGE (LSBs) 1 LSB = TWO'S COMPLEMENT BINARY OUTPUT CODE 0x1FFF OUTPUT CODE MAX1338 14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC Figure 8. ±10V Transfer Function Applications Information Layout, Grounding, and Bypassing For best performance, the board layout must follow some simple guidelines. Separate the control I/O and parallel I/O signals from the analog signals, and run the clock signals separate from everything. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the ADC package. Run the parallel I/O signals together as a bundle. The MAX1338 has an exposed underside pad for a low-inductance ground connection and low thermal resistance. Connect the exposed pad to the circuit board ground plane. Figure 12 shows the recommended system ground connections. Establish an analog ground point at AGND and a digital ground point at DGND. Connect all analog grounds to the analog ground point. Connect all digital grounds to the digital ground point. For lowest noise operation, make the power-supply ground returns as low impedance and as short as possible. Connect the analog ground point to the digital ground point at one location. High-frequency noise in the power supplies degrades the ADC’s performance. Bypass AVDD to AGND with a parallel combination of 0.1µF and 2.2µF capacitors, bypass DVDD to DGND with a parallel combination of 0.1µF and 2.2µF capacitors, and bypass DRVDD to DRGND with a parallel combination of 0.1µF and 2.2µF capacitors. If the supply is very noisy use a ferrite bead as a lowpass filter, as shown in Figure 12. ______________________________________________________________________________________ 14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC INPUT VOLTAGE (V) ±10V INPUT RANGE SELECTED ±5V INPUT RANGE SELECTED ±2.5V INPUT RANGE SELECTED ±1.25V INPUT RANGE SELECTED DECIMAL EQUIVALENT OUTPUT (CODE10) 9.9988 4.9994 2.4998 1.2499 8191 01 1111 1111 1111 → 0x1FFF 9.9976 4.9988 2.4997 1.2498 8190 01 1111 1111 1110 → 0x1FFE 0.0012 0.0006 0.0002 0.0001 1 00 0000 0000 0001 → 0x0001 TWO’S COMPLEMENT BINARY OUTPUT CODE 0 0 0 0 0 00 0000 0000 0000 → 0x0000 -0.0012 -0.0006 -0.0002 -0.0001 -1 11 1111 1111 1111 → 0x3FFF -9.9988 -4.9994 -2.4998 -1.2499 -8191 10 0000 0000 0001 → 0x2001 -10.0000 -5.0000 -2.5000 -1.2500 -8192 10 0000 0000 0000 → 0x2000 Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. For these devices, this straight line is a line drawn between the endpoints of the transfer function, once offset and gain errors have been nulled. Table 5. Input Ranges SELECTED INPUT RANGE (V) ±10 Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. For these devices, the DNL of each digital output code is measured and the worst-case value is reported in the Electrical Characteristics table. A DNL error specification of less than ±1 LSB guarantees no missing codes and a monotonic transfer function. Offset Error Offset error indicates how well the actual transfer function matches the ideal transfer function at a single point. Typically, the point at which the offset error is specified is at or near the zero scale of the transfer function or at or near the midscale of the transfer function. For the MAX1338, the ideal zero-scale digital output transition from 0x3FFF to 0x0000 occurs with an analog input voltage of zero. Offset error is the amount of analog input-voltage deviation between the measured input voltage and the calculated input voltage at the zeroscale transition. FULL-SCALE INPUT RANGE (V) ALLOWABLE COMMON-MODE RANGE (V) 2.0 ±8 ±5 2.5 ±10 ±5 VREFADC (V) ±5 ±2.5 ±1.25 3.0 ±12 ±5 2.0 ±4 ±2.5 2.5 ±5 ±2.5 3.0 ±6 ±2.5 2.0 ±2 ±1.25 2.5 ±2.5 ±1.25 3.0 ±3 ±1.25 2.0 ±1 ±0.625 2.5 ±1.25 ±0.625 3.0 ±1.5 ±0.625 Table 6. LSB Size with VREF = 2.500V SELECTED INPUT RANGE (V) GAIN MULTIPLIER (A) LSB SIZE (mV) ±10 8 1.2207 ±5 4 0.6104 ±2.5 2 0.1526 ±1.25 1 0.0736 ______________________________________________________________________________________ 19 MAX1338 Table 4. Code Table with VREF = 2.500V MAX1338 14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC 2 x VREFADC TWO'S COMPLEMENT BINARY OUTPUT CODE TWO'S COMPLEMENT BINARY OUTPUT CODE 4 x VREFADC 0x1FFF 0x1FFE 0x1FFD 0x1FFC 0x0001 0x0000 0x3FFF 0x2003 0x2002 0x2001 0x2000 4 x VREF 1 LSB = -1 -8192 -8190 0 +1 214 0x1FFF 0x1FFE 0x1FFD 0x1FFC 0x0001 0x0000 0x3FFF 0x2003 0x2002 0x2001 0x2000 +8189 +8191 1 LSB = -1 -8192 -8190 INPUT VOLTAGE (VAIN_+ - VAIN_- IN LSBs) 0 +1 2 x VREF 214 +8189 +8191 INPUT VOLTAGE (VAIN_+ - VAIN_- IN LSBs) Figure 9. ±5V Transfer Function Figure 10. ±2.5V Transfer Function TWO'S COMPLEMENT BINARY OUTPUT CODE VREFADC ANALOG POWER SUPPLY 0x1FFF 0x1FFE 0x1FFD 0x1FFC +5V DIGITAL POWER SUPPLIES +5V AGND GND +3V FERRITE BEAD 0x0001 0x0000 0x3FFF 0x2003 0x2002 0x2001 0x2000 1 LSB = VREF 2 -8192 -8190 -1 0 +1 AVDD AGND DVDD DGND DRVDD DRGND +5V GND 14 +8189 +8191 MAX1338 DIGITAL CIRCUITS INPUT VOLTAGE (VAIN_+ - VAIN_- IN LSBs) Figure 11. ±1.25V Transfer Function Figure 12. Power-Supply Grounding and Bypassing Gain Error Signal-to-Noise Ratio (SNR) Gain error indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. For the MAX1338, the gain error is the difference between the measured positive full-scale and negative full-scale transition points minus the difference between the ideal positive full-scale and negative fullscale bipolar transition points. SNR is a measure of the converter’s noise characteristics. For a waveform perfectly reconstructed from digital samples, SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization noise error only and results directly from the ADC’s resolution (N bits): 20 ______________________________________________________________________________________ 14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC Signal-to-Noise Plus Distortion (SINAD) SINAD indicates the converter’s noise and distortion performance. SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset. SIGNALRMS SINAD(dB) = 20 × log (NOISE + DISTORTION)RMS Effective Number of Bits (ENOB) ENOB specifies the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB for a fullscale sinusoidal input waveform is computed from: ENOB = SINAD − 1.76 6.02 Total Harmonic Distortion (THD) THD is a dynamic indication of how much harmonic distortion the converter adds to the signal. THD is the ratio of the RMS sum of the first five harmonics of the fundamental signal to the fundamental itself. This is expressed as: Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. SFDR is specified in decibels relative to the carrier (dBc). Aperture Delay Aperture delay (tAD) is the time delay from the sampling clock edge to the instant when an actual sample is taken. Aperture Jitter Aperture jitter (tAJ) is the sample-to-sample variation in aperture delay. Channel-to-Channel Isolation Channel-to-channel isolation indicates how well each analog input is isolated from the others. The channel-tochannel isolation for the MAX1338 is measured by applying a DC -0.5dBFS sine wave to the ON channel while a high frequency 10kHz -0.5dBFS sine wave is applied to all OFF channels. An FFT is taken for the ON channel. From the FFT data, channel-to-channel crosstalk is expressed in dB as the power ratio of the DC signal applied to the ON channel and the high-frequency crosstalk signal from the OFF channels. Power-Supply Rejection (PSRR) PSRR is defined as the shift in gain error when the analog power supply is changed from 4.75V to 5.25V. Small-Signal Bandwidth A -20dBFS sine wave is applied to the MAX1338 input. The frequency is increased until the amplitude of the digitized conversion result decreases 3dB. Full-Power Bandwidth A -0.5dBFS sine wave is applied to the MAX1338 input. The frequency is increased until the amplitude of the digitized conversion result decreases 3dB. 2 2 2 2 2 V2 + V3 + V4 + V5 + V6 THD = 20 × log V1 where V1 is the fundamental amplitude and V2–V6 are the amplitudes of the 2nd- through 6th-order harmonics. ______________________________________________________________________________________ 21 MAX1338 SNR = (6.02 x N + 1.76)dB where N = 14 bits. In reality, there are other noise sources such as thermal noise, reference noise, and clock jitter. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics, and the DC offset. 14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC MAX1338 Typical Operating Circuit 15 DVDD INTCLK/EXTCLK 54 +5V +5V 0.1µF 1 0.1µF 7 AVDD AVDD 0.1µF 9 AVDD 0.1µF 17 MAX1338 DGND SHDN CLK CONVST AVDD CS 0.1µF 19 0.1µF 21 0.001µF 22 0.1µF 23 AVDD REFADC REFP1 REFP2 WR RD EOLC EOC STANDBY 55, 56 GND 53 51 50 49 48 CONTROL I/O 47 46 45 52 1.0µF 27 0.1µF REFN2 24 25 0.1µF DRGND COM2 D13 D12 6, 8, 14, 16, 18, 20, 28 AGND 2 AIN0+ 3 4 5 ANALOG INPUTS 10 11 12 13 +3V TO +5V 44 GND COM1 0.1µF 22 43 26 REFN1 1.0µF GND DRVDD D11 D10 D9 AIN0- D8 AIN1+ D7 D6 AIN1AIN2+ AIN2- D5 D4 D3 D2 AIN3+ D1 AIN3- D0 42 41 40 39 DIGITAL OUTPUT 38 37 36 PARALLEL I/O 35 34 33 32 DIGITAL I/O 31 30 29 ______________________________________________________________________________________ 14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC CS RD EOLC EOC DRGND DRVDD 47 46 45 44 43 CONVST 50 WR CLK 51 48 STANDBY 52 49 DVDD SHDN 53 55 54 DGND DGND 56 TOP VIEW TRANSISTOR COUNT: 27,000 PROCESS: BiCMOS EXPOSED PAD: Connect to AGND AVDD 1 42 D13 AIN0+ 2 41 D12 AIN0- 3 40 D11 AIN1+ 4 39 D10 AIN1- 5 38 D9 AGND 6 37 D8 AVDD 7 36 D7 AGND 8 35 D6 MAX1338 23 24 25 26 27 28 COM1 COM2 REFN1 REFN2 AGND D0 REFP2 29 22 14 REFP1 D1 AGND 21 30 REFADC 13 20 D2 AIN3- 19 31 AVDD 12 AGND D3 AIN3+ 18 32 17 11 AVDD D4 AIN2- AGND D5 33 16 34 10 15 9 AGND AVDD AIN2+ INTCLK/EXTCLK Chip Information THIN QFN ______________________________________________________________________________________ 23 MAX1338 Pin Configuration Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 56L THIN QFN.EPS MAX1338 14-Bit, 4-Channel, Software-Programmable, Multiranging, Simultaneous-Sampling ADC Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.