TI SN74BCT2414

SN74BCT2414
MEMORY DECODER
WITH ON-CHIP SUPPLY VOLTAGE MONITOR
SCBS059B – MARCH 1989 – REVISED NOVEMBER 1993
•
•
•
•
•
•
•
DW OR N PACKAGE
(TOP VIEW)
BiCMOS Design Substantially Reduces
Standby Current
Two Independent 2-Line to 4-Line Decoders
or One 3-Line to 8-Line Decoder
Separate Enable Inputs for Easy Cascading
Two Supply Voltage Terminals (VCC and
Vbat )
Built-In Supply-Voltage Monitor for VCC
Automatic Cut Off of Outputs During
VCC Fail
Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic 300-mil DIPs (N)
VS
SD
1A
2A
1B
2B
1G
2G
G
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
Vbat
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
description
The SN74BCT2414 is a decoder specially designed to be used in memory systems with battery backup during
power failure. The two independent 2-line to 4-line decoders with separate and common control inputs may be
externally cascaded to implement a 3-line to 8-line decoder.
The circuit has two supply voltage inputs: the voltage monitor (bandgap) is powered via the VCC terminal; the
internal logic of the circuit is powered via the Vbat terminal. In case VCC drops below 3.65 V (nominal), the voltage
monitor forces the voltage-control (VS) and decoder outputs (Y) to the high level. VS may be used to disconnect
the supply voltage of the memories (Vbat) from the system supply. This output is switched off when the on-chip
supply voltage monitor detects a power failure.
The SN74BCT2414 is characterized for operation from 0°C to 70°C.
Copyright  1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–1
SN74BCT2414
MEMORY DECODER
WITH ON-CHIP SUPPLY VOLTAGE MONITOR
SCBS059B – MARCH 1989 – REVISED NOVEMBER 1993
logic symbol†
VCC
SD
G
VCOMP
20
2
EN
X/Y
1A
1B
1G
5
7
0
1
1
2
2
EN
3
2A
2B
2G
4
6
8
X/Y
0
1
1
2
2
EN
3
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2–2
VS
&
9
3
1
X > 3.65 V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
18
17
16
15
14
13
12
11
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
SN74BCT2414
MEMORY DECODER
WITH ON-CHIP SUPPLY VOLTAGE MONITOR
SCBS059B – MARCH 1989 – REVISED NOVEMBER 1993
logic diagram (positive logic)
VCC
20
VCOMP
Vbat
SD
1A
1
19
18
2
1G
2G
G
17
5
15
2B
1Y1
1Y2
1Y3
7
8
9
14
2A
1Y0
3
16
1B
VS
4
13
12
6
2Y0
2Y1
2Y2
11
2Y3
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–3
SN74BCT2414
MEMORY DECODER
WITH ON-CHIP SUPPLY VOLTAGE MONITOR
SCBS059B – MARCH 1989 – REVISED NOVEMBER 1993
FUNCTION TABLES
INPUTS
CONTROL
OUTPUTS
SELECT
G
1G
SD
1B
1A
1Y0
1Y1
1Y2
1Y3
H
X
X
X
X
H
H
H
H
X
H
X
X
X
H
H
H
H
X
X
L
X
X
H
H
H
H
L
L
H
L
L
L
H
H
H
L
L
H
L
H
H
L
H
H
L
L
H
H
L
H
H
L
H
L
L
H
H
H
H
H
H
L
INPUTS
CONTROL
G
2G
OUTPUTS
SELECT
SD
2B
2A
2Y0
2Y1
2Y2
2Y3
H
X
X
X
X
H
H
H
H
X
H
X
X
X
H
H
H
H
X
X
L
X
X
H
H
H
H
L
H
H
L
L
L
H
H
H
L
H
H
L
H
H
L
H
H
L
H
H
H
L
H
H
L
H
L
H
H
H
H
H
H
H
L
NOTE: For a 3-line to 8-line decoder, the following pins must
be shorted: 1G to 2G, 1A to 2A and 1B to 2B.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, Vbat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Supply voltage VCC with respect to Vbat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1.5 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Off-state output voltage range at VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Voltage range applied to any Y output in the power-off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Voltage applied to any Y output in the power-off state with respect to Vbat . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability
2–4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74BCT2414
MEMORY DECODER
WITH ON-CHIP SUPPLY VOLTAGE MONITOR
SCBS059B – MARCH 1989 – REVISED NOVEMBER 1993
recommended operating conditions
MIN
NOM
MAX
VCC
Vbat
Supply voltage
4.5
5
5.5
V
Supply voltage
4.5
5
5.5
V
VIH
VIL
High-level input voltage
Low-level input voltage
0.8
V
IIK
IOH
Input clamp current
–18
mA
– 400
µA
IOL
Low level output current
Low-level
tt
TA
Input transition time
0
10
ns / V
Operating free-air temperature
0
70
°C
2
UNIT
V
High-level output current
Y outputs
8
VS outputs
20
mA
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
TEST CONDITIONS
VCC = 4.5 V,
Vb
45V
batt = VCC = 4.5
VOH
Vbat = 2 V, VCC = 0,
VOL
45V
Vb
batt = VCC = 4.5
IOL = 4 mA
IOL = 8 mA
VS
Vbat = VCC = 4.5 V,
IOL = 20 mA
Vbat = VCC = 5.5 V,
Vbat = VCC = 5.5 V,
VI = 5.5 V
VI = 2.7 V
Vbat = VCC = 5.5 V,
Vbat = 4.5 V,
VI = 0.5 V
VCC = 0
Vbat = VCC = 5.5 V,
VO = 2.25 V
Outputs high
TYP†
MAX
UNIT
–1.2
V
4.4
V
3.5
1.8
0.4
0.5
VS
ICC
Vb
55V
batt = VCC = 5.5
Vbat = 2.5 V,
Ibat
55V
Vb
batt = VCC = 5.5
Ci
Vbat = VCC = 5 V,
Any Y
VS
– 30
1
± 20
µA
± 20
µA
1
µA
– 200
mA
10
20
3
4
6.5
Vb
batt = VCC = 0
µA
3
Outputs low
VI = 0 or 3 V
V
100
3
Outputs low
VCC = 0
Outputs high
V
1
3.65
IIH
IIL
Co
IOH = – 400 µA
IOH = – 50 µA
All except VS
VT‡
II
IOH
IO§
II = –18 mA
IOH = – 20 µA
MIN
5
mA
µA
mA
pF
pF
† All typical values are at VCC = 5 V, TA = 25°C.
‡ This value represents the VCC monitor threshold voltage. Typical range is from 3.5 V to 3.8 V.
§ This output condition has been chosen to produce a current that closely approximates one half of the short-circuit output current, IOS. Not more
than one output should be tested at a time, and the duration of the test should not exceed one second.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–5
SN74BCT2414
MEMORY DECODER
WITH ON-CHIP SUPPLY VOLTAGE MONITOR
SCBS059B – MARCH 1989 – REVISED NOVEMBER 1993
switching characteristics (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
tPLH
tPHL
A or B
Any Y
tPLH
tPHL
Any G
Any Y
tPLH
tPHL
SD
Any Y
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX†
VCC = 5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = 25°C
TYP
MAX
MIN
MAX
1
5
10
1
12
2
5.8
10
2
12
1
4.5
9
1
10
2
5.5
9
2
11
2
6.5
11
2
12
2
6.5
11
2
12
UNIT
ns
ns
ns
switching characteristics (see Note 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
VCC
Any Y
tPLH
tPHL
VCC
VS
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX†
VCC = 5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = 25°C
MIN
TYP
MAX
MIN
MAX
10
25
50
10
250
15
45
100
15
250
10
28
50
10
250
20
50
100
20
250
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 1: Load circuits and voltage waveforms are shown in Section 1.
2–6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
ns
ns
SN74BCT2414
MEMORY DECODER
WITH ON-CHIP SUPPLY VOLTAGE MONITOR
SCBS059B – MARCH 1989 – REVISED NOVEMBER 1993
APPLICATION INFORMATION
A typical application circuit for a battery-buffered memory in a microcomputer system is shown in Figure 1 which uses
the SN74BCT2414. When power fails, the supply-voltage supervisor (TL7705) resets the microcomputer and
disables the memory by switching the shutdown input SD of the memory decoder to a logic zero. All memory decoder
outputs are forced to a logic one. Abnormal write commands from the microprocessor, which may be issued during
further voltage breakdown, no longer affect the contents of the memory. When the system supply voltage becomes
lower than approximately 3.65 V, the voltage monitor inside the SN74BCT2414 memory decoder disconnects the
input buffers of this circuit from the decoding logic internally and keeps all outputs at a logic one. The VS output is
also switched off, disconnecting the system supply voltage from the memory circuits. During this low-voltage
condition, the memory decoder and the memory circuits are supplied by the battery.
Microprocessor
8
D0 – D7
D3
VCC
A0 – A15
16
DBIN
R3
R1
Q1
WE
R2
D1
1N4148
1 kΩ
RESET
SN74BCT2414
VS
VCC
Vbat
A15
5V
A14
TL7705A
10 kΩ
A13
VCC
RES
SENSE
RESIN
1G
1Y0
2G
1Y1
1B
1Y2
2B
1Y3
1A
2Y0
2A
2Y1
SD
2Y2
G
2Y3
VCC
CE
VREF
Ct
GND
0.1 µF
A0 – A12
OE
0.1 µF
WR
8- × 8K-Byte CMOS RAM
For further information on this device, please contact factory.
Figure 1. Memory System With Battery Backup
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–7
SN74BCT2414
MEMORY DECODER
WITH ON-CHIP SUPPLY VOLTAGE MONITOR
SCBS059B – MARCH 1989 – REVISED NOVEMBER 1993
2–8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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Copyright  1998, Texas Instruments Incorporated