SEMICONDUCTOR TECHNICAL DATA High–Performance Silicon–Gate CMOS The MC54/74HC14A is identical in pinout to the LS14, LS04 and the HC04. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC14A is useful to “square up” slow input rise and fall times. Due to hysteresis voltage of the Schmitt trigger, the HC14A finds applications in noisy environments. • • • • • • • J SUFFIX CERAMIC PACKAGE CASE 632–08 14 1 N SUFFIX PLASTIC PACKAGE CASE 646–06 14 Output Drive Capability: 10 LSTTL Loads 1 Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 2 to 6V D SUFFIX SOIC PACKAGE CASE 751A–03 Low Input Current: 1µA 14 High Noise Immunity Characteristic of CMOS Devices 1 In Compliance With the JEDEC Standard No. 7A Requirements Chip Complexity: 60 FETs or 15 Equivalent Gates DT SUFFIX TSSOP PACKAGE CASE 948G–01 14 1 LOGIC DIAGRAM ORDERING INFORMATION A1 A2 A3 1 2 3 4 5 6 MC54HCXXAJ MC74HCXXAN MC74HCXXAD MC74HCXXADT Y1 Y2 Y3 FUNCTION TABLE Y=A A4 A5 A6 9 8 11 10 13 12 Y4 Pin 14 = VCC Pin 7 = GND Y5 Y6 Pinout: 14–Lead Packages (Top View) VCC A6 Y6 A5 Y5 A4 Y4 14 13 12 11 10 9 8 1 2 3 4 5 6 7 A1 Y1 A2 Y2 A3 Y3 GND 10/95 Motorola, Inc. 1995 Ceramic Plastic SOIC TSSOP 1 REV 7 Inputs Outputs A Y L H H L ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MC54/74HC14A MAXIMUM RATINGS* Symbol VCC Parameter DC Supply Voltage (Referenced to GND) Value Unit – 0.5 to + 7.0 V V Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V DC Input Current, per Pin ± 20 mA Iout DC Output Current, per Pin ± 25 mA ICC DC Supply Current, VCC and GND Pins ± 50 mA PD Power Dissipation in Still Air, Plastic or Ceramic DIP† SOIC Package† TSSOP Package† 750 500 450 mW Tstg Storage Temperature Range – 65 to + 150 _C Iin TL This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. v v _C Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package Ceramic DIP 260 300 * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. †Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C Ceramic DIP: – 10 mW/_C from 100_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: – 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature Range, All Package Types tr, tf Input Rise/Fall Time (Figure 1) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Min Max Unit 2.0 6.0 V 0 VCC V – 55 + 125 _C 0 0 0 No Limit* No Limit* No Limit* ns * When Vin = 50% VCC, ICC > 1mA MOTOROLA 2 High–Speed CMOS Logic Data DL129 — Rev 6 MC54/74HC14A DC CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Condition Guaranteed Limit VCC V –55 to 25°C ≤85°C ≤125°C Unit VT+ max Maximum Positive–Going Input Threshold Voltage (Figure 3) Vout = 0.1V |Iout| ≤ 20µA 2.0 3.0 4.5 6.0 1.50 2.15 3.15 4.20 1.50 2.15 3.15 4.20 1.50 2.15 3.15 4.20 V VT+ min Minimum Positive–Going Input Threshold Voltage (Figure 3) Vout = 0.1V |Iout| ≤ 20µA 2.0 3.0 4.5 6.0 1.0 1.5 2.3 3.0 0.95 1.45 2.25 2.95 0.95 1.45 2.25 2.95 V VT– max Maximum Negative–Going Input Threshold Voltage (Figure 3) Vout = VCC – 0.1V |Iout| ≤ 20µA 2.0 3.0 4.5 6.0 0.9 1.4 2.0 2.6 0.95 1.45 2.05 2.65 0.95 1.45 2.05 2.65 V VT– min Minimum Negative–Going Input Threshold Voltage (Figure 3) Vout = VCC – 0.1V |Iout| ≤ 20µA 2.0 3.0 4.5 6.0 0.3 0.5 0.9 1.2 0.3 0.5 0.9 1.2 0.3 0.5 0.9 1.2 V VHmax Note 2 Maximum Hysteresis Voltage (Figure 3) Vout = 0.1V or VCC – 0.1V |Iout| ≤ 20µA 2.0 3.0 4.5 6.0 1.20 1.65 2.25 3.00 1.20 1.65 2.25 3.00 1.20 1.65 2.25 3.00 V VHmin Note 2 Minimum Hysteresis Voltage (Figure 3) Vout = 0.1V or VCC – 0.1V |Iout| ≤ 20µA 2.0 3.0 4.5 6.0 0.20 0.25 0.40 0.50 0.20 0.25 0.40 0.50 0.20 0.25 0.40 0.50 V VOH Minimum High–Level Output Voltage Vin ≤ VT– min |Iout| ≤ 20µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 Vin ≤ VT– min VOL Maximum Low–Level Output Voltage |Iout| ≤ 2.4mA |Iout| ≤ 4.0mA |Iout| ≤ 5.2mA Vin ≥ VT+ max |Iout| ≤ 20µA Vin ≥ VT+ max Iin ICC |Iout| ≤ 2.4mA |Iout| ≤ 4.0mA |Iout| ≤ 5.2mA V Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0µA 6.0 1.0 10 40 µA 1. Information on typical parametric values along with frequency or heavy load considerations can be found in Chapter 2 of the Motorola High– Speed CMOS Data Book (DL129/D). 2. VHmin > (VT+ min) – (VT– max); VHmax = (VT+ max) – (VT– min). High–Speed CMOS Logic Data DL129 — Rev 6 3 MOTOROLA MC54/74HC14A AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns) Symbol Parameter Guaranteed Limit VCC V –55 to 25°C ≤85°C ≤125°C Unit tPLH, tPHL Maximum Propagation Delay, Input A or B to Output Y (Figures 1 and 2) 2.0 3.0 4.5 6.0 75 30 15 13 95 40 19 16 110 55 22 19 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 2) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 16 110 36 22 19 ns 10 10 10 pF Cin Maximum Input Capacitance NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High– Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Inverter)* 22 pF * Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). tf INPUT A tr VCC 90% 50% 10% GND tPLH tPHL 90% OUTPUT Y 50% 10% tTLH tTHL Figure 1. Switching Waveforms TEST POINT OUTPUT DEVICE UNDER TEST CL* *Includes all probe and jig capacitance Figure 2. Test Circuit MOTOROLA 4 High–Speed CMOS Logic Data DL129 — Rev 6 VT , TYPICAL INPUT THRESHOLD VOLTAGE (VOLTS) MC54/74HC14A 4 3 (VT+) VHtyp 2 (VT–) 1 2 3 4 5 VCC, POWER SUPPLY VOLTAGE (VOLTS) 6 VHtyp = (VT+ typ) – (VT– typ) Figure 3. Typical Input Threshold, VT+, VT– versus Power Supply Voltage A Y (a) A Schmitt–Trigger Squares Up Inputs With Slow Rise and Fall Times VH Vin (b) A Schmitt–Trigger Offers Maximum Noise Immunity VCC VH VT+ VT– Vin VCC VT+ VT– GND GND VOH VOH Vout Vout VOL VOL Figure 4. Typical Schmitt–Trigger Applications High–Speed CMOS Logic Data DL129 — Rev 6 5 MOTOROLA MC54/74HC14A OUTLINE DIMENSIONS J SUFFIX CERAMIC DIP PACKAGE CASE 632–08 ISSUE Y -A14 8 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMESNION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. -B- C -T- L DIM A B C D F G J K L M N K SEATING PLANE F G D 14 PL 0.25 (0.010) M N T A M J 14 PL 0.25 (0.010) S M T B S INCHES MIN MAX 0.750 0.785 0.245 0.280 0.155 0.200 0.015 0.020 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0° 15° 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.94 7.11 6.23 5.08 3.94 0.50 0.39 1.65 1.40 2.54 BSC 0.38 0.21 4.31 3.18 7.62 BSC 15° 0° 0.51 1.01 N SUFFIX PLASTIC DIP PACKAGE CASE 646–06 ISSUE L 14 NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. 8 B 1 7 A F DIM A B C D F G H J K L M N L C J N H MOTOROLA G D SEATING PLANE K M 6 INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01 High–Speed CMOS Logic Data DL129 — Rev 6 MC54/74HC14A OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751A–03 ISSUE F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. –A– 14 8 P 7 PL –B– 1 0.25 (0.010) 7 G D 0.25 (0.010) T M F J M K 14 PL M R X 45° C SEATING PLANE B M B S A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.75 8.55 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7° 0° 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 7° 0° 0.228 0.244 0.010 0.019 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G–01 ISSUE O 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. S S N 2X 14 L/2 0.25 (0.010) 8 M B –U– L PIN 1 IDENT. F ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ ÇÇÇ ÉÉÉ ÇÇÇ ÉÉÉ ÇÇÇ 7 1 0.15 (0.006) T U N S DETAIL E K A –V– K1 J J1 SECTION N–N –W– C 0.10 (0.004) –T– SEATING PLANE D High–Speed CMOS Logic Data DL129 — Rev 6 G H DETAIL E 7 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 ––– 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 ––– 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MOTOROLA MC54/74HC14A Motorola reserves the right to make changes without further notice to any products herein. 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Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 MFAX: [email protected] –TOUCHTONE (602) 244–6609 INTERNET: http://Design–NET.com HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MOTOROLA ◊ CODELINE 8 *MC54/74HC14A/D* MC54/74HC14A/D High–Speed CMOS Logic Data DL129 — Rev 6