ADDTEK A704

A704
SWITCHING MODE LED DRIVER
www.addmtek.com
DESCRIPTION
FEATURES
The A704 is a PWM high efficiency LED driver
controller. The LED string is driven at constant current
rather than constant voltage, thus providing constant light
output and enhanced reliability.
Low Startup Current (5uA in typical).
Low Operating Current (3mA in typical).
Lead-Edge Blanking.
Internal OVP Detected.
150°C OTP Sensor with Hysteresis.
Under Voltage Lockout (UVLO).
Fixed PWM Frequency.
PFC > 0.9 with Suitable External Components.
TYPICAL APPLICATION CIRCUIT
APPLICATIONS
B22, E27 lamp device
RD
V DD
EN
R1
A704
Gate
D BR
L1
CS
C s *Note
GND
DR
PACKAGE PIN OUT
RG
Q
85V AC Bridge
|
235V AC Diode
General purpose lighting
CX
C IN
R CS
L
LED
DF
C OUT
*Note: C S MUST be very close to A704’s V DD pin and GND pin.
Please refer to ADDtek’s reference layout.
Gate
1
GND
2
EN
3
5
VDD
4
CS
SOT-23-5
(Top View)
ORDER INFORMATION
W
SOT-23-5
5 pin
A704WFT
Note: The letter “F” is marked for Lead Free parts, and letter “T” is marked for Tape & Reel.
Contack Info:Samsun Zhang 13556850583 [email protected]
Copyright © 2008 ADDtek Corp.
1
A704_V0.6 -- AUGUST 2008
A704
ABSOLUTE MAXIMUM RATINGS
(Note)
Input Voltage, VDD
32V
Operating temperature
-20°C ~85°C
Maximum Operating Junction Temperature, TJ
150℃
Storage Temperature Range
-65°C to 150°C
Lead Temperature (Soldering, 10 seconds)
260°C
Note: Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground.
Currents are positive into, negative out of the specified terminal.
BLOCK DIAGRAM
Internal Bias
5 VDD
[email protected]
UVLO 16V/8V
Duty Cycle Limit
EN
OSC
3
S
130/65kHz
PWM
Latch
Q
1 Gate
LEB
250ns
4 CS
R
+
GND
Driver
2
-
Comparator
0.5V
PIN DESCRIPTION
Pin Name
Pin Function
Gate
Drives the gate of the external MOSFET.
GND
Power Ground Pin.
EN
Enable Pin.
CS
Current Sense Pin
VDD
Input Power Supply Pin and Over Voltage Protected Pin.
Contack Info:Samsun Zhang 13556850583 [email protected]
Copyright © 2008 ADDtek Corp.
2
A704_V0.6 -- AUGUST 2008
A704
THERMAL DATA
Thermal Resistance from Junction to Ambient, θ JA
TBD °C /W
Junction Temperature Calculation: TJ = TA + (PD × θ JA).
The θJA numbers are guidelines for the thermal performance of the device/pc-board system.
Connect the ground pin to ground using a large pad or ground plane for better heat dissipation.
All of the above assume no ambient airflow.
Maximum Power Calculation:
PD(MAX)= TJ(MAX) – TA(MAX)
θJA
TJ(OC):
Maximum recommended junction temperature
TA(OC):
Ambient temperature of the application
θJA(OC /W):
Junction-to-Ambient thermal resistance of the package, and other heat dissipating materials.
Contack Info:Samsun Zhang 13556850583 [email protected]
Copyright © 2008 ADDtek Corp.
3
A704_V0.6 -- AUGUST 2008
A704
ELECTRICAL CHARACTERISTICS
VDD=20VDC, CLoad=1nF, RLoad=2.2Ω in series, TA=25°C, unless otherwise noted.
Description & Conditions
Parameter
Conditions
Min
Typ
6.5
Max
Unit
32
V
Input Supply Voltage
VDD
Input Supply Current
IDD
After start-up, VDD=20V
3
5
mA
Input Quiescent Current
IQC
Before start-up, VDD=15V
5
30
uA
Input Shutdown Current
ISD
VDD pin, after start-up.
VDD=20V, VEN=Low
1
2
mA
17
18
V
8
V
Under-Voltage Lockout, Turn On
VUVLO,ON
16
Under-Voltage Lockout, Turn Off
VUVLO,OFF
6
Over-Voltage Protection
VOVP
Current Sense Voltage
VCS
485
Enable Input Logic “High”
VIH
Enable Input Logic “Low”
VIL
Oscillator Maximum Duty Cycle
26
V
500
515
mV
2.2
6
V
0
0.8
V
50
%
200
250
nS
50
75
nS
DMAX
Leading Edge Blanking
tLEB
CS to Gate Pin Delay Time
tPD
Minimum Turn-ON Time
VDD pin
150
CS=“1”, Gate=“0”
tON,MIN
300
nS
Thermal Shutdown Temperature
TSD
150
°C
Thermal Shutdown Recovery
Temperature
TREC
120
°C
Switching Frequency
fSW
50
Gate Pin Source Current
70
kHz
ISOURCE
CLoad=1nF
300
mA
Gate Pin Sink Current
ISINK
CLoad=1nF
500
mA
Gate Pin Maximum Voltage
VGate
20
V
Contack Info:Samsun Zhang 13556850583 [email protected]
Copyright © 2008 ADDtek Corp.
4
A704_V0.6 -- AUGUST 2008
A704
CHARACTERISTIC CURVES
AC Input Voltage and Current
Output Voltage and Current
VIN, AC
V IN, AC
(100V/DIV)
(10V/DIV)
IIN, AC
I IN, AC
(500mA/DIV)
(500mA/DIV)
TIME= 10ms/DIV
TIME= 10ms/DIV
Line Regulation
Load Regulation
500
400
VOUT=12V
400
IOUT (mA)
IOUT (mA)
390
380
370
300
200
360
100
350
0
85
145
205
265
110VAC
10
V IN,AC (V)
15
20
25
30
V OUT (V)
IOUT(%)
Sample to Sample Offset vs.
Temperature
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
Sample1 90V
Sample1 240V
Sample2 90V
Sample2 240V
Sample3 90V
Sample3 240V
-40
-20
0
20 40
60
Temperature(℃ )
80
100 120
Contack Info:Samsun Zhang 13556850583 [email protected]
Copyright © 2008 ADDtek Corp.
5
A704_V0.6 -- AUGUST 2008
A704
APPLICATION INFORMATION
The A704 PWM controller is a monolithic integrated circuit, design for High Brightness LED application,
provides the necessary feature to implement LED driver with a minimal external component needed. Internally
implemented function include, a low start up current and operating current reducing the power dissipation on start-up
resistor, Built-in OVP and UVLO function detected the LED output whether open and short circuit occur, SOT-23
package can save your PCB layout spaces and easy design into place you want, …etc.
Application Circuit:
R6
VDD
R2
EN
A704
Gate
DBR
DR
C5
R7
L1
Bridge
GND
CS
R8
Q1
CX
CIN1
DF
Diode
LED
L2
R4
C8
Fig. 1 - Typical Application circuit
Circuit Topology
A Buck converter is an excellent choice for LED driver in off line application provides a constant LED current.
A peak current controlled buck converter can give reasonable LED current variation over a wide input rang and LED
voltage when the converter is implemented in continuous conduction mode. The A704 is a “Buck” or Step-Down
Converter controller and its typical application circuit was shown as Fig.1. Simplify Fig. 1, its basic schematic can be
seen in Fig.2.
Rsense
Q1
Vin
Vout
L
Vd
DF
Cout
RLoad
Fig 2. Basic Buck converter
Contack Info:Samsun Zhang 13556850583 [email protected]
Copyright © 2008 ADDtek Corp.
6
A704_V0.6 -- AUGUST 2008
A704
The operation of this regulator topology has two distinct time periods. The first one occurs when the series
switch is “on”, the input voltage is connected to the input of the inductor. The output of the inductor is the output
voltage, and the rectifier (or catch diode) is reverse biased. During this period, since there is a constant voltage source
connected across the inductor, the inductor current begins to linearly ramp upwards, as described by the following
equation:
I L (on) =
(Vin − Vout ) × t on
L
During this “on” period, energy is stored within the core material in the form of magnetic flux. If the inductor is
properly designed, there is sufficient energy stored to carry the requirements of the load during the “off” period.
The next period is the “off” period of the power switch. When the power switch turns off, the voltage across the
inductor reverses its polarity and is clamped at one diode voltage drop below ground by the catch diode. The current
now flows through the catch diode thus maintaining the load current loop. This removes the stored energy from the
inductor. The inductor current during this time is:
I L(off ) =
Vout × (Ts − t on )
L
This period ends when the power switch is once again turned on. Regulation of the converter is accomplished by
varying the duty cycle of the power switch. It is possible to describe the duty cycle as follows:
t
D = on
Ts
Where, Ts is period of switching, and ton is ” turn on” time of Q1.
For the buck converter with ideal components, the duty cycle can also be described as: Figure 3 shows the buck
converter, idealized waveforms of the catch diode voltage and the inductor current.
Inductor Current
Inductor Voltage
Vd - Vout
Time
-Vout
IPK
0
ton
ILoad(AV)
Ts
Time
Fig 3. Basic Buck converter
Contack Info:Samsun Zhang 13556850583 [email protected]
Copyright © 2008 ADDtek Corp.
7
A704_V0.6 -- AUGUST 2008
A704
Component Selection
This application note discusses the design of a buck-based LED driver using A704 with the help of an off-line
application example. . In this example, Vin= 90~240Vac & LED string voltage= 12V are used. Anyway, the same
procedure can be used to design LED drivers with wide AC voltage input & DC voltage output.
1. Maximum output voltage consideration ( Vo, max )
The first design criterion to meet is that the maximum LED string voltage Vo,max is should be less than half the
minimum input voltage to avoid having to implement a special loop compensation technique. For this example, the
minimum input voltage Vin, dc should be:
Vin, dc _ min = 2 × Vo, max
Where, Vin,dc _ min is the minimum voltage of bridge diodes
For example, the Vin,dc _ min in the circuit of this application note is about 100V. So the Vo,max (LED string
voltage) should < 50V.
2. Choose the Input Diode Bridge (DBR)
The voltage rating of the bridge diode Vbridge will depend on the maximum value of the input voltage. The
current rating will depend on the maximum average current drawn by the converter.
Vbridge = 1.25 × ( 2 × Vmax,ac ) …(1)
Where, Vmax, ac is the maximum input voltage RMS value.
The 1.25 factor in equation (1) is used for a safety margin.
For this design, the Vbridge should be exceed than (1.25* 1.414* Vmax, ac )= (1.25*1.414* 240)=425 V. A 600V,
0.5A bridge diode is chosen in the example.
3. Choose the Input inductor and input Capacitors
Placing an inductor (L1) in series with input bridge rectifier reduces input current rejection to input source. At
this times, utilizing the equivalents series resistance (ESR) of L1 to limit the inrush current charge to input bulk
capacitor C1. The ESR should limit the inrush current not more than the Maximum Peak forward Surge Current (IFSM)
of the bridge rectifier specification as given by equation (2), assuming maximum voltage is applied. The required
resistance is:
ESR ≥
Vbridge
I FSM
(2)
Contack Info:Samsun Zhang 13556850583 [email protected]
Copyright © 2008 ADDtek Corp.
8
A704_V0.6 -- AUGUST 2008
A704
In this design, the Vbridge is 425 V and IFSM is 30A. So the ESR of the chock should > (425/30)=14.1Ω. If the
power loss of such high ESR chock is too high, the designer can replace the high ESR chock with a low ESR chock
and add a negative-temperature-coefficient (NTC) resistor to limit the inrush current. As long as the (NTC (hot)
resistance + low ESR Chock resistance) is lower than the resistance of the high ESR chock, the efficiency of the A704
DC-DC can be improved.
The hold-up and input filter capacitor required at the diode bridge output have to be calculated at the minimum
AC input voltage. The minimum capacitor value can be calculated as:
In this design, C1 ≥
Vo, max × I o, max × (1 − 2 × freq × tc )
2
2
(2 × Vmin,
ac − Vmin, dc ) ×η × freq
Where, freq is the AC input frequency, as a rule, freq is 50 ~ 60Hz.
η is efficiency of the system , and tc is the conduction angle of the AC input, use 45°
conduction angle if unknown.
C1 ≥
12 × 0.35 × (1 − 0.5)
(2 × 90 2 − 90 2 ) × 0.8 × 60
≥ 5.4uF
The voltage rating of the capacitor should be at least 1.15 times greater than the peak input voltage for a safety
margin. For example, the input 220Vac input, the input capacitor voltage should exceed than as:
Vmax, cap ≥ 1.15 × 2 × Vmax, ac ⇒ Vmax, ac ≥ 360V
Choose a 400V/ 10µF electrolytic capacitor in the example.
Such electrolytic capacitor has sizable ESR component. The large ESR of these capacitors makes it inappropriate
to absorb the high frequency ripple current generated by the buck converter. Thus, adding a small MLCC capacitor in
parallel with the electrolytic capacitor is recommended.
4. Choose the power choke
The inductor selection should make the Buck converter work in CCM; the inductor value depends on the ripple
current in the LEDs. For example, assume a +/- 30% ripple current in the LEDs. Then, the inductor can be calculated
as:
L=
Vo (1 − D)Ts
0.6 I o ×η
In this design example, Ts is 16.6µ s, D=0.12, Vo=12Vdc , η =0.8, Io=0.35
L=
12 × (1 − 0.12) × 16.6µ
= 1.05mH
0.6 × 0.35 × 0.8
Choose the power choke inductance is 1mH.
Contack Info:Samsun Zhang 13556850583 [email protected]
Copyright © 2008 ADDtek Corp.
9
A704_V0.6 -- AUGUST 2008
A704
Note that the inductance of most chocks drop when the chock current has DC-current components. This
inductance drop may cause the actual Io to be lower than the calculation value of Io (please refer the Rcs section of
this application note for more detail)
5: Choose the FET (Q1) and Diode (DF)
Since these power components (diode & MOSFET) maximum peak current exceeds the regulator maximum load
current, these components current rating must be at least 1.2 times greater than the maximum load current. And the
reverse voltage rating of these components should be at least 1.25 times the maximum input voltage. Therefore, the
peak voltage seen by the FET is equal to the maximum input voltage
VQ1 = 1.25 × Vmax, ac = 1.25 × ( 2 × 240) = 425V
Hence, the current rating of the FET is
I Q1 = 1.25 × I o , pk = 1.25 × 1.3 × 0.35 = 0.57 A
In the example, choose at least a 500V 2A N-channel MOSFET. A 600V/2A N-channel MOSFET can allow
more safety margin.
The peak voltage rating of the diode is as same as the Q1 MOSFET. Hence,
V DF = 1.25 × Vmax, ac = 1.25 × ( 2 × 240 ) = 425V
The average current through the diode is:
I DF = 1.25 × I o , pk = 1.25 × 1.3 × 0.35 = 0.57 A
Choose 600V 2A Trr=35nS Fast recovery diode in the example.
6. Choose the Sense Resistor (R4)
Since the output ripple current IPP is design for 0.6 times Io current.
V (1 − d )Ts
I pp = o
= 0.6 × I o
L
Therefore the Peak current can be given as:
I pk = I o + 12 I pp = 1.3 × I o
Hence, the sense resistor value is given by:
Rcs =
Vcs
V
= cs
1.3 × I o I pk
In the design example, use RCS = (0.5V/(1.3*0.35) =1.1Ω. Note that factors like inductor value deviation could
cause the actual Io to be higher (or lower) than the ideal value. So we may need to fine-tune the Rcs value for accurate
Io.
Copyright © 2008 ADDtek Corp.
10
A704_V0.6 -- AUGUST 2008
A704
7. Start-up Circuitry
When the power is turned on, the input rectified voltage Vin, dc charges the hold-up capacitor C5 and the
output capacitor Cout via a start-up resistor Rin as shown in Fig. 4. As the voltage of VCC pin reaches the start
threshold voltage VTH (ON ) , the A704 activates and drives the entire power supply to work.
−T
VTH (ON )
D
C out
(Vin − I DDST ⋅ Rin )(1 − e Rin ⋅(C5 // Cout ) )
≅
C out + C5
Where IDDST is the start-up current of A704
VDD
Gate
RIN
CS
C5
GND
IDDST
VIN
COUT
Fig.4. Start-up Circuitry
Since the start-up current IDDST is only 5uA typical, a large RIN such as 2M ohms can be used. Also with a C5 is
2.2uF/50V, and Cout is 22uF/50V, the Start-up delay TD_ON is less than 0.63 sec for 90Vac input.
For example, if the input voltage Vin, dc is 310Vdc, output voltage Vo=12Vdc, and start-up resistor Rin is
2MΩ,the power dissipation on the Rin is:
PRin =
Vin2,dc − 2Vo2
R IN
=
310 2 − 2 × 12 2
= 48mW
2M
Contack Info:Samsun Zhang 13556850583 [email protected]
Copyright © 2008 ADDtek Corp.
11
A704_V0.6 -- AUGUST 2008
A704
LAYOUT GUIDELINES
1.
PCB Layout consideration:The hold-up capacitor C5 need closed by the VDD pin of the controller IC。
2.
PCB Layout consideration: Please must put these components, (Cin1, Q1, R4, DF) & (Q1,704, R4,R7), as close as
possible to each other when in PCB placement ( refer to Fig-1, Fig-11 & Fig-12). An A704 DC-DC may not work
well if some of these components are placed far away from others.
3.
When the MOSFET turned on, a spike, which is induced by the diode reverse recovery and by the output
capacitances of the MOSFET and diode, inevitably appears on the sensed signal. Inside A704, a leading edge
blanking time about 250nsec is introduced to avoid premature termination of MOSFET by the spike. Therefore,
only a small-value RC filter (e.g. 100ohm + 470pF) is required between the SENSE pin and RS.
4.
A704 output stage is a totem pole driver stage that can directly drive MOSFET gate. It is also equipped with a
voltage clamping circuit to protect MOSFET from damage caused by undesirable over drive voltage. The output
voltage is clamped at 20Vmax. An external pull down resistor Rx in the range of 10k to 47k ohm is used to avoid
floating state of gate before startup. A gate drive resistor Rg in the range from several to several tens ohm is
recommended. This resistor limits the peak gate drive current and provides damping to prevent oscillations at the
MOSFET gate terminal.
Rg
VDD
Gate
RF
CS
GND
RS
CF
Rx
L
DF
COUT
Fig.10. Gate drive
5.
The power stage ground and the controller loop ground in this circuit is different, therefore, the measurement
equipment need be isolated with device under test (DUT).
6.
When output load is open/disconnect, the output voltage would increase the value of the over-voltage protection.
However, the start-up circuitry still charges energy to the output capacitor; Placed a dummy load in the range of
10k to 47k ohm in the output is recommended.
Contack Info:Samsun Zhang 13556850583 [email protected]
Copyright © 2008 ADDtek Corp.
12
A704_V0.6 -- AUGUST 2008
A704
Figure 11. Top layer
Figure 12. Bottom layer.
Table 1. Bill of Material list
C.R. NO
Q’TY
Description
Vendor
A704 control IC
ADD
Package
A1
1
Q1
1
Power NMOS 02N60H
APEC
TO-252,
CIN1
1
E.C Cap:10uF/ 400V
NCC
DIP D10x16mm
CX
1
Cap X1 MPP 0.1uF
Chiefcon
CKX104M
L1
1
IND 2.2mH
GangSong
L2
1
IND 1mH
GangSong
DF
1
DIO Super fast 600V 2A,
PANJIT
SOT23-5
SMB
DR
1
DIO Fast Diode 600V 1A,
PANJIT
SMA
DBR
1
Bridge Diode 600V 0.5A B6S
PANJIT
MDI
R2, R8
2
1MΩ
relac
SMD 1206
R4
1
1.1Ω
relac
SMD 0805
R6
1
12Ω
relac
SMD 0805
R7
1
47kΩ
relac
SMD 0805
C5
1
E.C Cap:2.2uF/ 50V
NCC
D5x11
C8
1
E.C Cap:22uF/ 50V
NCC
D5x11
Contack Info:Samsun Zhang 13556850583 [email protected]
Copyright © 2008 ADDtek Corp.
13
A704_V0.6 -- AUGUST 2008
A704
IMPORTANT NOTICE
ADDtek reserves the right to make changes to its products or to discontinue any integrated circuit product or service
without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing
orders, that the information being relied on is current.
A few applications using integrated circuit products may involve potential risks of death, personal injury, or severe
property or environmental damage. ADDtek integrated circuit products are not designed, intended, authorized, or
warranted to be suitable for use in life-support applications, devices or systems or other critical applications. Use of
ADDtek products in such applications is understood to be fully at the risk of the customer. In order to minimize risks
associated with the customer’s applications, the customer should provide adequate design and operating safeguards.
ADDtek assumes to no liability to customer product design or application support. ADDtek warrants the performance of
its products to the specifications applicable at the time of sale.
Contack Info:Samsun Zhang 13556850583 [email protected]
Copyright © 2008 ADDtek Corp.
14
A704_V0.6 -- AUGUST 2008