AD AND8020

AND8020/D
Termination of ECL
Logic Devices with
EF (Emitter Follower)
OUTPUT Structure
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Prepared by: Paul Shockman
ON Semiconductor Logic Applications Engineering
APPLICATION NOTE
CONTENTS OF APPLICATION NOTE
Introduction − DC Termination Analysis
Section 3. Thevenin Equivalent/Parallel Termination
Section 1. Unterminated Lines
R
R
R
R
RE
VEE
Section 2. Parallel Termination − External and Internal
External
Section 4. Series (Back) Termination
R
Rt
Rt
RE
Rt
RE
RE
R
RE
VTT
VEE
Section 5. Diode Termination
Near (Standard Pair)
Far (Standard Pair)
VBB
Internal
D2
D1
Driver
*
Receiver
*
RE
RE
VEE V
Rt
Rt
Vt
to
(Open)
Rt
Rt
*All Media
D1
D2
VBB
VTT
Section 6. Capacitive Coupling
R
RE
RE
VEE
Vt1
Vt2
Rt
Rt
(Shorted)
Near (Standard Pair)
 Semiconductor Components Industries, LLC, 2004
July, 2004 − Rev. 5
Vt1
Vt2
VTT
Rt
Rt
R
VBB
R
R
R
VCC
Far (Standard Pair)
1
Publication Order Number:
AND8020/D
AND8020/D
INTRODUCTION
Static DC Termination Analysis
A standard Emitter Coupled Logic (ECL) output driver
typically uses a current switching differential with an emitter
follower for level shifting the output and the internal CML
levels to familiar ECL levels. This output driver architecture
presents about 6−8 internal impedance in both LOW and
HIGH states when properly current biased. This results in a
typical VPP signal of 800 mVPP (measured single−endedly on
each line) swinging around a DC voltage point of
VCC − 1.3 V when properly terminated and operating
correctly as shown in Figure 1.
VCC
VCC
8 Internal Output
Impedance
Q
D
Q
D
RE
RE
VEE
VEE
VEE
Driver
Receiver
Figure 1. Typical ECL Output with Emitter Follower Output Structure,
Typical Termination, and Typical ECL Input Interconnect
Output
Driver
Signal
For proper static and dynamic operation, the output
emitter follower transistor must remain in the active region
of operation which requires an external resistive path be
provided from the output pin to a voltage more negative than
worst case VOL, such as VEE. The resistor, RE, is considered
a current bias for the Emitter Follower output structure.
When properly terminated and current biased (loaded),
the outputs will generate both: (1) static state voltage levels
VOL (LOW) or VOH (HIGH) and (2) a dynamic transition
edge (tr or tf) between state levels.
Input
Receiver
Signal
VCC
VIH
VOH
VCC −1.3 V
VOL
VIL
VEE
tr
Static State Voltage Levels
Figure 2 illustrates the typical relationship of static signal
levels and dynamic transition edges between an Output
Driver Signal and a Receiver Input Signal. Both outputs of
a differential driver should always be terminated and loaded
as identically as possible to preserve minimum skew and
jitter operation of the device.
tf
VCC
VIH
VOH
VCC −1.3 V
VOL
VIL
VEE
tf
tr
Figure 2. State Levels VOH, VOL,
and Dynamic Transitions at Q or Q and D or D
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AND8020/D
Dynamic Analysis of Termination Resistor RE
The dynamic function of the termination resistor, RE is to
develop the voltage change, V, during a high−to−low or
low−to−high transition and present this to the transmission
medium such as coax, twisted pair, microstrip or stripline.
The V signal propagates to the receiver and is either
reflected, dissipated, or a combination.
Since the reflection coefficient at the load is of opposite
polarity to that of the source, a reflection will travel back and
forth over the transmission changing polarity after each
reflection until critically damped by line impedance. Thus,
steps may appear in the signal V at the receiving gate input
due to impedance mismatch and consequent partial
reflections.
When RE is too large, steps appear in the trailing edge of
the propagating signal, V, at the input to the receiving gate,
slowing the edge speed and increasing the net propagation
delay. A reasonable negative−going signal swing at the input
of the receiving gate results when the value of RE is selected
to produce an initial step of 75% of the expected V, or a
600 mV step for an 800 mV signal at the driving gate. For
a RSECL expected V swing of 400, a 300 mV initial step
is desired. Hence for a 600 mV initial step:
Output Open, Short, and Safe DC Current
Left open, an output will only swing a few millivolts due
to parasitic “minimum current” leakage paths.
Shorted to VEE, a maximum current will develop, limited
only by the output transistor 8 impedance, and may cause
damage to the output. Worst case short circuit current risks
destruction of the devices.
ISC VOH 4 V
8
RINT
(eq. 1)
= 500 mA!
Where:
VOH = 4.0 V
VCC = 5.0 V
VEE = 0.0 V
Rint = 8 The continuous safe output current, Iout (continuous),
maximum limit is 50 mA under all spec operating
conditions. The continuous safe repetitive surge, Iout
(surge), maximum current limit is 100 mA for
10 milliseconds per second duty cycle, provided the device’s
total thermal limits are observed. Output current polarity
will always be sinking into the termination scheme during
proper operation.
I(init) * Z0 0.6
( VOH VEE )
* Z0 0.6
( Rt Z0 )
Static Analysis of Termination Resistor RE
The output continuous safe current limit, Iout (cont),
determines RE minimum DC termination scheme resistance
to VEE although this will not provide a practical AC signal
termination as shown in Table A: Minimum RE Values.
RE VOH
I max
The value for RE is found in Table B: Recommended
Values of RE in Dynamic Functional Application. This table
lists recommended RE values for the various ECL devices by
Family Series according to the equation above. The table
assumes operation with various data sheet VOH values and
various VCC values driving a Z0 = 50 line. Lowering the
value of RE will increase the voltage change, V, launched
into the transmission media. Raising the value of RE will
decrease the voltage change, V, launched into the
transmission media.
(eq. 2)
Table A. Minimum RE Values
Line
VOH
RE(min)
PECL
4.0 V
80 LVPECL
2.4 V
48 LVEP PECL
1.6 V
32 (eq. 3)
Table B. Recommended Nominal Values of RE in
Dynamic Functional Application
Series
A DC terminating resistor minimum, RE (min), of 80,
while sufficiently limiting the output load current to VEE,
may generate insufficient PECL output LOW and HIGH
state transitions.
The RE maximum is effectively determined by the
application load capacitance, CL, since an RC network is
formed by RE and CL which limits the signal fall time,
discharging the line to the LOW state voltage level. A
sufficiently high value RE or CL can cause the signal fall
time to the VOL level to violate specification limits.
Designed RE or CL values may selectively eliminate
undesirable noise.
|VCC−VEE|
RE (
NB
2.5
140
NB
3.3
250
10/100LVEP
2.5
50
10/100EP, 100LVEL
3.3
120
10/100EL, 10/100E
5.0
235
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AND8020/D
SECTION 1. UNTERMINATED LINES
Interconnect Line Lengths
The output signal Waveform rise (tr) and fall (tf) time are
measured from the 20% and 80% levels of the static signal
levels. This edge rate represents the waveforms highest
harmonic and determines the maximum unterminated open
line trace length, Lmax, permissible without sustaining
signal reflections.
The impetus in restricting interconnect lengths, L, is to
mitigate the effects of overshoot and undershoot. A handy
rule of thumb is that the undershoot can be limited to less
than 15% of the logic swing if the two way line delay is less
than the rise time of the pulse. With an undershoot of <15%,
the physics of the situation will result in an overshoot which
will not cause saturation problems at the receiving input.
Thus, the maximum line length can be determined:
R
From transmission line theory, when the driver RE
develops a V swing, the signal propagates from point A
arriving at point B at time Td later as shown in Figure 3. This
configuration is also referred to as a stub or an open line.
A
Td
B
T−Line Z0
RE
L max VEE
At point B, the signal is reflected as a function of L. If the
input impedance of the receiving gate is large relative to the
line characteristic impedance, according to Equation 4:
(eq. 4)
Where:
TpdEff Tpd
L = Load Reflection Coefficient
RL = Load Impedance
Z0 = Line Characteristic Impedance
A large positive reflection occurs resulting in overshoot.
The reflected signal reaches point A at time 2Td , and a large
negative reflection results because the output impedance of
the driver gate is much less than the line characteristic
impedance (i.e. RO << Z0 ).
When the reflected signal arrives at the source it is
reflected back toward the load with a magnitude dictated by
the source reflection coefficient:
S (Rs Z0)
(Rs Z0)
(eq. 6)
Where:
Lmax = Maximum Open Line Length
tr = Signal Rise Time
Tpd = Length Pulse Delay per Unit Length
Further, the propagation delay increases with gate
loading; thus, the effective delay per unit length (TpdEff) is
given as:
Figure 3. Unterminated Transmission Line Stub
L (RL Z0)
(RL Z0)
tr
2 * Tpd
1 L C* CD
(eq. 7)
O
Where:
Tpd = Length Pulse Delay per Unit Length
CD = Distributed Capacitance
CO = Capacitance per Unit Length (Foot)
L = Line Length
Using the effective delay per unit length, TpdEff, yields:
tr (2) (L) (Tpd )
1 L C* CD
(eq. 8)
O
Solving for Lmax line length produces:
(eq. 5)
L max 0.5
Where:
S = Source Reflection Coefficient
RL = Source Impedance
Z0 = Line Characteristic Impedance
The reflected signal continues to be reflected by the source
and load impedances and is attenuated with each passage over
the transmission line. The output response appears as a
damped oscillation asymptotically approaching a steady state
value. This phenomena is often referred to as “ringing.”
The importance of minimizing the reflected signals lies in
their adverse affect on noise margin and the potential for
driving the input transistors of the succeeding stage into
saturation. Both of these phenomena can lead to less than
ideal system performance. To maximize signal integrity on
transmission lines, four basic techniques are available:
1. Minimizing Interconnect Line Lengths (Section 1)
2. Parallel Termination (Sections 2 and 3)
3. Series Termination (Section 4)
4. Diode Termination (Section 5)
CD
CO
tr
tpd
2
2
C
D
CO
(eq. 9)
Where:
Lmax = Line Length Maximum
CD = Distributed Capacitance
CO = Capacitance per Unit Length (Foot)
Tpd = Length Pulse Delay per Unit Length
Assuming a worst case capacitance of 2 pF and a rise time
of 100 ps for EP gives a value of 0.03 inch for the maximum
open line length. Maximum open line lengths derived from
SPICE simulations for single and double gate loads, a
maximum overshoot of 40% and undershoot of 20% was
assumed. The simulation results indicate that for a 50 line,
a stub length of 0.03 inches will limit the overshoot to less
than 40%, and the undershoot to within 20% of the logic
swing. Signal traces will most assuredly be larger than
0.03 inch for most practical applications.
Therefore, it will be necessary to use controlled
impedance environments for EP devices in general and
devices with faster edges.
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AND8020/D
TERMINATION OF ECL LOGIC DEVICES
SECTION 2. PARALLEL TERMINATION − EXTERNAL AND INTERNAL
External
Internal
Rt
RE
RE
RE
VEE V
RE
Rt
Rt
Vt
to
(Open)
Rt
Rt
VTT
VEE
Near (Standard Pair)
RE
Rt
RE
Rt
Rt
Rt
Vt1
Vt2
VTT
VEE
(Shorted)
VTT
Far (Standard Pair)
Near (Standard Pair)
Method of choice for best circuit performance
Particularly excellent for driving distributed loads
Undistorted waveform along the full length of the line
Decreased power consumption.
Far DC Current Return − VTT
A parallel terminated line is one in which the receiving end
is signal terminated internally or externally (usually to a
voltage VTT) through a resistor (Rt) with a value equal to the
line characteristic impedance (Figure 4). This line also carries
the biasing current for the drivers output far from the driver.
Output current and power dissipation is decreased due to use
Driver
Receiver
Rt
Far (Standard Pair)
Driver
Receiver
*T−Line Z0
*T−Line Z0
*T−Line Z0
*T−Line Z0
(*or twisted pair)
(*or twisted pair)
Rt
Rt
of a VTT termination supply. The VTT supply must sustain the
emitter follower output transistor in its active operating region
under all operating conditions. A minimum continuous current
occurs for the most negative VOL, therefore the VTT supply
must remain more negative than the worst case VOLmin and
always sink current.
Standard VTT is 2.0 V below VCC supply. A parallel
resistor, Rt, matching the controlled impedance transmission
line, Z0, connects the signal to the VTT supply. The Parallel
Termination to VTT is shown in Figure 4. The termination
resistors may be internal or external and either ganged into a
Combo pin or offered as Singulated pins. Some devices may
have each internal resistors independently pinned out,
allowing further termination versatility.
Parallel termination advantages:
•
•
•
•
Vt1
Vt2
Rt
VTT
R
R
Vt
VTT
External (Far, Diff.)
Driver
Internal Termination Combo Pin (Far, Diff.)
Receiver
Driver
Receiver
*T−Line Z0
T−Line Z0
*T−Line Z0
Rt
Rt = Z0
VTT = VCC −2.0 V
(*or twisted pair)
VTT
VTT
External (Far, S.E.)
R
R
Vt1
Vt2
Internal Termination Singulated Pins (Far, Diff.)
Figure 4. Parallel Termination to VTT − Differential and Single−Ended with Combo or Singulated Vt Pins (Far Return)
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AND8020/D
Internal Termination Resistors
Internal termination conveniently uses 50 values for Rt,
with the most popular being Z0. Note the internal termination
allows the Combo Pin node, Vt, from the internal resistors to
be connected to an external VTT supply, typically at
VCC − 2.0 V, as shown in Figure 5. Alternatively, this Combo
Pin may be pulled to VEE through an external resistor to form
a “Y” type termination variant, as shown in Figure 5. See the
“Y Variance” topic and the “Y Term Table” for Rt3 resistor
values.
If +5% tolerances are assumed, two worst case conditions result.
Case #1: VCCmin = VCC − 5%, VTTmax = VTT + 5%
IOHmax (VOHmax VTT)
Rt
((3.135 0.885) 1.365)
17.7 mA
50
IOLmin (VOLmin VTT)
Rt
((3.135 1.685) 1.365)
1.7 mA
50
A.
Driver
Receiver
Case #2: VCCmin + 5%, VTTmax − 5%
*T−Line Z0
(VOHmax VTT)
Rt
((3.465 0.885) 1.235)
26.9 mA
50
*T−Line Z0
(*or twisted pair)
VTT Connection
IOHmax R
R
VTT
(VOLmin VTT)
Rt
((3.465 1.685) 1.235)
1.09 mA
50
IOLmin B.
Driver
Receiver
Y Variance
The “Y” termination for a differential pair may be
preferred when avoiding the use of a VTT supply. The design
is shown in Figure 6 and utilizes the following formulas for
calculating resistor values which are found in the Y Term
Table. The voltage at the Node where Rt1, Rt2, and Rt3
connect remains at a static VTT voltage of VCC − 2.0 V, or
1.3 V.
*T−Line Z0
*T−Line Z0
(*or twisted pair)
R
R
Y Connection
Rt3
VEE
Rt1 Rt2 Z0
Figure 5. Combo Pin VTT or “Y” Connection with
Internal Parallel Termination
Rt3 Rt1
Example Calculations
Ideally, VTT supply tracks 1:1 with VCC; however, supply
tolerances need to be considered. Assume for instance a
MC10EP16, +85°C, nominal +3.3 VCC, terminated 50 (Rt)
to VTT, where VTT is VCC − 2.0 V, or 1.3 V:
VTT VOHVTTVOLVEE2VTT
Rt3 ( VOH VOL ) ( Rt1 * VEE )
Rt1 2Rt3
(eq. 11)
(eq. 12)
Receiver
Driver
IOHmax of (VCC ) 0.885 V
*T−Line Z0
IOLmin of (VCC ) 1.685 V
*T−Line Z0
resulting in the nominal case:
* or Twisted Pair
(V
VTT )
IOHmax OHmax
Rt
(3.3 0.885) 1.3
22.3 mA
50
IOLmin (eq. 10)
Rt1
Rt2
Rt3
C1 0.1−0.01 F
VCC
(VOLmin VTT )
Rt
Figure 6. “Y” Variance
(3.3 1.685) 1.3
6.3 mA
50
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AND8020/D
Table C. Y Term Table
|VCC−VEE| = 5.0 V
|VCC−VEE| = 3.3 V
|VCC−VEE| = 2.5 V
Z0
Rt1
Rt2
Rt3
Z0
Rt1
Rt2
Rt3
Z0
Rt1
Rt2
Rt3
50
50
50
112
50
50
50
46
50
50
50
21.2
70
70
70
156
70
70
70
64
70
70
70
29.7
75
75
75
166
75
75
75
68
75
75
75
31.8
80
80
80
179
80
80
80
72
80
80
80
33.9
90
90
90
201
90
90
90
82
90
90
90
38.1
100
100
100
223
100
100
100
91
100
100
100
42.4
120
120
120
268
120
120
120
109
120
120
120
50.8
150
150
150
335
150
150
150
136
150
150
150
63.6
signal line pair. This can compliment a pull−down resistor, RE,
located on each line of a differential at the driver pins. This is
illustrated in Figure 8.
*T−Line Z0
*T−Line Z0
RE
RE
Rt
(*or twisted pair)
VEE
Driver
Receiver
*T−Line Z0
Figure 7. Standard Pair with External Parallel
*T−Line Z0
RE
Near DC Current Return − Standard Pair
Termination
The standard pair termination scheme uses a pull−down
resistor, RE, located at each driver pin to return the output
transistor bias current near the driver, and an impedance
matching parallel resistor, RT, located at the receiver input
pins (see Figure 7, standard pair with external parallel, and
Figure 8, standard pair termination with internal
termination, and Figure 9, standard pair termination with
singulated internal termination resistors). The impedance
matching parallel resistor may be internal or external
depending on the receiver device. If internal to the receiver,
the resistor may be singulated or combined (“combo”) for
external pinout.
The diagram of Figure 7 shows a Standard Pair
Termination with an RE resistor for DC output current bias
located nearby each driver pin: refer to Table B, for values
of RE. The differential transmission line AC impedance
matching resistance, Rt, is located externally near the
receiver input pins.
As a variation of a Standard Pair Termination, a receiver
may provide the differential transmission line AC
impedance matching resistance, Rt, internally. This internal
impedance matching termination may be pinned out either
combined into a Combo Vt pin or each resistor may be
singulated and pinned out, such as Vt1 and Vt2.
When left open, the Combo Pin still provides a passive
100 termination across the nearby receiver’s differential
RE
VEE
(*or twisted pair)
R
R
Open Vt Pin
Internal Termination Combo Pin
Figure 8. Standard Pair Termination with
Internal Termination
When the Internal Termination resistors are singulated,
the two Vt pins must be shorted to create the 100 value as
shown in Figure 9.
Driver
Receiver
*T−Line Z0
*T−Line Z0
RE
RE
VEE
(*or twisted pair)
Shorted
R
R
Vt1
Vt2
Internal Termination Singulated Pins
Figure 9. Standard Pair Termination with
Singulated Internal Termination Resistors
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AND8020/D
Internal 100 Termination (LVDS)
For some technologies, such as LVDS, this passive 100 internal termination can provide sufficient termination for the
driver as shown in Figure 10. Devices with a Combo Pin will
require this pin to remain open, while devices with singulated
internal resistors require the two pinned out Vt nodes for a
differential pair to be shorted together to provide the 100
termination.
LVDS Driver
this variation will simply move the level within the valid
specification window and no loss of worst case noise margin
will be seen.
The IOL situation on the other hand does pose a potential
AC problem. In the worst Case #1 IOLmin situation, the
output emitter follower could move into the cutoff state
(0 mA). The output emitter followers of ECL devices are
designed to be in the conducting, active region of operation
at all times. When forced into cutoff, the delay of the device
will be increased due to the extra time required to pull the
output emitter follower out of the cutoff state. Again, this
situation will arise only under a number of simultaneous
worst case situations and therefore, is highly unlikely to
occur. But, because of the potential, it should not be
overlooked.
Receiver
*T−Line Z0
*T−Line Z0
(*or twisted pair)
R
R
Output Drive Characteristics
Figure 11 shows the nominal output characteristics for
ECL devices operating in negative ECL mode, driving
various load impedances (including the standard 50)
returned to a negative two volt supply. The output
resistances, RH (high state output resistance) and RL (low
state output resistance), are obtained from the reciprocal of
the slope at the desired operating point. Many applications
require loads other than 50 − the resulting VOH and VOL
levels can be estimated using the following technique.
Open Vt Pin
Internal Termination Combo Pin
LVDS Driver
Receiver
*T−Line Z0
*T−Line Z0
(*or twisted pair)
0
R
SLOPE = 6 − 8 −5
Vt1
Vt2
OUTPUT CURRENT (mA)
Shorted
R
Internal Termination Singulated Pins
Figure 10. LVDS Interconnect with Internal
Termination
Differential ECL outputs can be terminated as independent
complimentary single−ended lines. Both sides of any
differential pair must be terminated as identically as possible
to minimize phase error and pulse width duty cycle skew.
The IOH currents in these two cases will vary the DC VOH
levels by 40 mV. However in the vast majority of cases, DC
levels are well centered in their specification windows, thus
150 to − 2.0 V
−10
−15
100 to − 2.0 V
−20
−25
−30
VOL
−35
−40
−2.0 −1.75
VOH
50 to − 2.0 V
25 to − 2.0 V
TA =25°C
−1.5
−1.25 −1.0 −0.75
−0.5 −0.25
OUTPUT VOLTAGE (V)
Figure 11. Normal Output Levels Driving Various
Load Impedances
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0
AND8020/D
SECTION 3. THEVENIN EQUIVALENT PARALLEL TERMINATION
R
R
R
R
The Thevenin equivalent of the two resistors needs to be
equal to the characteristic impedance of the signal
transmission line. Calculated values for resistors R1 and R2
may be obtained from the following relationships.
Although the single resistor termination to VTT conserves
power, it requires an additional supply voltage. An alternate
approach to using a VTT power supply is to use a resistor
divider network as shown in Figure 12 to develop a
Thevenin voltage, VTT, and provide a parallel impedance
matching AC termination, the Thevenin parallel
termination.
Receiver
*
R2
(eq. 15)
R2 50
0 125 55 3
(eq. 16)
R1 125
3 83.3 35 0
(eq. 17)
VTT 5
125125
3.0 V
83.3
(eq. 19)
For the typical VCC = 3.3 V LVPECL scheme, where
VEE = GND, VTT = 1.3 V, and Z0 = 50 :
R1
Receiver
*
R2 50
*
3.3 0 82.5 3.3
1.3
(eq. 20)
1.3 126 3.3
1.3 0
R1 82.5
or Twisted Pair R2
(eq. 18)
VTT VCC 2.0 V 3.0 V
VCC
*
VTT
VVCC
TT VEE
and cross−checking for VTT:
VEE
* T−Line Z0
* T−Line Z0
R1 R2
VTT = VCC − 2.0 V
Z0 = Characteristic Impedance of the Signal
Transmission Line
R1
Driver
(eq. 14)
For a typical VCC = 5.0 V PECL scheme, where VEE =
GND, VTT = 3.0 V, and Z0 = 50 :
Driver
R1
VEE
VVCC
CC VTT
Where:
VCC
T−Line Z0
R2 Z0
R2
(eq. 21)
and cross−checking for VTT:
*
VTT VCC 2.0V
R2
VCC
R1 R2
VEE
VTT 3.3
(eq. 13)
12682.5
1.3 V
82.5
VTT VCC 2.0 V 1.3 V
Figure 12. Thevenin Equivalent Parallel Termination
(eq. 22)
(eq. 23)
Table D. Thevenin Term Table
|VCC−VEE| = 5.0 V
Differential ECL outputs can be terminated as independent
complimentary single−ended lines. Both sides of a
differential pair must be terminated. Balanced, symmetrical
loading of each line must be preserved.
While a Thevenin Parallel technique dissipates more
termination power, it does not require the additional VTT
supply. This additional power is consumed entirely in the
external resistor divider network and thus will not change
the current being sourced by the device, hence it does not
alter the IC reliability or lifetime. As with standard parallel
termination, variance of VTT and VCC supplies must be
considered.
|VCC−VEE| = 2.5 V
Z0
R1
R2
Z0
R1
R2
Z0
R1
R2
50
83
125
50
127
83
50
250
62.5
70
117
175
70
178
115
70
350
87.5
75
125
188
75
190
123
75
375
93.8
80
133
200
80
203
132
80
400
100
90
150
225
90
229
149
90
450
112.5
100
167
250
100
253
165
100
500
125.5
120
200
300
120
305
198
120
600
150
150
250
375
150
381
248
150
750
187.5
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9
|VCC−VEE| = 3.3 V
AND8020/D
Thus:
Because the resistor divider network of R1 and R2 is used
to generate VTT, the variation in VTT will be intimately tied
to the variation in VCC. Differentiating the equation for VTT
with respect to VCC yields:
VTT
R2
VCC
VCC
( R1 R2 )
IOHmax = 23 mA
IOLmin = 3.0 mA
At +5% minimal variation case for VCC:
VCC = 5.25 V
VTT = 3.05 V
Thus:
IOHmax = 28 mA
IOLmin = 5.2 mA
(eq. 24)
For the nominal case, this equation reduces to:
VTT 0.6 VCC
(eq. 25)
If VCC = 5% = 0.25 V, then VTT = 0.15 V.
As mentioned previously, the real potential for problems
will be if the VOL level can potentially put the output emitter
follower out of the active operating region and into cutoff.
Because of the relationship between the VCC and VTT levels,
the only cutoff risk condition occurs at VCCmin, the lowest
value of VCC. Applying the equation for IOLmin under this
−5% VCC condition yields:
IOLmin IOLmin ( VOLmin VTT )
Rt
Although the output currents are slightly higher than
nominal, the elimination of emitter follower cutoff risk is
well justified.
When the equivalent termination resistance matches the
line impedance, no reflection occurs because all the energy
in the signal is dissipated by the termination. Hence, in
comparing properly terminated schemes parallel and
Thevenin, a primary consideration is the power supply
requirements. As mentioned earlier, the parallel VTT scheme
requires an extra power supply; however, the Thevenin
termination dissipates 10 times more DC power.
Fortunately, this extra power dissipation cannot be seen on
the die; therefore, either technique results in similar die
junction temperatures.
(eq. 26)
(4.75 1.85) 2.85
1.0 mA (eq. 27)
50
The results of this cutoff risk analysis show there is no
potential for the output emitter follower to be in cutoff. This
would indicate a Thevenin equivalent termination scheme is
more robust to variation in VCC. Since the designer has the
flexibility of choosing the VTT level via the selection of the
R1 and R2 resistors, the following procedure can be used.
At −5% minimal variation case for VCC:
VCC = 4.75 V
VTT = VCC − 2.0 V = 2.75 V
R2 = 119 R1 = 86 http://onsemi.com
10
AND8020/D
SECTION 4. SERIES TERMINATION
R
VO
A
B
R
R
R
*T−Line Z0
RO
Series Damping is a technique in which a termination
resistance is placed between the driver and the transmission
line with no termination resistance placed at the receiving
end of the line (Figure 13).
Driver
RS
* Optional
RS
Driver
VEE
Receiver
Figure 14. Series Termination
*T−Line Z0
Series termination techniques are useful when the
interconnect lengths are long or impedance discontinuities
exist on the line. Additionally, the signal travels down the
line at half amplitude minimizing problems associated with
crosstalk. Unfortunately, a drawback with this technique is
the possibility of a two−step signal appearing when the
driven inputs are far from the end of the transmission line.
To avoid this problem, the distance between the end of the
transmission line and input gates should adhere to the
guidelines specified from the section on unterminated lines.
*T−Line Z0
RS
Rt
or Twisted Pair
Rt
VEE
Driver
RS
* Optional
Receiver
*T−Line Z0
Series Termination Theory
When the output of the series terminated driver gate
switches levels, this driver output voltage change, VO, is
impressed on the input to the transmission line (Point A) as
a change in voltage (VA) and propagates to the Receiver at
the output of the transmission line (Point B) as a change in
voltage (VB) in Figure 14.
Rt
VEE
Figure 13. Series Termination
VA VO *
Differential ECL outputs can be terminated as
independent complimentary single−ended lines. Both sides
of any differential pair must be terminated as identically as
possible to minimize phase error and pulse width duty cycle
skew.
Series Termination is a special case of series damping in
which the sum of the termination resistor (RS) and the output
impedance of the Driver gate (RO) is equal to the line
characteristic impedance (Figure 14).
RS RO Z0
Receiver
Rt
R
Z0
S RO Z0
(eq. 29)
Where:
VA = Input to the Transmission Line Voltage
Change
VB = Receiver Input Voltage Change
VO = Driver Output Voltage Change
Z0 = Line Characteristic Impedance
RO = Output Impedance of the Driver Gate
RS = Termination Resistance
(eq. 28)
Where:
Since Z0 = RS + RO, substitution into the above equations
yields:
RS = Series Termination Resistor
RO = Output Impedance
Z0 = Line Characteristic Impedance
VA http://onsemi.com
11
VO
2
(eq. 30)
AND8020/D
From this relationship, VA = VO / 2, an incident wave
of half amplitude propagates down the transmission line. At
the Receivers input Point B, typically high impedance, the
transmission line sees an unterminated open line and the
signal reflection coefficient at the Receiver load is
approximately unity. The reflection causes the voltage to
double at the receiving end. When the reflected wave arrives
back at the source end, its energy is dissipated by the series
resistor. When the sum of the source and series impedance
is equal to the characteristic impedance of the line, no further
reflections occur.
An initial current, Iinit, must be sufficient to generate a
transient voltage equal to half of the logic swing since the
voltage at the receiver will double due the reflection
coefficient approaching 1.0 for series termination. To
accommodate reflections caused by discontinuities and load
capacitances the transient voltage should be increased by
25%. Thus, Iinit is defined as:
Iinit 1.25 * VSWING
( VOH VEE )
2
( Rt RS Z0 )
Z0
(eq. 33)
Solving for Rt, gives the inequality:
Rt ( KZ0 ) Z0 RS
(eq. 34)
Where:
Z0
RO
RS
KZ0
=
=
=
=
Line Characteristic Impedance
Output Impedance of the Driver Gate
Termination Resistance
Coefficient to Z0
For various series, the coefficient to Z0, KZ0, is presented
in Table E: Coefficient to Z0.
*T−Line Z0
RS
Driver
(eq. 32)
Z0
To satisfy the initial constraints of Imax > Iinit:
Calculation of Rt
The Emitter Pull−Down Resistor, Rt, functions to
establish VOH and VOL levels. Voltage transitions imposed
on Rt propagate through RS and Z0 to a receiver. Negative
voltage transition are current limited by Rt, RS, and Z0 when
the driver output switches to the low state. The Rt value must
maximize the negative voltage transition and prevent the
output transistor from entering the cutoff operating region in
a low state (Figure 15).
RO
1.25 * V2pp Table E. Coefficient to Z0
Receiver
Series
Rt
VEE
Figure 15. Equivalent Circuit for RE Determination
The worst case scenario occurs when the driver output
emitter follower enters into cutoff during a negative going
transition. When this happens, the driver can be considered
opened and, at the instant it opens, the line characteristic
impedance behaves as a linear resistor returned to VOH. The
model becomes a simple series resistive network as shown
in Figure 16.
KZ0
10EP
4.0
100LVEL
4.01
10EL
5.99
10E
7.10
100E
6.57
For the 10EP series (LVPECL mode operation),
where VOH = 2.4 V, VSWING = 0.8 V, and VEE = 0.0 V:
(2.4 0.0)
0.5
(Rt RS Z0)
Z0
(eq. 35)
4.0 * Z0 RS Rt
*T−Line Z0
For the 100LVEL series (LVPECL mode operation),
where: VOH = 2.345 V, VSWING = 0.750 V, VEE = 0.0 V:
RS
(2.345 0.0)
0.468
(Rt RS Z0)
Z0
VOH
Rt
(eq. 36)
4.01 * Z0 RS Rt
VEE
VEE
For the 10EL series (PECL mode operation),
where: VOH = 4.185 V, VSWING = 0.958 V, VEE = 0.0 V:
Figure 16. Equivalent Circuit with Output Cutoff
(4.185 0.0)
0.599
(Rt RS Z0)
Z0
The maximum current, Imax, occurs at the instant the
switch opens and is calculated by:
( VOH VEE )
I max ( Rt RS Z0 )
5.99 * Z0 RS Rt
(eq. 31)
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12
(eq. 37)
AND8020/D
For the 10E series (ECL mode operation),
where: VOH = −0.9 V, VSWING = 0.85 V, VEE = −5.2 V:
( 0.9) ( 5.2)
0.531
Rt Rs Z0
Z0
Where:
n = Number of Parallel Circuits
When:
Z01 Z02 Z0 n , and RS1 RS2 RS n (eq. 42)
(eq. 38)
Then Rt is calculated as:
7.10 * Z0 Rs Rt
Rt For the 100E series (ECL mode operation),
where: VOH = −0.955 V, VSWING = 0.75 V, VEE = −4.5 V:
( 0.955) ( 4.5)
0.468
Rt Rs Z 0
Z0
(eq. 39)
Parallel Fanout of Series Termination
An extension of the series termination technique, using
parallel fanout, eliminates the problem of lumped loading at
the expense of extra transmission lines (Figure 17).
NMloss IT * ( Rs RO )
(eq. 44)
Where:
IT = Sum of IINH Currents
RO = Output Impedance of the Driver Gate
RS = Termination Resistance
Receiver n
*T−Line Z0
N number of lines
Driver
(eq. 43)
When a single series terminated line is driving more than
a single receiver, the maximum number of loads must be
addressed. The factor limiting the number of loads is the DC
voltage drop across the series termination resistor caused by
the summary input currents IT during the receivers quiescent
high state. Noise margin loss, NMloss, will probably
determine the acceptable DC voltage drop limit across Rs.
6.57 * Z0 Rs Rt
RSn
(KZ0 * Z0 Rs)
n r
Driver
RS 1
IT
RS
*T−Line Z0
Receiver 1
*T−Line Z0
RO
Rt
Rt
Receiver 1
VEE
Receiver 2
VEE
Figure 17. Parallel Fanout Using Series Termination
Receiver N
Figure 17 shows a modification of the series termination
scheme in which several series terminated lines in parallel
fanout are driven using a single ECL gate. The principle
concern when applying this technique is to maintain the
current in the output emitter follower below the maximum
rated value. The value for Rt can be calculated by viewing
the circuit in terms of conductances.
Goutput G1 G2n G
Figure 18. Noise Margin Loss Example
For the majority of ECL devices typical maximum value
for quiescent high state input current is 150 uA. Thus, for the
circuit shown in Figure 18, in which three gate loads are
present in a 50 environment, the loss in high state noise
margin is calculated as:
(eq. 40)
From Table B, for each of the series:
NMloss 3 * 150 mA * 50 22.5 mV
1 1
( Rt )
( KZ0 * Z01 RS1)
1
( KZ0 * Z02 RS2)
1
( KZ0 * Z0n RS)
(eq. 45)
This represents a potential shift in the VOH level of
−22.5 mV.
(eq. 41)
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13
AND8020/D
SECTION 5. DIODE TERMINATION
VBB
Driver
D2
D1
*
Alternative to the resistor network termination schemes,
a Diode method shown in Figure 19 may afford certain
advantages when a design has the following constraints.
1. Impedance controlled media line is not required
(coax, twisted pair, striplines, etc.)
2. Impedance matched termination network is not
required.
3. Overshoot and Noise need to be clamped to logic
HIGH/LOW levels.
Receiver
*
*All Media
D1
D2
VBB
VBB
D1
Driver
D2
Receiver
*
*
*All Media
D1
D2
VBB
Driver
Receiver
*
*All Media
D1
D2
VBB
Figure 19. Diode Termination
D1 and D2 diodes may be an MBD301, MMBD301,
MBD701, MMBD701LT1, or a dual package MMBD452LT1.
Diode forward voltage curves from a data sheet, such as shown
in Figure 20, will determine specific current and voltage
operation range. Frequency limitations may be a consideration
when selecting the diodes. The Silicon Hot−Carrier Schottky
Barrier diode MBD701, for example, displays a forward Vf of
about 0.55 V and an If of about 11 mA (at 25°C) to match a
50 impedance line. At higher temperatures, the current
decreases.
IF, FORWARD CURRENT (mA)
100
TA =−40°C
TA = 85°C
10
TA = 25°C
1.0
0.1
0
0.2
0.4
0.8
1.2
1.6
VF, FORWARD VOLTAGE (V)
Figure 20. MMBD701 Diode Forward Voltage
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14
2.0
AND8020/D
SECTION 6. CAPACITIVE COUPLING
current. Typical driver signal levels present voltages that
forward bias the input ESD protection diode structure and
the input base collector junction. Potentially lethal current
paths may develop through forwarded junctions to VCC.
There is also a risk for a powered down or off NECL or
LVNECL receiver and driver. A VEE supply will typically
appear as a low impedance path to 0.0 V (GND). Typical
negative levels present signal voltages that will forward bias
the input ESD protection diode structure and the input base
collector junction to this low impedance path. Potentially
lethal current paths may develop through the forwarded
junctions and VEE to 0.0 V.
Powered down receiver risk may be managed in several
ways.
R
R
VBB
R
R
R
VCC
Although not strictly a termination, AC or capacitive
coupling is often used to provide features in conjunction
with proper termination. Such capabilities as hot swapping
capability, DC isolation to a receiver, and level shifting are
possible with capacitive coupling.
Data stream characteristics may impose restriction on
both termination and capacitive coupling. AC coupled
signals have the line DC blocked and will require a DC
restoration voltage, VBIAS, for the receiver input. Data in
unencoded Non−Return−to−Zero (NRZ) format will require
DC restoration prior to AC coupling into a ECL receiver
input.
A sinusoidal waveform clock signal may be cap coupled
for conversion to a square wave with 50% duty cycle and
sharp rise and fall edges.
The capacitor used to couple the signal must have a
impedance rating of < 50 over the frequency range of the
input signal. Because large capacitors appear somewhat
inductive at high frequencies, it may be necessary to use a
small capacitor in parallel with a larger one to achieve
satisfactory operation.
A coupling capacitor and the signal load impedance form
an RC network which will boundary the duration of a pulse.
Values for the R (load and leakage total resistance) and C
(coupling capacitor) should be selected to provide a time
constant, TC, of at least 10x the pulse width. Data streams
may require larger TC values to retain logic levels.
1. Physical Sequencing − the supplies for VEE
(Ground) and VCC (Power) may be physically
connected prior to signal lines by altering the
daughter board edge connection geometry, making
VEE and VCC connectors protrude and engage or
sequence first. VEE connectors could even be
sequenced prior to VCC. This insures the supplies
are powered prior to input signal voltages.
2. Switching − a relay (or analog switch) could be
used to open or close the supply lines insuring the
power supply line is opened when powered off.
3. Cap Coupling − DC isolation of potentially
damaging current.
4. Series R − an additional series impedance matching
resistor, RS, will act as power splitter with an
existing parallel termination resistor, RT, to
accomplish some current limiting to help manage
the risk. This will also attenuate the amplitude
50%, easily tolerated by most high gain, high input
sensitivity devices.
Hot Swapping
The desire often arises to remove or install a receiver or
daughter card without powering down the driver or
motherboard. This is termed “Hot Swapping”.
Using VBB Pin for VBIAS
Some devices provide a convenient VBB pin for use as a
VBIAS reference supply to rebias a DC level. A DC rebias
level must be at the common mode voltage of the input
signal to properly preserve a 50% output duty cycle (see
AND8066). A package VBB pin may provide an internally
generated DC switching reference voltage for the device
inputs, and is available only to the package input pins. Do not
port one package VBB pin directly to another device without
current amplification. When used, decouple VBB to VCC (or
VTT) via a 0.01 to 0.001 F capacitor to suppress noise
injection. Limit current to less than 0.5 mA (Absolute
Maximum Rating source or sink) as shown in Figure 21.
When not used, VBB should be left open.
Powered Driver and an Unpowered Receiver
Damage Risk
Hot swapping presents a potential risk to an unpowered or
powered down ECL device receiver and driver in either the
Negative or Positive mode when driven by a typical signal
level.
When a receiver PECL receiver VCC is off or powered
down, the VCC Power Supply typically appears as a low
impedance source at 0.0 V capable of sinking considerable
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15
AND8020/D
A. Differential
small signal gain, and feedback from the output to the input
through parasitic capacitive and inductive paths.
As a differential receiver input voltage diverges, the
output responds by transitioning toward a state voltage. A
sufficient voltage across the receiver inputs will force the
output to state level. Depending on conditions, about 10 to
50 mV is sufficient to suppress instability oscillation and
force a determined state on the output.
For the configuration using the VBB reference, Figure 21,
this input voltage may be accomplished by injecting a
minimum current from VCC through an external pullup
resistor, Rpu, on ONE input line. The value of Rpu could
range from 25 k to 100 k. As Rpu increases, the phase
error is diminished and the susceptibility to oscillation
increases.
Generally, an internal pull−down resistor ranging in value
from 52 k to 75 k is deployed on an input pin. On some
D−bar (Invert) input pins an additional 36 k to 75 k
resistor is deployed to suppress oscillation by forcing a
determined state on the output under open input or null
voltage conditions. A minimum input voltage of 20 to
30 mV may be effective depending on noise, gain, and
layout.
Generating VBB for VBIAS
When VBB voltages are desired, but not available within
a device, the reference level may be ported from a generator
as illustrated in Figure 22. Any of the “16” type buffers are
recommended for use in a high current gain VBB Generator
buffer. For example, the E416, EL16, LVEL16, EP16,
LVEP16, EL17, LVEL17, etc. type devices have a VBB pin
available for constructing a VBB Generator buffer.
VCC
Rpu 25 k to 100 k
Receiver
* 0.001 F
IN
OUT
INb
0.001 F
OUT
1 k
VBB
Rt
0.01 − 0.001 F
Rt
VTT
VCC or VTT
B. Single−Ended
VCC
* 0.001 F
Rpu 25 k to 100 k
Receiver
IN
OUT
OUT
1 k
VBB
0.01 − 0.001 F
Rt
Rt
VTT
VCC or VTT
* High Voltage Cap May Be Needed
Figure 21. Differential and Single−Ended AC
Configurations Using VBB Reference
In Figure 21A, the IN line has a 1 k resistor to VBB,
presenting a 1 K impedance across the differential signal
lines. This assumes the signal impedance matching has been
accomplished prior to the cap coupling, on the driver side of
cap. Locate the coupling capacitor as physically close to the
input pin as possible to minimize the trace length and
diminish potential reflections due to the impedance
mismatch.
If signal impedance matching has not been accomplished
prior to the cap coupling, then a characteristic impedance
resistor, 2Z0, would be used across the input lines, on the
receiver side of the cap. The value of the Rpu resistor would
be adjusted to produce an acceptable null signal default
voltage drop.
Auto−Oscillation Suppression with VBB
If the differential inputs to the AC coupled device are left
open or if the driving signals are lost, both receiver input pin
voltages converge toward the VBIAS reference voltage VBB
value. Sustained oscillation may autonomously result from
a combination of ambient environmental noise, the device
1 K
16
VBB(out)
VBB
RT
0.01 F
VTT
VCC or VTT
Figure 22. VBB Voltage Reference Generator
Non−VBB Biasing
Alternative to a device supplied VBB, any voltage source
may be supplied to bias receiver inputs to provide an
acceptable VIHCMR (Voltage Input HIGH Common Mode
Range) DC reference to the receiver (see specific device data
sheet). Signal impedance matching may be accomplished
prior to cap coupling, allowing a wide range values for a
rebiasing resistor network.
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16
AND8020/D
Single−Ended AC Configurations Using Non−VBB Biasing
(A and B). This network total resistance may be from 1 K
to 10 K. For 50 impedance traces, the typical value for the
voltage divider resistors are given in Table F. Typical Rebias
and Impedance Matching Resistor Network Values @
Z0 = 50. Note the impedance presented to a signal is 5 K
When the coupling capacitor is physically located near
enough to the receiver input pins to prohibit reflections on the
connecting trace length or signal impedance matching has
been accomplished prior to cap coupling, then a simple high
value resistor divider network from VCC to VEE is
recommended as shown in Figure 23. Differential and
Table F. Typical Rebias and Impedance Matching Resistor Network Values @ Z0 = 50
Resistor
|VCC−VEE| = 5.0 V
|VCC−VEE| = 3.3 V
|VCC−VEE| = 2.5 V
Units
R1 (R1′)
4
4
4
K
R2 (R2′)
6
6
6
K
Vrebias
3.3
2.2
1.7
V
When the coupling capacitor is physically located at a
distance from receiver over a trace or cable length capable
of sustaining reflections, a Thevenin parallel network
matching the line of impedance is recommended for their
suppression. This is shown in Figure 23. Differential and
Single−Ended AC Configurations Using Non−VBB Biasing
(A and B). The rebias voltage may always be safely set at
VCC−1.3. For 50 impedance traces, the typical value for
the voltage divider resistors are given in Table G. Typical
Rebias and Impedance Matching Resistor Network Values @
Z0 = 50.
Table G. Typical Rebias and Impedance Matching Resistor Network Values @ Z0 = 50
Resistor
|VCC−VEE| = 5.0 V
|VCC−VEE| = 3.3 V
|VCC−VEE| = 2.5 V
Units
R1 (R1′)
68
83
96.15
R2 (R2′)
192
127
104.16
Vrebias
3.7
2.0
1.2
V
A. Differential
The characterized VBB reference voltage bias, VBIAS, is
VCC − 1.33 V, but a device is not restricted to this VBIAS
value. The VBIAS range is determined by the Vpp
amplitude and the signal HIGH level, VIH. Input HIGH
level, VIH, is constrained by the data sheet specification of
common mode range, VIHCMR or VCMR. Thus, the VBIAS
range is constrained:
VCC
0.001 F
R1
R1
Receiver
IN
OUT
INb
OUTb
0.001 F
R2
R2
Rt
VEE
VBIAS max VIHCMRmax ( 0.5 ) ( Vpp )
VBIAS min VIHCMRmin ( 0.5 ) ( Vpp )
Rt
A single−ended source into a differential type input signal
amplitude swing, Vpp, is typically constrained from
Vppmin = 300 mV to Vppmax = 1000 mV.
An input signal must swing symmetrically above and
below VBIAS to preserve a 50% duty cycle out of the
receiver. Differential signals must have identical crosspoint
voltages to preserve minimum phase error and duty cycle
error. Crosspoint voltages are determined by the matched
precision of the resistor divider network from VCC to VEE.
VTT
B. Single−Ended
VCC
0.001 F
R1
R1
Receiver
IN
OUT
Auto−Oscillation Suppression without VBB
For a configuration without a VBB reference pin, such as
illustrated in Figure 23, the resistor network may be
modified to have an input voltage of 20 to 30 mV offset
between the input pins. Either a high resistor value divider
or a Thevenin parallel network may be modified to
accomplish this input voltage . This is accomplished by
altering the values of R1, R1′, R2, and R2′.
OUTb
R2
R2
VEE
Rt
Rt
VTT
Figure 23. Differential and Single−Ended AC
Configurations Using Non−VBB Biasing
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17
AND8020/D
Combining the high impedance and impedance matching
networks results in an input voltage scheme shown in
Figure 24. This creates the proper input voltage , VBIAS,
using fewer components.
The 0.001 coupling cap may need to be adjusted to
frequency and Vpp amplitude of the receiver input signal.
A similar single−ended network may be used with only
one coupling cap and sufficient bypass capacitance on the
non−driven resistor to preserve a DC level.
VCC
Output Level Shifting
Receiver inputs may be level shifted using capacitive
coupling and adjusting VBIAS within the acceptable
common mode range for VIH. Output levels may also be
changed independent of input levels. The driver device may
be operated with both VCC and VEE at shifted values. This
is used at the factory to evaluate devices and conveniently
port signals directly into standard 50 impedance
equipment modules. The VCC is fixed to +2.0 V above Test
System chassis ground and the test equipment internal 50
impedance constitutes a proper signal termination. Thus, the
split VEE supply is adjusted to a negative value.
R1
0.001 F
Receiver
IN
OUT
RZ
OUTb
INb
0.001 F
R2
VEE
Rt
Rt
VTT
Figure 24. VBIAS and Auto−Oscillation Suppression
with Thevenin Parallel Network
For a 3.3 V VCC, the values of R1 and R2 provide a
Thevenin parallel network divider voltage with VIH in the
VIHCMR of the receiver. Current through the divider
develops the default offset across Rz and can be adjusted as
needed. For example, in Z0 = 50 traces, a 30 mV default
offset difference will be created if VCC = 3.3 V and the DC
bias voltage is 2.0 V (typical VBB) when:
|VCC − VEE|
Split VCC
Split VEE
Unit
3.0
+2.0
−1.0
V
3.3
+2.0
−1.3
V
5.0
+2.0
−3.0
V
5.5
+2.0
−3.5
V
Output levels may be shifted to symmetrically cross 0.0 V
by a similar method although the advantage of conveniently
directly connecting into standard test equipment is no longer
available.
R1 4.22 k
R2 6.34 k
RZ 100 ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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