AD ADP3308ART-27

a
FEATURES
ⴞ1.2% Accuracy Over Line and Load Regulations
@ 25ⴗC
Ultralow Dropout Voltage: 80 mV Typical @ 50 mA
Requires Only CO = 0.47 ␮F for Stability
anyCAP = Stable with All Types of Capacitors
(Including MLCC)
Current and Thermal Limiting
Low Noise
Low Shutdown Current: 1 ␮A
3.0 V to 12 V Supply Range
–20ⴗC to +85ⴗC Ambient Temperature Range
Several Fixed Voltage Options
Ultrasmall SOT-23-5 Package
Excellent Line and Load Regulations
anyCAP™ 50 mA
Low Dropout Linear Regulator
ADP3308
FUNCTIONAL BLOCK DIAGRAM
Q1
IN
OUT
ADP3308
THERMAL
PROTECTION
ERR/NC
Q2
R1
CC
DRIVER
Gm
R2
SD
BANDGAP
REF
GND
APPLICATIONS
Cellular Telephones
Notebook, Palmtop Computers
Battery Powered Systems
PCMCIA Regulator
Bar Code Scanners
Camcorders, Cameras
GENERAL DESCRIPTION
The ADP3308 is a member of the ADP330x family of precision
low dropout anyCAP voltage regulators. It is pin-for-pin and
functionally compatible with National’s LP2980, but offers
performance advantages. The ADP3308 stands out from the
conventional LDOs with a novel architecture and an enhanced
process. Its patented design requires only a 0.47 µF output
capacitor for stability. This device is stable with any type of
capacitor regardless of its ESR (Equivalent Serial Resistance)
value, including ceramic types for space restricted applications.
The ADP3308 achieves ± 1.2% accuracy at room temperature
and ± 2.2% overall accuracy over temperature, line and load
regulations. The dropout voltage of the ADP3308 is only
80 mV (typical) at 50 mA. This device also includes a current
limit and a shutdown feature. In shutdown mode, the ground
current is reduced to ~1 µA.
ERR/NC 4
ADP3308-3.3
1 IN
VIN
OUT 5
VOUT = +3.3V
C2
0.47mF
C1
0.47mF
3
2
ON
OFF
SD
GND
Figure 1. Typical Application Circuit
The ADP3308 operates with a wide input voltage range from
3.0 V to 12 V and delivers a load current in excess of 100 mA.
The ADP3308 anyCAP LDO offers a wide range of output
voltages. For 100 mA version, refer to the ADP3309 data sheet.
anyCAP is a trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
(@TA = –20ⴗC to +85ⴗC, VIN = 7 V, CIN = 0.47 ␮F, COUT = 0.47 ␮F, unless
ADP3308-xx–SPECIFICATIONS otherwise noted.) The following specifications apply to all voltage options.
1
Parameter
Symbol
Conditions
Min
OUTPUT VOLTAGE ACCURACY
VOUT
VIN = VOUTNOM + 0.3 V to 12 V
IL = 0.1 mA to 50 mA
TA = +25°C
VIN = VOUTNOM + 0.3 V to 12 V
IL = 0.1 mA to 50 mA
Typ
Max
Units
–1.2
+1.2
%
–2.2
+2.2
%
∆V O
∆V IN
VIN = VOUTNOM + 0.3 V to 12 V
TA = +25°C
0.02
mV/V
∆V O
∆ IL
IL = 0.1 mA to 50 mA
TA = +25°C
0.06
mV/mA
GROUND CURRENT
IGND
IL = 50 mA
IL = 0.1 mA
0.54
0.19
1.4
0.3
mA
mA
GROUND CURRENT IN DROPOUT
IGND
VIN = 2.4 V
IL = 0.1 mA
0.9
1.7
mA
VOUT = 98% of VOUTNOM
IL = 50 mA
IL = 10 mA
IL = 1 mA
0.08
0.025
0.004
0.17
0.07
0.030
V
V
V
0.75
0.75
0.3
V
V
1
9
µA
µA
0.005
1
µA
0.01
3
µA
2
4
µA
µA
13
µA
0.3
V
LINE REGULATION
LOAD REGULATION
DROPOUT VOLTAGE
SHUTDOWN THRESHOLD
SHUTDOWN PIN INPUT CURRENT
VDROP
VTHSD
ISDIN
GROUND CURRENT IN SHUTDOWN IQ
MODE
ON
OFF
2.0
0 < VSD ≤ 5 V
5 < VSD ≤ 12 V @ VIN = 12 V
VSD = 0 V, VIN = 12 V
TA = +25°C
VSD = 0 V, VIN = 12 V
TA = +85°C
TA = +25°C @ VIN = 12 V
TA = +85°C @ VIN = 12 V
OUTPUT CURRENT IN SHUTDOWN
MODE
IOSD
ERROR PIN OUTPUT LEAKAGE
IEL
ERROR PIN OUTPUT
“LOW” VOLTAGE
VEOL
ISINK = 400 µA
0.12
PEAK LOAD CURRENT
ILDPK
VIN = VOUTNOM + 1 V, TA = +25°C
150
mA
OUTPUT NOISE @ 5 V OUTPUT
VNOISE
f = 10 Hz–100 kHz
100
µV rms
NOTES
1
Ambient temperature of +85°C corresponds to a junction temperature of +125°C under typical full load test conditions.
Specifications subject to change without notice.
–2–
REV. A
ADP3308
ABSOLUTE MAXIMUM RATINGS*
PIN FUNCTION DESCRIPTIONS
Input Supply Voltage . . . . . . . . . . . . . . . . . . . –0.3 V to +16 V
Shutdown Input Voltage . . . . . . . . . . . . . . . . –0.3 V to +16 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . Internally Limited
Operating Ambient Temperature Range . . . –55°C to +125°C
Operating Junction Temperature Range . . . –55°C to +125°C
θJA␣ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165°C/W
θJC␣ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged.
ORDERING GUIDE
Model
Voltage
Output
Package
Option*
Marking
Code
ADP3308ART-2.7
ADP3308ART-2.85
ADP3308ART-2.9
ADP3308ART-3
ADP3308ART-3.3
ADP3308ART-3.6
2.7 V
2.85 V
2.9 V
3.0 V
3.3 V
3.6 V
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DAC
DJC
DKC
DCC
DEC
DFC
Pin Name
Function
1
2
3
IN
GND
SD
4
ERR/NC
5
OUT
Regulator Input.
Ground Pin.
Active Low Shutdown Pin. Connect to
ground to disable the regulator output.
When shutdown is not used, this pin
should be connected to the input pin.
Open Collector. Output that goes low
to indicate the output is about to go out
of regulation or no connect.
Output of the Regulator, fixed 2.7, 2.85,
2.9, 3.0, 3.3, or 3.6 volts output voltage.
Bypass to ground with a 0.47 µF or larger
capacitor.
PIN CONFIGURATION
IN
1
GND 2
SD
5 OUT
ADP3308
TOP VIEW
3 (Not to Scale) 4 ERR/NC
NC = NO CONNECT
*SOT = Surface Mount.
Contact the factory for the availability of other output voltage options.
Other Member of anyCAP Family 1
Model
Output Current
Package Option2
ADP3309
100 mA
SOT-23-5 Lead
NOTES
1
See individual data sheet for detailed ordering information.
2
SOT = Surface Mount.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3308 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. A
–3–
WARNING!
ESD SENSITIVE DEVICE
ADP3308–Typical Performance Characteristics
3.302
3.302
1150
I L = 0mA
OUTPUT VOLTAGE – Volts
OUTPUT VOLTAGE – Volts
I L = 10mA
3.300
3.299
VOUT = 3.3V
3.298
I L = 50mA
3.297
GROUND CURRENT – mA
3.301
3.301
VOUT = 3.3V
I L = 0mA
VOUT = 3.3V
VIN = 7V
3.300
3.299
3.298
3.297
3.296
3.296
3.295
3.3 4
3.295
5
0
6 7 8 9 10 11 12 13 14
INPUT VOLTAGE – Volts
Figure 2. Line Regulation: Output
Voltage vs. Supply Voltage
8
800
650
400
160
0
16 24 32 40 48 56 64 72 80
OUTPUT LOAD – mA
Figure 3. Output Voltage vs. Load
Current
900
0
1.2 2.4 3.6 4.8 6.0 7.2 8.4 9.6 10.8 12.0
INPUT VOLTAGE – Volts
Figure 4. Quiescent Current vs.
Supply Voltage
0.2
700
0.1
600
550
425
IL = 0 TO 80mA
300
–0.2
I L = 50mA
0
20
40
60
OUTPUT LOAD – mA
80
Figure 6. Output Voltage Variation %
vs. Temperature
INPUT/OUTPUT VOLTAGE – Volts
72
48
24
0
20
40
60
OUTPUT LOAD – mA
80
Figure 8. Dropout Voltage vs. Output
Current
300
IL = 0mA
200
15 35 55 75 95 115 135
TEMPERATURE – 8C
Figure 7. Quiescent Current vs.
Temperature
8.0
VOUT = 3.3V
RL = 66V
4
3
2
1
0
400
0
–45 –25 –5
15 35 55 75 95 115 135
TEMPERATURE – 8C
5
96
IL = 50mA
500
100
–0.4
–45 –25 –5
120
INPUT/OUTPUT VOLTAGE – mV
I L = 30mA
–0.1
–0.3
Figure 5. Quiescent Current vs. Load
Current
0
I L = 0mA
0.0
INPUT/OUTPUT VOLTAGE – Volts
175
GROUND CURRENT – mA
675
OUTPUT VOLTAGE – %
GROUND CURRENT – mA
VIN = 7V
0
1
3
2
4
3
2
INPUT VOLTAGE – Volts
1
0
Figure 9. Power-Up/Power-Down
–4–
VIN
7.0
6.0
5.0
4.0
VOUT
3.0
2.0
1.0
0
0
VSD = VIN
CL = 0.47mF
RL = 66V
VOUT = 3.3V
20 40 60 80 100 120 140 160 180 200
TIME – ms
Figure 10. Power-Up Overshoot
REV. A
ADP3308
3.320
VOUT = 3.3V
3.310
3.300
3.290
Volts
RL = 3.3kV
CL = 0.47mF
3.280
VIN
7.5
7.0
7.0
0
40 80 120 160 200 240 280 320 360 400
TIME – ms
Figure 11. Line Transient Response
VOUT = 3.3V
CL = 4.7mF
Volts
3.310
VIN
20 40 60 80 100 120 140 160 180 200
TIME – ms
0
Figure 12. Line Transient Response
VOUT = 3.3V
3.3
200
300
TIME – ms
400
VOUT
CL = 0.47mF
3
3.3V
3.300
2
CL = 4.7mF
Volts
3.290
150
mA
3.280
IOUT
10
0
100
200
300
TIME – ms
400
IOUT
100
0
+3
0
0
0
500
1
2
3
TIME – ms
0
4
VOUT = 3.3V
RL = 66V
CL = 0.47mF
–10
RIPPLE REJECTION – dB
3
2
1
0
3
VSD
0
5
–20
–30
VOUT = +3.3V
a. 0.47mF, RL = 3.3kV
b. 0.47mF, RL = 66V
c. 4.7mF, RL = 3.3kV
d. 4.7mF, RL = 66V
b
–40
–50
d
a
–60
–70
c
b d
–80
–90
0
20
40
60
TIME – ms
Figure 17. Turn Off
REV. A
80
VSD
+3V
0
Figure 15. Short Circuit Current
Figure 14. Load Transient
3.3V
4
VOUT = 3.3V
RL = 66V
1
50
100
–100
10
a c
100
1k
10k 100k
FREQUENCY – Hz
1M
10M
Figure 18. Power Supply Ripple
Rejection
–5–
20
40
60
TIME – ms
80
100
Figure 16. Turn On
VOLTAGE NOISE SPECTRAL DENSITY – mV/ Hz
100
Volts
500
4
VOUT
0
100
Figure 13. Load Transient
200
mA
IOUT
100
10
0
Volts
3.320
3.280
mA
7.5
3.300
3.290
3.290
RL = 66V
CL = 0.47mF
3.280
VOUT = 3.3V
CL = 0.47mF
3.310
Volts
3.300
Volts
3.320
3.320
VOUT = 3.3V
3.310
10
VOUT = 3.3V
CL = 0.47mF
IL = 1mA
1
0.1
0.01
100
1k
10k
FREQUENCY – Hz
100k
Figure 19. Output Noise Density
ADP3308
cellent line and load regulation. An impressive ± 2.2% accuracy
is guaranteed over line, load and temperature.
THEORY OF OPERATION
The new anyCAP LDO ADP3308 uses a single control loop for
regulation and reference functions. The output voltage is sensed
by a resistive voltage divider consisting of R1 and R2, which is
varied to provide the available output voltage option. Feedback
is taken from this network by way of a series diode (D1) and a
second resistor divider (R3 and R4) to the input of an amplifier.
Additional features of the circuit include current limit and thermal shutdown. Compared to the standard solutions that give
warning after the output has lost regulation, the ADP3308 provides improved system performance by enabling the ERR pin to
give warning before the device loses regulation.
As the chip’s temperature rises above +165°C, the circuit activates a soft thermal shutdown, indicated by a signal low on the
ERR pin, to reduce the current to a safe level.
OUTPUT
INPUT
COMPENSATION
CAPACITOR
ATTENUATION
(VBANDGAP /VOUT)
Q1
NONINVERTING
WIDEBAND
DRIVER
Gm
R3
PTAT
VOS
R1
RLOAD
D1
APPLICATION INFORMATION
Capacitor Selection: anyCAP
(a)
R4
PTAT
CURRENT
R2
ADP3308
Output Capacitors: as with any micropower device, output
transient response is a function of the output capacitance. The
ADP3308 is stable with a wide range of capacitor values, types
and ESR (anyCAP). A capacitor as low as 0.47 µF is all that is
needed for stability. However, larger capacitors can be used if
high output current surges are anticipated. The ADP3308 is
stable with extremely low ESR capacitors (ESR ≈ 0), such as
multilayer ceramic capacitors (MLCC) or OSCON.
CLOAD
GND
Figure 20.␣ Functional Block Diagram
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that at equilibrium it
produces a large, temperature proportional input “offset voltage” that is repeatable and very well controlled. The temperature proportional offset voltage is combined with the
complementary diode voltage to form a “virtual bandgap” voltage, implicit in the network, although it never appears explicitly
in the circuit. Ultimately, this patented design makes it possible
to control the loop with only one amplifier. This technique also
improves the noise characteristics of the amplifier by providing
more flexibility on the tradeoff of noise sources that leads to a
low noise design.
Input Bypass Capacitor: an input bypass capacitor is not required. However, for applications where the input source is high
impedance or far from the input pin, a bypass capacitor is recommended. Connecting a 0.47 µF capacitor from the input pin
(Pin 1) to ground reduces the circuit’s sensitivity to PC board
layout. If a bigger output capacitor is used, the input capacitor
must be 1 µF minimum.
Thermal Overload Protection
The ADP3308 is protected against damage due to excessive
power dissipation by its thermal overload protection circuit
which limits the die temperature to a maximum of +165°C.
Under extreme conditions (i.e., high ambient temperature and
power dissipation) where die temperature starts to rise above
+165°C, the output current is reduced until the die temperature
has dropped to a safe level. The output current is restored when
the die temperature is reduced.
The R1, R2 divider is chosen in the same ratio as the bandgap
voltage to the output voltage. Although the R1, R2 resistor
divider is loaded by the diode D1 and a second divider consisting of R3 and R4, the values can be chosen to produce a temperature stable output. This unique arrangement specifically
corrects for the loading of the divider so that the error resulting
from base current loading in conventional circuits is avoided.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, device power dissipation should be externally limited
so that junction temperatures will not exceed +125°C.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to
include the load capacitor in a pole splitting arrangement to
achieve reduced sensitivity to the value, type and ESR of the
load capacitance.
Calculating Junction Temperature
Device power dissipation is calculated as follows:
PD = (VIN – VOUT) ILOAD + (VIN) IGND
Most LDOs place very strict requirements on the range of ESR
values for the output capacitor because they are difficult to
stabilize due to the uncertainty of load capacitance and resistance. Moreover, the ESR value required to keep conventional
LDOs stable, changes, depending on load and temperature.
These ESR limitations make designing with LDOs more difficult because of their unclear specifications and extreme variations over temperature.
Where ILOAD and IGND are load current and ground current, VIN
and VOUT are input and output voltages respectively.
Assuming ILOAD = 50 mA, IGND = 2 mA, VIN = 5.5 V and
VOUT = 2.7 V, device power dissipation is:
PD = (5.5 – 2.7) 50 mA + 5.5 × 2 mA = 151 mW
∆T = TJ – TA = PD × θJA = 151 × 165 = 24.9°C
With a maximum junction temperature of +125°C, this yields a
maximum ambient temperature of ~100°C.
This is no longer true with the ADP3308 anyCAP LDO. It can
be used with virtually any capacitor, with no constraint on the
minimum ESR. This innovative design allows the circuit to be
stable with just a small 0.47 µF capacitor on the output. Additional advantages of the design scheme include superior line
noise rejection and very high regulator gain which leads to ex-
Printed Circuit Board Layout Consideration
Surface mount components rely on the conductive traces or
pads to transfer heat away from the device. Appropriate PC
board layout techniques should be used to remove heat from the
immediate vicinity of the package.
–6–
REV. A
ADP3308
Higher Output Current
The following general guidelines will be helpful when designing
a board layout:
The ADP3308 can source up to 50 mA without any heatsink or
pass transistor. If higher current is needed, an appropriate pass
transistor can be used, as in Figure 22, to increase the output
current to 1 A.
1. PC board traces with larger cross section areas will remove
more heat. For optimum results, use PC boards with thicker
copper and or wider traces.
2. Increase the surface area exposed to open air so heat can be
removed by convection or forced air flow.
MJE253*
VIN = 4V TO 8V
C1
47mF
VOUT = 3.0V @ 1A
R1
50V
3. Do not use solder mask or silk screen on the heat dissipating
traces because it will increase the junction to ambient
thermal resistance of the package.
IN
OUT
C2
10mF
ADP3308-3.0
Shutdown Mode
Applying a TTL high signal to the shutdown pin or tying it to
the input pin will turn the output ON. Pulling the shutdown pin
down to a TTL low signal or tying it to ground will turn the
output OFF. In shutdown mode, quiescent current is reduced
to less than 1 µA.
SD
GND
*AAVID531002 HEAT SINK IS USED
Figure 22. Higher Output Current Linear Regulator␣
Constant Dropout Post Regulator
APPLICATION CIRCUITS
Crossover Switch
The circuit in Figure 23 provides high precision with low dropout for any regulated output voltage. It significantly reduces the
ripple from a switching regulator while providing a constant
dropout voltage, which limits the power dissipation of the LDO
to 30 mW. The ADP3000 used in this circuit is a switching
regulator in the step-up configuration.
The circuit in Figure 21 shows that two ADP3308s can be used
to form a mixed supply voltage system. The output switches
between two different levels selected by an external digital input.
Output voltages can be any combination of voltages from the
Ordering Guide of the data sheet.
VIN = 4V TO 12V
VOUT = 3.0V/3.3V
OUT
IN
ADP3308-3.0
SD
OUTPUT SELECT
4V
0V
GND
IN
C1
1.0mF
OUT
C2
0.47mF
ADP3308-3.3
SD
GND
Figure 21. Crossover Switch
L1
6.8mH
VIN = 2.5V TO 3.5V
D1
1N5817
ADP3308-3.0
OUT
IN
C1
100mF
10V
R1
120V
ILIM
C2
100mF
10V
VIN
SW1
ADP3000-ADJ
R2
30.1kV
1%
SD
[email protected]
GND
Q1
2N3906
C3
2.2mF
Q2
2N3906
FB
GND
R3
124kV
1%
SW2
Figure 23. Constant Dropout Post Regulator
REV. A
–7–
R4
274kV
ADP3308
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
5-Lead Surface Mount Package
(SOT-23)
0.071 (1.80)
0.059 (1.50)
5
1
4
2
3
C3246a–2–9/98
0.122 (3.10)
0.106 (2.70)
0.118 (3.00)
0.098 (2.50)
PIN 1
0.0374 (0.95) REF
0.075 (1.90)
REF
0.051 (1.30)
0.035 (0.90)
0.020 (0.50)
0.010 (0.25)
SEATING
PLANE
108
08
0.009 (0.23)
0.003 (0.08)
0.022 (0.55)
0.014 (0.35)
PRINTED IN U.S.A.
0.006 (0.15)
0.000 (0.00)
0.057 (1.45)
0.035 (0.90)
–8–
REV. A