fax id: 5603 CY7C960 CY7C961 Low Cost VMEbus Interface Controller Family Features Functional Description • 80-Mbyte-per-second block transfer rates • All VME64 transactions provided, including A64/D64, A40/MD32 transfers • Auto Slot ID • CR/CSR space • All standard (Rev C) VMEbus transactions implemented • VMEbus Interrupter • No local CPU required • Programmable from VMEbus, serial PROM, or local bus • DRAM controller, including refresh • On-chip DMA controller • Local I/O controller • Flexible VMEbus address scheme • User-configured VMEbus response • 64-pin TQFP, 10x10mm (CY7C960) • 100-pin TQFP, 14x14mm (CY7C961) The CY7C960 Slave VMEbus Interface Controller provides the board designer with an integrated, full-featured VME64 interface. This 64-pin device can be programmed to handle every transaction defined in the VME64 specification. The CY7C961 is based upon the CY7C960: additional features include Remote Master capability whereby the CY7C961 can be commanded to move data as a VMEbus master. The CY7C961 is packaged in a 100-pin outline. The CY7C960 contains all the circuitry needed to control large DRAM arrays and local I/O circuitry without the intervention of a local CPU. There are no registers to read or write, no complex command blocks to be constructed in memory. The CY7C960 simply fetches its own configuration parameters during the power-on reset period. After reset the CY7C960 responds appropriately to VMEbus activity and controls local circuitry transparently. D64 STROBE DENO* DENIN* DENIN1* LADI LAEN LEDI LEDO ABEN* LDS CY7C960 Logic Block Diagram REGION [3:0] AM [5:0] SYSRESET* REGION/ AM TABLE POWER-ON RESET GENERATOR VME CONTROL INTERFACE VME INTERRUPT INTERFACE DRAM CONTROLLER RAS* CAS* ROW COL REFRESH CONTROLLER LIRQ* IRQ* IACK* IACKIN* IACKOUT* CHIP SELECT OUTPUT PATTERN TABLE TIMING GENERATOR CLK AS* DS0* DS1* DTACK* WRITE* LOCAL ADDRESS CONTROLLER CY7C964 CONTROLLER Cypress Semiconductor Corporation • DATABYTE LANE DECODER 3901 North First Street DATA BYTE ENABLE CONTROLLER LOCAL CONTROL CIRCUIT LA [7:1] L WORD CS[5:0] DBE [3:0] LACK* LDEN* PREN* SWDEN* R/W c960–1 • San Jose • CA 95134 • 408-943-2600 December 1994 – Revised December 4, 1997 CY7C960 CY7C961 D64 STROBE DENO* DENIN* DENIN1* LADI LAEN LEDI LEDO ABEN* LDS MWB* BLT LADO FC1 LAEN321 VMECNT CY7C961 Logic Block Diagram REGION [3:0] SELECTLM AM[5:0] SYSRESET* CY7C964 CONTROLLER REGION/ AMTABLE POWER-ON RESET GENERATOR LOCAL ADDRESS CONTROLLER LA [7:1] DMA CHANNEL REGISTERS LD [7:0] CHIP SELECT OUTPUT PATTERN TABLE CS [5:0] TIMING GENERATOR CLK AS* DS0* DS1* DTACK* WRITE* BR* BBSY* BERR* BGIN* BGOUT* VME CONTROL INTERFACE DMA CONTROLLER DATA BYTE ENABLE DATABYTE CONTROLLER LANE DECODER REFRESH CONTROLLER IRQ* IACK* IACKIN* IACKOUT* VME INTERRUPT INTERFACE LOCK CONTROLLER DRAM CONTROLLER LOCAL CONTROL CIRCUIT LIRQ* RAS* CAS* ROW COL c960–2 CY7C960 Pin Configuration AM0 VCC DBE1 DBE2 DBE3 R/W DBE0 COL/CS3 AM1 GND CAS*/CS5 AM2 ROW/CS2 PREN* SWDEN* RAS*/CS4 TQFP Top View 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 LA7 LA6 LA5 LA4 IRQ* LA3 GND AM5 LA2 VCC LA1 DS1* LWORD LDS DENIN1* LAEN 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 2728 29 30 31 32 ABEN* DTACK* GND DS0* VCC SYSRESET* D64 LEDO LEDI LADI STROBE c960–3 DENO* IACKOUT* IACKIN* IACK* AS* LACK* LIRQ* LDEN* CS0 CS1 AM3 REGION3/CS2 AM4 VCC GND REGION2 CLK WRITE* REGION1 REGION0 DENIN* LWORD 2 DBE [3:0] LACK* LBERR* LDEN* PREN* SWDEN* R/W CY7C960 CY7C961 DBE2 DBE3 R/W AM0 NC VCC LD6 DBE1 GND GND BR* DBE0 LD5 COL/CS3 AM1 ROW/CS2 NC AM2 NC TQFP Top View LD3 CAS*/CS5 LD4 PREN* SWDEN* RAS*/CS4 CY7C961 Pin Configuration 10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 LACK* LIRQ* LDEN* LD1 CS0 VCC LD2 CS1 NC AM3 REGION3/CS2 AM4 VCC BERR* GND VMECNT REGION2 LD0 CLK NC WRITE* NC REGION1 REGION0 DENIN* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LA7 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 LA6 LA5 LD7 LA4 SELECTLM* LBERR* IRQ* NC LA3 LAEN321 GND AM5 LA2 BBSY* VCC LA1 58 57 56 55 54 53 52 51 NC DS1* NC LWORD FC1 LDS DENIN1* LAEN 26 27 28 29 30 31 32 33 34 35 3637 38 39 40 41 42 43 44 4546 47 48 49 50 LEDI DS0* NC VCC BLT SYSRESET* LADO D64 LEDO AS* NC LADI STROBE BGIN* ABEN* DTACK* GND NC MWB* NC DENO* IACKOUT* IACKIN* BGOUT* IACK* c960–4 panion device, CY7C964: all control sequences for the part are generated automatically by the CY7C960 in response to VMEbus or local activity. If more information is desired, consult the CY7C964 chapter in the VIC64 Design Notes (available separately). Functional Description (continued) The CY7C960 controls a bridge between the VMEbus and local DRAM and I/O. Once programmed, the CY7C960 provides activities such as DRAM refresh and local I/O handshaking in a manner that requires no additional local circuitry. The VMEbus control signals are connected directly to the CY7C960. The VMEbus address and data signals are connected to companion address/data transceivers which are controlled by the CY7C960. The CY7C964 VMEbus Interface Logic Circuit is an ideal companion device: the CY7C964 provides a slice of data and address logic that has been optimized for VME64 transactions. In addition to providing the specified drive strength and timing for VME64 transactions, the CY7C964 contains all the circuitry needed to multiplex the address/data bus for multiplexed VMEbus transactions. It contains counters and latches needed during BLT operations; and it also contains address comparators which can be used in the board’s Slave Address Decoder. For a 6U or 9U application, four CY7C964 devices are controlled by a single CY7C960. For 3U applications, the CY7C960 controls two CY7C964 devices and an address latch. VMEbus transactions supported by the CY7C960 include D8, D16, D32 (incl. UAT), MD32, D64, A16, A24, A32, A40, A64 single-cycle and block-transfer reads and writes, Read-Modify-Write cycles (incl. multiplexed), and Address-only (with or without Handshake). The CY7C960 functions as a VMEbus Interrupter, and supports the new Auto Slot ID standard and CR/CSR space. The CY7C960 also handles LOCK cycles, although full LOCK support is not possible within the constraints of the CY7C960 pinout. Full LOCK support is provided by the CY7C961. On the local side, no CPU is needed to program the CY7C960, nor to manage transactions. All programmable parameters are initialized through the use of either the VMEbus, a serial PROM, or some other local circuit. As the CY7C960 incorporates a reliable power-on reset circuit, parameters are self-loaded by the device at power-up or after a system reset. If the VMEbus is used to provide parameters, a VMEbus Master provides the programming information using a protocol, described in the User’s Guide, which is compliant with the Auto Slot ID protocol from the new VME64 specification. The design of the CY7C960 makes it unnecessary to know the details of the VMEbus transaction timing and protocol. The complex VMEbus activities are translated by CY7C960 to simple local cycles involving a few familiar control signals. Similarly, it is not necessary to understand the operation of the com- 3 CY7C960 CY7C961 The CY7C961 master block facility provides “block transfer on demand” capability for slave cards built around the Cypress CY7C961/CY7C964 chipset. This facility allows one or many VMEbus masters to write short series of commands to the slave card, telling it how much data to move, where to get it from, where to put it, and what transfer protocol to use while moving it. Blocks can be moved over the VMEbus as indivisible single cycles or BLTs. The protocol menu includes D8, D16, D32, MD32, or D64. A16, A24, A32, A40, and A64 address spaces can be specified. Burst lengths from 16 bytes to 8 megabytes can be requested. Eight registers accessible from the VMEbus make the facility simple to configure and simple to control. The facility has a busy semaphore, a VMEbus Interrupt on completion feature with a programmable Status/ID byte, and a built in requester and bus grant daisychain. To assist in generating the configuration file, a Windows™-based program is available which guides the user through the process of selecting appropriate options. Contact your Sales Office for further details. The CY7C961 is a true superset of the CY7C960. Signal pins have been added to control CY7C964 DMA functions. Existing VMEbus input pins have been changed to bidirectional and augmented to complete a master interface. A data port and chip select signal (SELECTLM*) complete the pin additions. As a VMEbus Slave, the CY7C961 behaves in every respect like the CY7C960. It simply has more pins, a master block transfer facility, and (because of the addition of the BBSY* connection) full lock cycle support. From a system perspective, the CY7C961 master block transfer capability can be viewed as a DMA channel that resides on the slave card, but is controlled over the VMEbus by one or more VMEbus masters or programmed from the local bus. System Diagram Using the CY7C960 LA [31:0] DRAMMEMORY I/O DBE[3:0], RW LACK* RAS*, CAS*, ROW,COL LIRQ* CS[2:0] LD[15:0] D[31:16] SWDEN RW SWAP BUFFER DECODER VCOMP REGION LA [7:1, LWORD] D[31:0] A [31:1], LWORD* IRQ* IACK* IACKIN* IACKOUT* SYSRESET* VME ADDRESS BUS CY7C960 AM[5:0] AS* D[15:8] VMEDATABUS D[7:0] CY7C964 A[7:1], LWORD* CY7C964 A[15:8] D[23:16] CY7C964 A[23:16] D[31:24] A[31:24] CY7C964 DS1/0* DTACK WRITE* LA [31:0] VME INTERRUPT BUS c960–5 4 CY7C960 CY7C961 DC Specifications - VMEbus Signals AS*, DS1*, DS0*, DTACK*, BBSY Parameter VIH VIL VOH VOL IL VIK IOZ Description Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Minimum High-Level Output Voltage Maximum Low-Level Output Voltage Maximum Input Leakage Current Input Clamp Voltage Maximum Output Leakage Current Test Conditions VCC = Min., IOH = VCC = Min., IOL = VCC = Max., GND < VIN < VCC VCC = Min., IIN = –18 mA VCC = Max. GND < VOUT < VCC Outputs Disabled Comm. 2.0 Industrial 2.0 Military 2.0 Units V 0.8 0.8 0.8 V 2.4 –16 mA 0.6 64 mA ±5 2.4 –10 mA 0.6 60 mA ±5 2.4 –9 mA 0.6 52 mA ±5 V –1.2 ±10 –1.2 ±10 –1.2 ±10 V µA V µA DC Specifications - VMEbus Signals AM5, AM4, AM3, AM2, AM1, AM0, IRQ*, BERR*, Write, BR[1] Parameter VIH VIL VOH VOL IL VIK IOZ Description Maximum High-Level Input Voltage Maximum Low-Level Input Voltage Minimum High-Level Output Voltage Minimum Low-Level Output Voltage Maximum Input Leakage Current Input Clamp Voltage Maximum Output Leakage Current Test Conditions VCC = Min., IOH = VCC = Min., IOL = VCC = Max., GND < VIN < VCC VCC = Min., IIN = –18 mA VCC = Max. GND < VOUT < VCC Outputs Disabled Comm. 2.0 Industrial 2.0 Military 2.0 Units V 0.8 0.8 0.8 V 2.4 –16 mA 0.6 48 mA ±5 2.4 –10 mA 0.6 44 mA ±5 2.4 –9 mA 0.6 38 mA ±5 V –1.2 ±5 –1.2 ±5 –1.2 ±10 V µA Comm. 2.0 Industrial 2.0 Military 2.0 Units V 0.8 0.8 0.8 V 2.4 –16 mA 0.6 20 mA ±5 2.4 –10 mA 0.6 18 mA ±5 2.4 –9 mA 0.6 16 mA ±5 V –1.2 ±5 –1.2 ±5 –1.2 ±10 V µA V µA DC Specifications - All Other Output Signals[2] Parameter VIH VIL VOH VOL IL VIK IOZ Description Maximum High-Level Input Voltage Maximum Low-Level Input Voltage Minimum High-Level Output Voltage Minimum Low-Level Output Voltage Maximum Input Leakage Current Input Clamp Voltage Maximum Output Leakage Current Test Conditions VCC = Min., IOH = VCC = Min., IOL = VCC = Max., GND < VIN < VCC VCC = Min., IIN = –18 mA VCC = Max. GND < VOUT < VCC Outputs Disabled Notes: 1. The BERR* signal has an on-chip pull-up resistor. For this signal the IOZ value is modified by Pullup/Pulldown Current. 2. Some signals have an on-chip pull-up or pull-down resistors. For these signals IOZ value is modified. 5 V µA CY7C960 CY7C961 Capacitance - All Signals Parameters Description Input Capacitance Output Capacitance CIN COUT Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 15 15 Units pF pF Typ. 100 µA Max. 250 µA 100 µA 250 µA Max. 100 Units mA Pullup/Pulldown Current - All Signals Parameters Description Input Pullup Current Input Pullup Current IPU IPU Test Conditions TA = –55°C, VCC = 5.5V VIN = GND TA = –55°C, VCC = 5.5V VIN = VCC Operating Current (CY7C960/CY7C961) Parameters Description Test Conditions Maximum Operating Current No external DC load IDD Related Documents VMEBus Interface Handbook Ordering Information Package Name Package Type CY7C960-ASC A64 10x10 mm body 64-Lead Plastic Thin Quad Flatpack CY7C960-NC N65 14x14 mm body 64-Lead Plastic Thin Quad Flatpack CY7C960-UM U65 14x14 mm body 64 lead Ceramic Quad Flatpack CY7C960-UMB U65 14x14 mm body 64 lead Ceramic Quad Flatpack Ordering Code Ordering Code Package Name CY7C961-NC A100 Package Type Operating Range Commercial Military Operating Range 14x14 mm body 100-Lead Plastic Thin Quad Flatpack Commercial Windows is a trademark of Microsoft Corporation. Document #: 38-00250-D 6 CY7C960 CY7C961 Package Diagrams 64-Pin Thin Quad Flatpack A64 7 CY7C960 CY7C961 Package Diagrams (continued) 100-Pin Thin Quad Flatpack A100 8 CY7C960 CY7C961 Package Diagrams (continued) 64-Lead Plastic Thin Quad Flatpack N65 9 CY7C960 CY7C961 Package Diagrams (continued) 64-Lead Ceramic Quad Flatpack (Cavity Up) U65 © Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.