LINER LTM4618

LTM4618
6A DC/DC µModule
Regulator with Tracking and
Frequency Synchronization
DESCRIPTION
FEATURES
n
n
n
n
n
n
n
n
n
n
n
n
n
n
Complete Standalone Power Supply
Wide Input Voltage Range: 4.5V to 26.5V
6A DC Typical, 8A Peak Output Current
0.8V to 5V Output
Output Voltage Tracking
±1.75% Maximum Total DC Error
Current Mode Control/Fast Transient Response
Phase-Lockable Fixed Frequency 250kHz to 780kHz
On-Board Frequency Synchronization
Selectable Burst Mode® Operation
Power Good Voltage Indicator
Output Overvoltage Protection
Output Current Foldback Limiting
9mm × 15mm × 4.32mm LGA Package
APPLICATIONS
n
n
n
n
n
n
n
The LTM®4618 is a complete 6A output switching mode
DC/DC power supply in a 9mm × 15mm × 4.32mm LGA
package. Included in the package are the switching controller, power FETs, inductor and all support components.
Operating over an input voltage range of 4.5V to 26.5V,
the LTM4618 supports an output voltage range of 0.8V
to 5V set by a single external resistor. Its high efficiency
design delivers 6A continuous current (8A peak). Only a
few input and output capacitors are needed.
High switching frequency and a current mode architecture
enable a very fast transient response to line and load
changes without sacrificing stability. The device supports
frequency synchronization and output voltage tracking for
supply rail sequencing. Burst Mode operation or pulseskipping mode can be selected for light load operations.
Fault protection features include overvoltage protection,
overcurrent protection and foldback current limit for
short-circuit protection.
Telecom and Networking Equipment
Servers
Storage Cards
ATCA Cards
Industrial Equipment
Point of Load Regulation
Medical Systems
The LTM4618 is Pb-free and RoHS compliant.
L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode and μModule are registered
trademarks of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
TYPICAL APPLICATION
2.5V/6A DC/DC Power μModule® with 6V to 26.5V Input
Efficiency and Power Loss vs Load Current
95
3.0
EFFICIENCY
2.5
MODE/PLLIN INTVCC EXTVCC
FREQ
VIN
CIN
COMP
LTM4618
TK/SS
0.1μF
VOUT
COUT
VFB
RUN
PGOOD
SGND
28.7k
VOUT
2.5V/6A
2.0
85
1.5
80
1.0
POWER LOSS (W)
VIN
6V to 26.5V
EFFICIENCY (%)
90
POWER LOSS
PGND
4618 TA01
75
70
0.5
12VIN TO 2.5VOUT
24VIN TO 2.5VOUT
0
1
3
2
4
LOAD CURRENT (A)
5
6
0
4618 TA01b
4618f
1
LTM4618
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
VIN, SW ...................................................... –0.3V to 28V
INTVCC, RUN, EXTVCC, PGOOD .................... –0.3V to 6V
COMP, VFB ................................................. –0.3V to 2.7V
MODE/PLLIN, TK/SS,
FREQ ..................................................... –0.3V to INTVCC
VOUT ............................................................... 0.8V to 5V
Operating Junction Temperature Range
(Note 2)..................................................–40°C to 125°C
Storage Temperature Range................... –55°C to 125°C
Peak Package Body Temperature .......................... 250°C
TOP VIEW
SW
7
VIN
6
PGND
5
EXTVCC
4
SGND/PGND
MODE/
PLLIN
FREQ
RUN
3
VOUT
2
1
A
B
C
D
E
F
G
H
J
K
L
M
INTVCC
TK/SS COMP VFB PGOOD
LGA PACKAGE
84-LEAD (15mm s 9mm s 4.32mm)
ΘJA = 16°C/W, ΘJCtop = 15°C/W, ΘJCbottom = 4°C/W, WEIGHT = 2.3g,
θJB + θBA = 16°C/W, θBA = BOARD-TO-AMBIENT RESISTANCE,
θ VALUES DEFINED PER JESD51-12
ORDER INFORMATION
LEAD FREE FINISH
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTM4618EV#PBF
LTM4618V
84-Lead (15mm × 9mm × 4.32mm) LGA
–40°C to 125°C
LTM4618IV#PBF
LTM4618V
84-Lead (15mm × 9mm × 4.32mm) LGA
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, per typical application in Figure 21.
SYMBOL
PARAMETER
CONDITIONS
VIN(DC)
Input DC Voltage
(Note 5)
VOUT(DC)
Output Voltage Total Variation with
Line and Load
CIN = 10μF ×2, RFB = 28.0kΩ
COUT = 100μF ×3 X7R Ceramic
MODE/PLLIN = 0V, VFREQ = 2.4V
VIN = 6V to 26.5V, IOUT = 0A to 6A (Note 4)
MIN
TYP
MAX
UNITS
26.5
V
l
4.5
l
2.476
2.52
2.557
V
2.00
1.85
2.20
2.00
2.35
2.15
V
V
Input Specifications
VIN(UVLO)
Undervoltage Lockout Thresholds
VINTVCC Rising
VINTVCC Falling
IINRUSH(VIN)
Input Inrush Current at Start-Up
IOUT = 0A, CIN = 10μF ×2, COUT = 100μF ×3
VOUT = 2.5V
VIN = 12V
VIN = 26.5V
0.3
0.2
A
A
4618f
2
LTM4618
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, per typical application in Figure 21.
SYMBOL
PARAMETER
CONDITIONS
IQ(VIN)
Input Supply Bias Current
VIN = 12V, VOUT = 2.5V, IOUT = 0A
VIN = 26.5V, VOUT = 2.5V, IOUT = 0A
Shutdown, RUN = 0, VIN = 26.5V
MIN
26
20
80
IS(VIN)
Input Supply Current
VIN = 12V, VOUT = 2.5V, IOUT = 6A
VIN = 26.5V, VOUT = 2.5V, IOUT = 6A
1.430
0.675
INTVCC
Internal VCC Voltage
VIN = 12V, VRUN > 2V, No Load
VEXTVCC
EXTVCC Switchover Voltage
EXTVCC Ramping Positive
VLDO External
EXTVCC Voltage Drop
INTVCC = 20mA, VEXTVCC = 5V
VEXTVCC Hysteresis
EXTVCC Hysteresis
l
TYP
4.8
5
4.5
4.7
50
MAX
UNITS
mA
mA
μA
A
A
5.2
V
V
100
200
mV
mV
Output Specifications
IOUT(DC)
Output Continuous Current Range
VIN = 12V, VOUT = 2.5V (Note 4)
0
6
A
ΔVOUT(LINE)
VOUT
Line Regulation Accuracy
VOUT = 2.5V, VIN from 6V to 26.5V
IOUT = 0A
l
0.02
0.04
%/V
ΔVOUT(LOAD)
VOUT
Load Regulation Accuracy
VIN = 12V, VOUT = 2.5V, 0 to 6A (Note 4)
l
0.3
0.6
%
VOUT(AC)
Output Ripple Voltage
IOUT = 0A, COUT = 100μF ×3 X5R Ceramic
VIN = 12V, VOUT = 2.5V
VIN = 26.5V, VOUT = 2.5V
10
12
mV
mV
fS
Output Ripple Voltage Frequency
IOUT = 2A, VIN = 12V, VOUT = 2.5V, VFREQ = INTVCC
780
kHz
ΔVOUT(START)
Turn-On Overshoot
COUT = 100μF ×3 X5R Ceramic
VOUT = 2.5V, IOUT = 0A
VIN = 12V
VIN = 26.5V
20
20
mV
mV
0.75
0.70
ms
ms
tSTART
Turn-On Time
COUT = 100μF ×3 X5R Ceramic,
VOUT = 2.5V, IOUT = 0A, TK/SS Capacitor = 0.01μF
VIN = 12V
VIN = 26.5V
ΔVOUTLS
Peak Deviation for Dynamic Load
Load: 0% to 50% of Full Load
COUT = 100μF ×3 X5R Ceramic, VOUT = 2.5V
VIN = 12V
15
mV
tSETTLE
Settling Time for Dynamic Load Step
Load: 0% to 50% of Full Load
COUT = 100μF ×3 X5R Ceramic, VOUT = 2.5V
VIN = 12V
10
μs
COUT = 100μF ×3 X5R Ceramic
VIN = 6V, VOUT = 2.5V
VIN = 26.5V, VOUT = 2.5V
11
11
A
A
IOUT(PK)
Output Current Limit
Control Section
VFB
Error Amplifier Feedback Voltage
IOUT = 0A, VOUT = 2.5V
IFB
Error Amplifier Feedback Current
(Note 3)
VOVL
Feedback Voltage Lockout
Measured at VFB
ITK/SS
Soft-Start Charge Current
VTK/SS = 0V
DFMAX
Maximum Duty Factor
In Dropout (Note 3)
tON(MIN)
Minimum On-Time
(Note 3)
fNOM
Nominal Frequency
VFREQ = 1.2V
450
500
550
kHz
fLOW
Lowest Frequency
VFREQ = 0V
210
250
290
kHz
l
0.792
0.788
0.8
0.8
0.808
0.808
V
V
–10
–50
nA
0.84
0.86
0.88
V
0.9
1.3
1.7
μA
97
%
90
ns
4618f
3
LTM4618
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, per typical application in Figure 21.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fHIGH
Highest Frequency
VFREQ ≥ 2.4V, INTVCC
700
780
860
kHz
VIH(MODE/PLLIN)
Synchronous Clock High Level
2.0
VIL(MODE/PLLIN)
Synchronous Clock Low Level
RMODE/PLLIN
MODE/PLLIN Input Resistance
IFREQ
FREQ Pin
Sinking Current
Sourcing Current
fMODE/PLLIN > fOSC
fMODE/PLLIN < fOSC
RUN Rising
VRUN
RUN Pin On Threshold
VRUN Hysteresis
RUN Pin Hysteresis
RFBHI
Resistor Between VOUT and VFB Pins
V
0.8
1.1
kΩ
–13
13
μA
μA
1.22
1.35
120
60.1
V
250
V
mV
60.4
60.7
kΩ
0.1
0.3
V
±2
μA
–10
10
%
%
PGOOD Output
VPGL
PGOOD Voltage Low
IPGOOD = 2mA
IPGOOD
PGOOD Leakage Current
VPGOOD = 5V
VPG
PGOOD Trip Level
VFB with Respect to Set Regulated Voltage
VFB Ramping Negative
VFB Ramping Positive
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4618 is tested under pulsed load conditions such that
TJ ≈ TA. The LTM4618E is guaranteed to meet performance specifications
over the 0°C to 125°C operating junction temperature range. Specifications
over the full –40°C to 125°C operating junction temperature range are
assured by design, characterization and correlation with statistical process
controls. The LTM4618I is guaranteed to meet specifications over the full
–5
5
–7.5
7.5
operating junction temperature range. Note that the maximum ambient
temperature consistent with these specifications is determined by specific
operating conditions in conjunction with board layout, the rated package
thermal resistance and other environmental factors.
Note 3: 100% tested at wafer level only.
Note 4: See Output Current Derating curves for different VIN, VOUT and TA.
Note 5: For input voltages less than 6V, tie the VIN, INTVCC and EXTVCC
together. The LTM4618 will operate from 5V inputs, but VIN, INTVCC and
EXTVCC need to be tied together.
4618f
4
LTM4618
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current with
12VIN (CCM)
95
95
90
90
EFFICIENCY (%)
100
EFFICIENCY (%)
100
85
80
5V TO 0.8VOUT
5V TO 1.2VOUT
5V TO 1.5VOUT
5V TO 2.5VOUT
5V TO 3.3VOUT
75
70
0
1
95
90
85
80
12V TO 1.2VOUT
12V TO 1.5VOUT
12V TO 2.5VOUT
12V TO 3.3VOUT
12V TO 5VOUT
75
3
2
4
LOAD CURRENT (A)
5
6
Efficiency vs Load Current with
24VIN (CCM)
EFFICIENCY (%)
Efficiency vs Load Current with
5VIN (CCM)
70
0
1
3
2
4
LOAD CURRENT (A)
4618 G01
5
85
80
75
6
70
24V TO 2.5VOUT
24V TO 3.3VOUT
24V TO 5VOUT
0
1
2
4
3
LOAD CURRENT (A)
4618 G02
Efficiency vs Load Current with
Different Mode Settings
(12V to 3.3V)
5
6
4618 G03
1.2V Transient Response
1.5V Transient Response
100
VIN = 12V
90 VOUT = 3.3V
EFFICIENCY (%)
80
70
IOUT
1A/DIV
IOUT
1A/DIV
VOUT
50mV/DIV
VOUT
50mV/DIV
60
50
40
4618 G05
30
20
BURST
PULSE SKIP
CCM
10
0
0.01
0.1
LOAD CURRENT (A)
4618 G06
50μs/DIV
VIN = 12V AND VOUT = 1.2V AT 3A/μs LOAD STEP
COUT = 2s 22μF 6.3V CERAMIC CAPACITOR
1s 100μF 6.3V CERAMIC CAPACITOR
1s 220μF SANYO POSCAP
50μs/DIV
VIN = 12V AND VOUT = 1.5V AT 3A/μs LOAD STEP
COUT = 2s 22μF 6.3V CERAMIC CAPACITOR
1s 100μF 6.3V CERAMIC CAPACITOR
1s 220μF SANYO POSCAP
3.3V Transient Response
5V Transient Response
1
4618 G04
2.5V Transient Response
IOUT
1A/DIV
IOUT
1A/DIV
IOUT
1A/DIV
VOUT
50mV/DIV
VOUT
50mV/DIV
VOUT
100mV/DIV
4618 G07
50μs/DIV
VIN = 12V AND VOUT = 2.5V AT 3A/μs LOAD STEP
COUT = 2s 22μF 6.3V CERAMIC CAPACITOR
1s 100μF 6.3V CERAMIC CAPACITOR
1s 220μF SANYO POSCAP
4618 G08
50μs/DIV
VIN = 12V AND VOUT = 3.3V AT 3A/μs LOAD STEP
COUT = 2s 22μF 6.3V CERAMIC CAPACITOR
1s 100μF 6.3V CERAMIC CAPACITOR
1s 220μF SANYO POSCAP
4618 G09
50μs/DIV
VIN = 12V AND VOUT = 5V AT 3A/μs LOAD STEP
COUT = 2s 22μF 6.3V CERAMIC CAPACITOR
1s 100μF 6.3V CERAMIC CAPACITOR
1s 220μF SANYO POSCAP
4618f
5
LTM4618
TYPICAL PERFORMANCE CHARACTERISTICS
Start-Up, IOUT = 0A
Start-Up, IOUT = 6A
VOUT
1V/DIV
VOUT
1V/DIV
IIN
0.2A/DIV
IIN
0.5A/DIV
20ms/DIV
VIN = 12V AND VOUT = 2.5V
COUT = 2s 22μF 6.3V CERAMIC,
1s 100μF 6.3V CERAMIC AND
1s 220μF SANYO POSCAP
CSOFT-START = 0.1μF
4618 G10
20ms/DIV
VIN = 12V AND VOUT = 2.5V
COUT = 2s 22μF 6.3V CERAMIC,
1s 100μF 6.3V CERAMIC AND
1s 220μF SANYO POSCAP
CSOFT-START = 0.1μF
Short-Circuit Protection,
IOUT = 0A
Short-Circuit Protection,
IOUT = 6A
VOUT
1V/DIV
VOUT
1V/DIV
IIN
1A/DIV
IIN
1A/DIV
100μs/DIV
VIN = 12V AND VOUT = 2.5V
COUT = 2s 22μF 6.3V CERAMIC,
1s 100μF 6.3V CERAMIC AND
1s 220μF SANYO POSCAP
4618 G11
4618 G12
100μs/DIV
VIN = 12V AND VOUT = 2.5V
COUT = 2s 22μF 6.3V CERAMIC,
1s 100μF 6.3V CERAMIC AND
1s 220μF SANYO POSCAP
4618 G13
4618f
6
LTM4618
PIN FUNCTIONS
SGND (B3, C2 and C3): Signal Ground Pin. Return ground
path for all analog and low power circuitry. Tie a single
connection to PGND. See applications for details.
NC (A1): No Connect. Leave floating.
FREQ (A2): Frequency Selection Pin. An internal low pass
filter is tied to this pin. The frequency can be selected from
250kHz to 780kHz by setting a voltage from this pin to
SGND. A programming resistor divider can be used to set
the operating frequency. See the Applications Information
section.
COMP (C1): Current control threshold and error amplifier compensation point. The module has been internally
compensated for most I/O ranges.
EXTVCC (C4): External Voltage Input. Bypasses the internal
INTVCC LDO and powers the internal circuitry and MOSFET
drivers. If a 5V source is available, the internal LDO is
disabled, and the power dissipation is lower, especially at
higher input voltages. See the Applications Information
section.
MODE/PLLIN (A3): Mode Selection or External Synchronization Pin. Tying this pin to INTVCC enables pulse-skipping
operation. Tying this pin low enables forced continuous
mode operation. Burst Mode operation is enabled by floating the pin. A clock on the pin will force the controller into
forced continuous mode of operation and synchronize to
the internal oscillator. The programming DC voltage has
to be removed for clock synchronization.
VFB (D1): The negative input of the error amplifier. Internally, this pin is connected to VOUT with a 60.4kΩ precision
resistor. Different output voltages can be programmed
with an additional resistor between VFB and SGND pins.
See applications for details.
PGND (BANK 2: A4, B4, D4-D7, E1-E7, F1-F7, G1-G7,
H1-H7, J5-J7, K5, K7, L5-L7, M5-M7): Power ground
pins for both input and output returns.
PGOOD (D2): Output Voltage Power Good Indicator. Opendrain logic output that is pulled to ground when the output
voltage is not within ±7.5% of the regulation point.
VIN (BANK 1: A5-A7, B5-B7, C5-C7): Power Input Pins.
Apply input voltage between these pins and PGND pins.
Recommend placing input decoupling capacitance directly
between VIN pins and PGND pins.
INTVCC (D3): Internal 5V Regulator Output. This pin is for
additional decoupling of the 5V internal regulator.
TK/SS (B1): Output Voltage Tracking and Soft-Start Pin. An
internal soft-start current of 1.3μA charges the soft-start
capacitor. See the Applications Information section.
VOUT (BANK 3: J1-J4, K1-K4, L1-L4, M1-M4): Power Output Pins. Apply output load between these pins and PGND
pins. Recommend placing output decoupling capacitance
directly between these pins and PGND pins.
RUN (B2): Run Control Pin. A voltage above 1.35V on
this pin turns on the module. Forcing this pin below 1.1V
will shut down the output. The RUN pin has a 1μA pullup current source that increases to 10μA as the RUN pin
voltage reaches 1.5V and up to compliance. Therefore the
pin can be left floating for normal operation. A maximum
of 6V can be applied to the pin. A voltage divider can be
used for a UVLO function. See the Applications Information section.
SW (K6): Switching Node of the Circuit. This pin is used
to check the switching frequency. Leave pin floating. A
resistor-capacitor snubber can be placed from SW to
PGND to eliminate high frequency switch node ringing.
See the Applications Information section.
7
BANK 2
PGND
BANK 1
VIN 6
SW
5
SGND/PGND 4
3
BANK 3
VOUT
2
CNTRL
1
A
B
C
D
E
F
G
H
J
K
L
M
4618f
7
LTM4618
SIMPLIFIED BLOCK DIAGRAM
≤6V VIN
TIE VIN, INTVCC AND
EXTVCC TOGETHER
INTERNAL
FILTER
+
1.5μF
EXTVCC
INTVCC
MODE/PLLIN
VIN
4.5V TO 26.5V
CIN
M1
SW
1.5μH
TK/SS
VOUT
2.5V/6A
CSS
POWER
CONTROL
RUN
PGOOD
COMP
M2
+
10μF
COUT
PGND
INTVCC
INTERNAL
COMP
60.4k
FREQ
VFB
RFB
28k
INTERNAL
FILTER
SGND
4618 F01
Figure 1. Simplified LTM4618 Block Diagram
DECOUPLING REQUIREMENTS
TA = 25°C. Use Figure 1 configuration.
SYMBOL
PARAMETER
CONDITIONS
CIN
External Input Capacitor Requirement
(VIN = 4.5V to 26.5V, VOUT = 2.5V)
IOUT = 6A
COUT
External Output Capacitor Requirement
(VIN = 4.5V to 26.5V, VOUT = 2.5V)
IOUT = 6A
MIN
TYP
10
MAX
UNITS
μF
200
μF
4618f
8
LTM4618
OPERATION
Power Module Description
The LTM4618 is a standalone non-isolated switching mode
DC/DC power supply. It can deliver up to 6A (DC current)
output with few external input and output capacitors. This
module provides precisely regulated output voltages programmable via external resistors from 0.8VDC to 5.0VDC
over 4.5V to 26.5V input voltages. The typical application
schematic is shown in Figure 21. For ≤6V inputs, connect
VIN, INTVCC and EXTVCC together.
The LTM4618 has an integrated constant frequency current
mode regulator and built-in power MOSFET devices with
fast switching speed. The typical switching frequency is
750kHz.
With current mode control and internal feedback loop
compensation, the LTM4618 module has sufficient stability margins and good transient performance with a wide
range of output capacitors, even with all ceramic output
capacitors.
Current mode control provides cycle-by-cycle fast current
limit and current foldback in a short-circuit condition. Pulling the RUN pin below 1.1V forces the controller into its
shutdown state, by turning off both MOSFETs. The TK/SS
pin can be used for programming the output voltage ramp
and voltage tracking during start-up. See the Applications
Information section.
The LTM4618 is internally compensated to be stable over
all operating conditions. The Linear Technology μModule
Power Design Tool will be provided for transient and
stability analysis. The VFB pin is used to program the
output voltage with a single external resistor to ground.
Multiphase operation can be easily employed with the
synchronization control.
High efficiency at light loads can be accomplished with
selectable Burst Mode or pulse-skipping mode operations
using the MODE/PLLIN pin. Efficiency graphs are provided
for light load operation in the Typical Performance Characteristics section.
4618f
9
LTM4618
APPLICATIONS INFORMATION
The typical LTM4618 application circuit is shown in
Figure 21. External component selection is primarily
determined by the maximum load current and output
voltage.
VIN to VOUT Step-Down Ratios
There are restrictions in the maximum VIN to VOUT stepdown ratio that can be achieved for a given input voltage.
One of the restrictions is the minimum on-time tON(MIN),
which is the smallest time duration that the LTM4618 can
operate. Make sure that the operating on-time is larger than
the minimum on-time as shown in the equation below. See
the Thermal Considerations and Output Current Derating
sections in this data sheet for the current restrictions.
tON(MIN) is approximately 90ns, guardband to 110ns.
tON(MIN) <
VOUT
VIN • ƒ
The LTM4618 module should be connected to a low ACimpedance DC source. One 1.5μF input ceramic capacitor
is included inside the module. Additional input capacitors
are only needed if a large load step is required up to
the 6A level. A 47μF to 100μF surface mount aluminum
electrolytic bulk capacitor can be used for more input bulk
capacitance. This bulk input capacitor is only needed if
the input source impedance is compromised by long inductive leads, traces or not enough source capacitance.
If low impedance power planes are used, then this 47μF
capacitor is not needed.
For a buck converter, the switching duty-cycle can be
estimated as:
D=
VOUT
VIN
Without considering the inductor current ripple, the RMS
current of the input capacitor can be estimated as:
Output Voltage Programming
The PWM controller has an internal 0.8V reference voltage.
As shown in the Block Diagram, a 60.4k internal feedback
resistor connects VOUT to the VFB pin. Adding a resistor RFB
from the VFB pin to SGND programs the output voltage:
VOUT = 0.8V •
Input Capacitors
60.4k + RFB
RFB
Table 1. VFB Resistor Table vs Various Output Voltages
VOUT (V)
0.8
1
1.2
1.5
1.8
2.5
3.3
5
RFB (kΩ)
Open
243
121
69.8
48.7
28.7
19.1
11.5
ICIN(RMS) =
IOUT(MAX)
η
• D • (1– D)
In the above equation, η is the estimated efficiency of
the power module. One 10μF ceramic input capacitor is
typically rated for 2A of RMS ripple current, so the RMS
input current at the worst case 6A maximum current is
about 3A. If a low inductance plane is used to power the
device, then two 10μF ceramic capacitors are enough for
the output at 6A load and no external input bulk capacitor
is required. The input RMS ripple current can be cancelled
by paralleling multiple LTM4618 power modules out of
phase, allowing the use of fewer input capacitors. Application Note 77 explains the details.
4618f
10
LTM4618
APPLICATIONS INFORMATION
Output Capacitors
Frequency Selection
The LTM4618 is designed for low output voltage ripple
noise. The bulk output capacitors defined as COUT are
chosen with low enough effective series resistance (ESR) to
meet the output voltage ripple and transient requirements.
COUT can be a low ESR tantalum capacitor, a low ESR
polymer capacitor or ceramic capacitor. The typical output
capacitance range is from 100μF to 300μF. Additional output
filtering may be required by the system designer if further
reduction of output ripple or dynamic transient spikes is
required. Table 4 shows a matrix of different output voltages
and output capacitors to minimize the voltage droop and
overshoot during a 3A/μs transient. The table optimizes the
total equivalent ESR and total bulk capacitance to optimize
the transient performance. Stability criteria are considered
in the Table 4 matrix, and the Linear Technology μModule
Power Design Tool is available for stability analysis. Multiphase operation will reduce effective output ripple as a
function of the number of phases. Application Note 77
discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be
considered carefully as a function of stability and transient
response. The Linear Technology μModule Power Design
Tool can calculate the output ripple reduction as the number
of implemented phases increases by N times.
The switching frequency of the LTM4618’s controller can
be selected using a DC voltage. If the MODE/PLLIN pin
is not being driven by an external clock source, the FREQ
pin can program the controller’s operating frequency
from 250kHz to 780kHz by connecting a resistor divider
as shown in Figure 21. The typical frequency is 750kHz.
But if the minimum on-time is reached, a lower frequency
needs to be set to increase the turn-on time. Otherwise, a
significant amount of cycle skipping can occur with correspondingly larger ripple current and voltage ripple.
900
SWITCHING FREQUENCY (kHz)
800
700
600
500
400
300
200
100
0
0
0.5
1
1.5
FREQ PIN VOLTAGE (V)
2
2.5
4618 F03
Figure 3. Relationship Between Switching
Frequency and Voltage at the FREQ Pin
Mode Selections and Phase-Locked Loop
The LTM4618 can be enabled to enter high efficiency
Burst Mode operation, constant-frequency, pulse-skipping
mode, or forced continuous conduction mode. To select
the forced continuous operation, tie the MODE/PLLIN pin
to ground. To select pulse-skipping mode of operation,
tie the MODE/PLLIN pin to INTVCC . To select Burst Mode
operation, float the pin.
A phase-locked loop (PLL) is available on the LTM4618
to synchronize the internal oscillator to an external clock
source that is connected to the MODE/PLLIN pin. The
incoming clock should be applied before the regulator’s
RUN pin is enabled.
Frequency Synchronization
The MODE/PLLIN pin allows the LTM4618 to be synchronized to an external clock (between 400kHz to 780kHz)
and the internal phase-locked loop allows the LTM4618
to lock onto input clock phase as well. The FREQ pin has
the onboard loop filter for the PLL. The incoming clock
must be applied before the RUN pin is enabled. For applications powering the clock source from the LTM4618’s
INTVCC , the RUN pin has to be enabled in order to activate INTVCC for the clock source. In this situation (see
Figure 22) the TK/SS pin can be used to soft-start the
regulator for 100ms using a ≈ 0.22μF capacitor. This will
allow the regulator to synchronize to the right frequency
before the regulator’s inductor ripple current peaks.
4618f
11
LTM4618
APPLICATIONS INFORMATION
The LTM4618 can be synchronized from 400kHz to 780kHz
with an input clock that has a high level above 2.0V and a
low level below 0.8V. The 400kHz low end operation limit
is put in place to limit inductor ripple current. See the
Typical Applications section for synchronization examples.
The LTM4618 minimum on-time is limited to about 90ns.
Guardband the on-time to 110ns. The on-time can be
calculated as:
tON(MIN) =
1 ⎛ VOUT ⎞
•
FREQ ⎜⎝ VIN ⎟⎠
Soft-Start and Tracking
LTM4618 has the ability to either soft-start by itself with a
capacitor or track the output of an external supply. When
the module is configured to soft-start by itself, a capacitor
should be connected to its TK/SS pin. When the module
is in the shutdown state, the TK/SS pin is actively pulled
to ground.
Once the RUN pin voltage is above 1.22V, the module powers up. Then a soft-start current of 1.3μA starts to charge
its soft-start capacitor. Note that soft-start or tracking is
achieved not by limiting the maximum output current of
the controller but by controlling the output ramp voltage
according to the ramp rate on the TK/SS pin. Current
foldback is disabled during this phase to ensure smooth
soft-start or tracking. The soft-start or tracking range is
defined as the voltage range from 0V to 0.8V on the TK/SS
pin. The total soft-start time can be calculated as:
0.8V • CSS
t SOFT-START =
1.3µA
Output voltage tracking can be programmed externally
using the TK/SS pin. The master voltage is divided down
with an external resistor divider that is the same as the
slave’s feedback divider to implement coincident tracking.
The LTM4618 uses an accurate 60.4k resistor internally
for the top feedback resistor. Figure 4 shows an example
of coincident tracking.
VTRACK is the track ramp applied to the slave’s TK/SS
pin. VTRACK has a control range of 0V to 0.8V. When the
master’s output is divided down with the same resistor
values used to set the slave’s output, then the slave will
coincident track with the master until it reaches its final
value. The master will continue to its final value from the
slave’s regulation point.
Ratiometric modes of tracking can be achieved by selecting different divider resistor values to change the output
tracking ratio. The master output must be greater than the
slave output for the tracking to work. Master and slave
data inputs can be used to implement the correct resistor
values for coincident or ratio tracking.
VIN
5V
CIN
MODE/PLLIN INTVCC EXTVCC
VIN
FREQ
COMP
MASTER R1
OUTPUT 60.4k
VOUT
22pF
LTM4618
COUT
TK/SS
R2
28.7k
VOUT(SLAVE)
2.5V/6A
VFB
RUN
PGOOD
SGND
28.7k
PGND
4618 F04
Figure 4. Output Voltage Coincident Tracking
MASTER OUTPUT
SLAVE OUTPUT
OUTPUT
VOLTAGE
TIME
4618 F05
Figure 5. Coincident Tracking Characteristics
⎛ R1⎞
VOUT(SLAVE) = ⎜ 1+ ⎟ • VTRACK
⎝ R2 ⎠
4618f
12
LTM4618
APPLICATIONS INFORMATION
Slope Compensation
The module has already been internally compensated
for all output voltages. The Linear Technology μModule
Power Design Tool will be provided for other control loop
optimization.
RUN Pin
The RUN pin has a 1μA pull-up current source that will
enable the device in a float condition. A voltage divider
can be used to enable a UVLO function using the RUN
pin. See Figure 21.
Fault Conditions: Current Limit and Overcurrent
Foldback
The LTM4618 has a current mode controller, which inherently limits the cycle-by-cycle inductor current not only in
steady-state operation, but also in transient.
To further limit current in the event of an overload condition, the LTM4618 provides foldback current limiting. If the
output voltage falls by more than 40%, then the maximum
output current is progressively lowered to about 25% of
its full current limit value.
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those parameters defined by JESD51-9 and are intended for use with
finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation,
and correlation to hardware evaluation performed on a
μModule package mounted to a hardware test board—also
defined by JESD51-9 (“Test Boards for Area Array Surface
Mount Package Thermal Measurements”). The motivation
for providing these thermal coefficients in found in JESD
51-12 (“Guidelines for Reporting and Using Electronic
Package Thermal Information”).
Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to anticipate
the μModule regulator’s thermal performance in their application at various electrical and environmental operating
conditions to compliment any FEA activities. Without FEA
software, the thermal resistances reported in the Pin Con-
figuration section are in-and-of themselves not relevant to
providing guidance of thermal performance; instead, the
derating curves provided in the data sheet can be used in
a manner that yields insight and guidance pertaining to
one’s application-usage, and can be adapted to correlate
thermal performance to one’s own application.
The Pin Configuration section shows four thermal coefficients explicitly defined in JESD 51-12; these coefficients
are quoted or paraphrased below:
• θJA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient
air thermal resistance measured in a one cubic foot
sealed enclosure. This environment is sometimes
referred to as “still air” although natural convection
causes the air to move. This value is determined with
the part mounted to a JESD 51-9 defined test board,
which does not reflect an actual application or viable
operating condition.
• θJCbottom, the thermal resistance from junction to the
bottom of the product case, is the junction-to-board
thermal resistance with all of the component power
dissipation flowing through the bottom of the package. In the typical μModule, the bulk of the heat flows
out the bottom of the package, but there is always
heat flow out into the ambient environment. As a
result, this thermal resistance value may be useful
for comparing packages but the test conditions don’t
generally match the user’s application.
• θJCtop, the thermal resistance from junction to top of
the product case, is determined with nearly all of the
component power dissipation flowing through the
top of the package. As the electrical connections of
the typical μModule are on the bottom of the package, it is rare for an application to operate such that
most of the heat flows from the junction to the top of
the part. As in the case of θJCbottom, this value may
be useful for comparing packages but the test conditions don’t generally match the user’s application.
• θJB, the thermal resistance from junction to the
printed circuit board, is the junction-to-board thermal
resistance where almost all of the heat flows through
the bottom of the μModule and into the board, and
4618f
13
LTM4618
APPLICATIONS INFORMATION
is really the sum of the θJCbottom and the thermal resistance of the bottom of the part through the solder
joints and through a portion of the board. The board
temperature is measured at specified distance from
the package, using a two sided, two layer board.
This board is described in JESD 51-9.
A graphical representation of the forementioned thermal
resistances is given in Figure 6; blue resistances are contained within the μModule, whereas green resistances are
external to the μModule.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD 51-12 or provided in the
Pin Configuration section replicates or conveys normal
operating conditions of a μModule. For example, in actual
board-mounted applications, never does 100% of the
device’s total power loss (heat) thermally conduct exclusively through the top or exclusively through bottom of the
μModule—as the standard defines for θJCtop and θJCbottom,
respectively. In practice, power loss is thermally dissipated
in both directions away from the package—granted, in the
absence of a heat sink and airflow, a majority of the heat
flow is into the board.
Within a SIP (System-In-Package) module, be aware there
are multiple power devices and components dissipating
power, with a consequence that the thermal resistances
relative to different junctions of components or die are not
exactly linear with respect to total package power loss. To
reconcile this complication without sacrificing modeling
simplicity—but also, not ignoring practical realities—an
approach has been taken using FEA software modeling
along with laboratory testing in a controlled-environment
chamber to reasonably define and correlate the thermal
resistance values supplied in this data sheet: (1) Initially,
FEA software is used to accurately build the mechanical
geometry of the μModule and the specified PCB with all
of the correct material coefficients along with accurate
power loss source definitions; (2) this model simulates
a software-defined JEDEC environment consistent with
JSED51-9 to predict power loss heat flow and temperature
readings at different interfaces that enable the calculation
of the JEDEC-defined thermal resistance values; (3) the
model and FEA software is used to evaluate the μModule
with heat sinks and airflow; (4) having solved for and
analyzed these thermal resistance values and simulated
various operating conditions in the software model, a
thorough laboratory evaluation replicates the simulated
conditions with thermocouples within a controlled-environment chamber while operating the device at the same
power loss as that which was simulated. An outcome of
this process and due-diligence yields a set of derating
curves provided in other sections of this data sheet. After
these laboratory tests have been performed and correlated
to the μModule model, then the θJB and θBA are summed
together to correlate quite well with the μModule model
with no air flow or heat sinking in a properly define chamber. This θJB+ θBA value is shown in the Pin Configuration
section and should accurately equal the θJA value because
approximately 100% of power loss flows from the junction through the board into ambient with no airflow or top
mounted heat sink.
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
JUNCTION-TO-CASE (TOP)
RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
JUNCTION-TO-CASE
CASE (BOTTOM)-TO-BOARD
(BOTTOM) RESISTANCE
RESISTANCE
At
BOARD-TO-AMBIENT
RESISTANCE
4618 F06
μMODULE DEVICE
Figure 6. Graphical Representation of JESD51-12 Thermal Coefficients
4618f
14
LTM4618
APPLICATIONS INFORMATION
The 1.5V and 3.3V power loss curves in Figures 7 and 8
can be used in coordination with the load current derating
curves in Figures 9 to 16 for calculating an approximate
θJA thermal resistance for the LTM4618 with various heat
sinking and air flow conditions. The power loss curves
are taken at room temperature, and are increased with
multiplicative factors according to the ambient temperature. These approximate factors are: 1 for 40°C; 1.05 for
50°C; 1.1 for 60°C; 1.15 for 70°C; 1.2 for 80°C; 1.25 for
90°C; 1.3 for 100°C; 1.35 for 110°C and 1.4 for 125°C.
The derating curves are plotted with the output current
starting at 6A and the ambient temperature at 40°C. The
output voltages are 1.5V, and 3.3V. These are chosen to
include the lower and higher output voltage ranges for
correlating the thermal resistance. Thermal models are
derived from several temperature measurements in a controlled temperature chamber along with thermal modeling
analysis. The junction temperatures are monitored while
ambient temperature is increased with and without air
flow. The power loss increase with ambient temperature
change is factored into the derating curves. The junctions
are maintained at 120°C maximum while lowering output
current or power with increasing ambient temperature.
The decreased output current will decrease the internal
module loss as ambient temperature is increased. The
monitored junction temperature of 120°C minus the
ambient operating temperature specifies how much module temperature rise can be allowed. As an example, in
Figure 11 the load current is derated to ~5A at ~85°C with
2.0
no air flow or heat sink and the power loss for the 12V to
1.5V at 5A output is about 1.7W. The 1.7W loss is calculated with the ~1.4W room temperature loss from the 12V
to 1.5V power loss curve at 5A, and the 1.2 multiplying
factor at 85°C ambient. If the 85°C ambient temperature
is subtracted from the 115°C junction temperature, then
the difference of 30°C divided 1.7W equals a 17°C/W θJA
thermal resistance. Table 2 specifies a 16°C/W value which
is very close. Table 2 and Table 3 provide equivalent thermal
resistances for 1.5V and 3.3V outputs with and without air
flow and heat sinking. The derived thermal resistances in
Tables 2 and 3 for the various conditions can be multiplied
by the calculated power loss as a function of ambient
temperature to derive temperature rise above ambient,
thus maximum junction temperature. Room temperature
power loss can be derived from the efficiency curves
in the Typical Performance Characteristics section and
adjusted with the above ambient temperature multiplicative factors. The printed circuit board is a 1.6mm thick
four layer board with two ounce copper for the two outer
layers and one ounce copper for the two inner layers. The
PCB dimensions are 95mm × 76mm. The BGA heat sink
is listed in Table 3.
Safety Considerations
The LTM4618 modules do not provide isolation from VIN to
VOUT. There is no internal fuse. If required, a slow blow fuse
with a rating twice the maximum input current needs to be
provided to protect each unit from catastrophic failure.
3.0
5VIN
12VIN
12VIN
24VIN
2.5
POWER LOSS (W)
POWER LOSS (W)
1.5
1.0
2.0
1.5
1.0
0.5
0.5
0
0
1
3
2
4
LOAD CURRENT (A)
5
6
4618 F07
Figure 7. Power Loss at 1.5VOUT
0
0
1
3
2
4
LOAD CURRENT (A)
5
6
4618 F08
Figure 8. Power Loss at 3.3VOUT
4618f
15
LTM4618
6
6
5
5
5
4
3
2
1
0
0LFM
200LFM
400LFM
70
75
LOAD CURRENT (A)
6
LOAD CURRENT (A)
LOAD CURRENT (A)
APPLICATIONS INFORMATION
4
3
2
1
0
80 85 90 95 100 105 110 115
AMBIENT TEMPERATURE (°C)
75
2
0
80 85 90 95 100 105 110 115
AMBIENT TEMPERATURE (°C)
4618 F09
Figure 10. 5VIN to 1.5VOUT with
Heat Sink
5
5
1
0
75
4
3
2
1
0LFM
200LFM
400LFM
70
LOAD CURRENT (A)
5
LOAD CURRENT (A)
6
2
0
80 85 90 95 100 105 110 115
AMBIENT TEMPERATURE (°C)
60 65 70 75 80 85 90 95 100 105 110
AMBIENT TEMPERATURE (°C)
Figure 13. 12VIN to 3.3VOUT without
Heat Sink
6
6
5
5
4
3
2
65
0
0LFM
200LFM
400LFM
60 65 70 75 80 85 90 95 100 105 110
AMBIENT TEMPERATURE (°C)
4618 F15
4618 F14
Figure 14. 12VIN to 3.3VOUT with
Heat Sink
3
2
0
70 75 80 85 90 95 100 105
AMBIENT TEMPERATURE (°C)
Figure 15. 24VIN to 3.3VOUT
without Heat Sink
2
4
1
0LFM
200LFM
400LFM
60
3
4618 F13
LOAD CURRENT (A)
LOAD CURRENT (A)
Figure 12. 12VIN to 1.5VOUT with
Heat Sink
0
80 85 90 95 100 105 110 115
AMBIENT TEMPERATURE (°C)
4
1
0LFM
200LFM
400LFM
4618 F12
1
75
Figure 11. 12VIN to 1.5VOUT
without Heat Sink
6
3
70
4618 F11
6
4
0LFM
200LFM
400LFM
4618 F10
Figure 9. 5VIN to 1.5VOUT without
Heat Sink
LOAD CURRENT (A)
3
1
0LFM
200LFM
400LFM
70
4
0LFM
200LFM
400LFM
60
65
70 75 80 85 90 95 100 105
AMBIENT TEMPERATURE (°C)
4618 F16
Figure 16. 24VIN to 3.3VOUT with
Heat Sink
4618f
16
LTM4618
APPLICATIONS INFORMATION
Table 2. 1.5V Output
DERATING CURVE
VIN (V)
POWER LOSS CURVE
AIRFLOW (LFM)
HEAT SINK
ΘJA (°C/W)
Figures 9, 11
5, 12
Figure 7
0
None
16
Figures 9, 11
5, 12
Figure 7
200
None
12.2
Figures 9, 11
5, 12
Figure 7
400
None
11.2
Figures 10, 12
5, 12
Figure 7
0
BGA Heat Sink
15.2
Figures 10, 12
5, 12
Figure 7
200
BGA Heat Sink
11.6
Figures 10, 12
5, 12
Figure 7
400
BGA Heat Sink
10.7
DERATING CURVE
VIN (V)
POWER LOSS CURVE
AIRFLOW (LFM)
HEAT SINK
ΘJA (°C/W)
Figures 13, 15
12, 24
Figure 8
0
None
15
Figures 13, 15
12, 24
Figure 8
200
None
11.2
Figures 13, 15
12, 24
Figure 8
400
None
10.2
Figures 14, 16
12, 24
Figure 8
0
BGA Heat Sink
14.2
Figures 14, 16
12, 24
Figure 8
200
BGA Heat Sink
10.6
Figures 14, 16
12, 24
Figure 8
400
BGA Heat Sink
9.7
Table 3. 3.3V Output
Heat Sink Used: 15 × 9 Version of Aavid #375424B000346
Table 4. Output Voltage Response vs Component Matrix (Refer to Figure 21) 0A to 3A Load Step
VOUT (V)
CIN
(CERAMIC)
CIN
(BULK)
COUT1
(CERAMIC)
COUT2
(BULK)
COMP
C2
(pF)
FREQ
(kHz)
DROOP P-P DEVIATION
(mV)
(mV)
1
22μF × 2
68μF
100μF × 4
None
None
100
400
38
1
22μF × 2
68μF
100μF × 2
220μF
None
None
400
35
RECOVERY
TIME (μs)
LOAD STEP
(A/μs)
RFB
(kΩ)
76
35
3
242
70
35
3
242
1
22μF × 2
68μF
100μF
470μF
None
None
400
30
60
35
3
242
1.2
22μF × 2
68μF
100μF × 4
None
None
47
400
40
80
30
3
121
1.2
22μF × 2
68μF
100μF × 2
220μF
None
None
400
37
74
35
3
121
1.2
22μF × 2
68μF
100μF
470μF
None
None
400
27
54
35
3
121
1.5
22μF × 2
68μF
100μF × 3
None
None
47
500
48
96
36
3
68.1
1.5
22μF × 2
68μF
100μF
220μF
None
None
500
40
80
36
3
68.1
1.5
22μF × 2
68μF
100μF
470μF
None
None
500
30
60
40
3
68.1
1.8
22μF × 2
68μF
100μF × 3
None
None
47
500
52
104
36
3
48.7
1.8
22μF × 2
68μF
100μF
220μF
None
None
500
45
90
35
3
48.7
1.8
22μF × 2
68μF
100μF × 4
None
None
47
500
50
100
35
3
48.7
2.5
22μF × 2
68μF
100μF × 3
None
None
47
500
65
130
38
3
28
2.5
22μF × 2
68μF
100μF × 4
None
None
None
600
75
150
35
3
28
2.5
22μF × 2
68μF
100μF
220μF
None
None
600
60
120
45
3
28
3.3
22μF × 2
68μF
100μF × 2
None
None
22
600
90
180
36
3
19.1
3.3
22μF × 2
68μF
100μF × 2
None
None
47
600
80
160
40
3
19.1
5
22μF × 2
68μF
100μF
None
None
47
600
150
300
40
3
11.5
4618f
17
LTM4618
APPLICATIONS INFORMATION
VISHAY INLP1616BZERR22M01
0.22μH
π FILTER
VIN
6V TO 26.5V
10μF
s2
CIN
10μF
s2
VIN
C1
0.1μF
R1
¥ R2 ´
r 1.22V
VIN • ¦
§ R1 R2 µ¶
INTVCC
VIN
MODE/PLLIN
EXTVCC
FREQ
VOUT
COMP
LTM4618
VFB
TK/SS
RUN
SGND PGND
PGOOD
C2
47pF
VOUT
COUT 3.3V/6A
100μF
s3
19.1k
SW
4618 F17
RSNUB
1.2Ω 0805
R2
CSNUB
470pF
0805, 50V
Figure 17. 6V to 26.5V Input, 3.3V at 6A Design,
Meeting CISPR25 Conducted and CISPR22 Radiated EMI Solution
10dB/μV
PER DIV
150kHz
100MHz
VIDEO BANDWIDTH
4618 F18
Figure 18. VIN 26.5V, VOUT 3.3V, IOUT 5A,
π Filter 20μF to 0.22μH Vishay (1616BZ) to 20μF
CISPR25 Conducted Emissions
55
CISPR22
CLASS A
45
35
25
15
5
AMPLITUDE (dBμV/m)
AMPLITUDE (dBμV/m)
55
45
CISPR22
CLASS B
35
25
15
5
0
100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
0
100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
4618 F19a
4618 F19b
Figure 19. VIN 26.5V, VOUT 3.3V, IOUT 5A,
π Filter 20μF to 0.22μH Vishay (1616BZ) to 20μF
CISPR22 Radiated EMI Plots
4618f
18
LTM4618
APPLICATIONS INFORMATION
EMI Section
The LTM4618 has been evaluated for CISPR22 A and B
Radiated EMI and CISPR25 Conducted EMI. The CISPR25
Conducted EMI test was performed with an input π filter
as shown in Figure 17. An RC snubber circuit is optionally
used from the SW pin to the PGND pin to improve the higher
frequency attenuation and EMI limit guard band. Figure 18
shows the CISPR25 conducted emissions plot for 26.5V
input to 3.3V output at 5A load. Several conditions were
evaluated, and Figure 18 results are from the worst-case
condition. The input π filter is used to attenuate the reflected
noise from the regulator input, and is primarily utilized
when the power regulators are closed to the input power
feed to a board, like the input power connectors. If the
regulator design is placed out on the center of the system
board, then the input π filter may not be needed because
all of the extra board capacitance and the inductive planes
will provide filtering for reflected emissions. If the system
board has noise sensitive circuitry that is powered from
the same voltage rail as the regulators are, then an input
π filter is a good idea to keep regulator noise from corrupting the noise sensitive circuitry on the system board.
Figure 19 shows the CISPR22 B Radiated EMI plots. The
input π filter is used to attenuate the reflected noise from
propagating out onto the input power cables, thus possibly causing radiated EMI issues. An RC snubber circuit
is optionally used from the SW pin to the PGND pin to
improve the higher frequency attenuation and EMI limit
guard band. A placeholder can accommodate the RSNUB
and CSNUB components with 1.2Ω and 470pF. These
components are probably not necessary, but can be used
or adjusted to improve the radiated limit guard bands at
the higher frequencies by attenuating any switch node
ringing due to parasitic values in the high speed switching
paths. It is important to follow the recommended layout
guidelines and use good X5R or X7R ceramic capacitors
to get good results.
• Use large PCB copper areas for high current path,
including VIN, PGND and VOUT. It helps to minimize
the PCB conduction loss and thermal stress.
• Test points can be placed on signal pin for monitoring during testing.
• Place high frequency ceramic input and output
capacitors next to the VIN, PGND and VOUT pins to
minimize high frequency noise.
• Place a dedicated power ground layer underneath the
unit.
• To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers.
• Do not put vias directly on the pad, unless they are
capped.
• Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND
to PGND underneath the unit.
Figure 20 gives a good example of the recommended
layout.
VIN
PGND
7
6
5
4
3
CNTRL
2
1
A
B
C
D
E
CNTRL
G
H
J
K
L
M
COUT
Layout Checklist/Example
The high integration of LTM4618 makes the PC board layout
very simple and easy. However, to optimize its electrical
and thermal performance, some layout considerations
are still necessary.
F
COUT
PGND
VOUT
4618 F20
Figure 20. Recommended PCB Layout Example
4618f
19
LTM4618
TYPICAL APPLICATIONS
31.6k
VIN
6V TO 26.5V
VIN
¥ R2 ´
VIN • ¦
r 1.22V
§ R1 R2 µ¶
UVLO FUNCTION
CIN
10μF
s2
C1
0.1μF
INTVCC
VIN
MODE/PLLIN
EXTVCC
FREQ
10k
VOUT
COMP
VFB
TK/SS
28.7k
PGOOD
RUN
R1
SGND
VOUT
COUT 2.5V/6A
100μF
s3
C2
47pF
LTM4618
PGND
4618 F21
R2
Figure 21. Typical 6V to 26.5V Input, 2.5V at 6A Design, 500kHz Operation
CLOCK SYNC
0° PHASE
PGOOD
VIN
VIN
6V TO 26.5V
CIN1
10μF
MODE/PLLIN
FREQ
VOUT
COMP
LTM4618
VFB
TK/SS
C3 ON/OFF
0.47μF
RUN
SGND
R5
165k
C5
0.1μF
INTVCC
PGND EXTVCC
C4
47pF
R4
14.3k
VOUT
2.5V/12A
COUT
100μF
s4
V+
OUT1
LTC6908-1
OUT2
GND
SET
CLOCK SYNC
180° PHASE
PGOOD
VIN
MOD
2-PHASE OSCILLATOR
CIN2
10μF
MODE/PLLIN
FREQ
VOUT
COMP
LTM4618
WITH CLOCK SYNC,
SOFT-START THE REGULATOR FOR APPROXIMATELY 100ms
100ms • 2 • 1.3μA
C3 0.8V
VFB
TK/SS
RUN
SGND
INTVCC
PGND EXTVCC
4618 F22
Figure 22. Two LTM4618 Parallel, 2.5V at 12A Design
4618f
20
ISOLATED
INTERMEDIATE BUS
R1
19.1k
TK/SS
COMP
CIN2
10μF
RUN
TK/SS
COMP
C7
100μF
35V OPT
VFB
VOUT
FREQ
R2
19.1k
C2
22pF
R1
11.5k
C1
47pF
COUT2
100μF
s2
R9
28.7k
R8
60.4k
R11
48.7k
R10
60.4k
VOUT1
VOUT2
3.3V/6A
COUT1
100μF
VOUT1
5V/6A
VOUT1
4-PHASE OSCILLATOR
SET
V+
U5 MOD
DIV
LTC6902
GND
PH
OUT4
OUT1
OUT3
OUT2
CIN4
10μF
ON/OFF
CIN3
10μF
C8
0.1μF
RUN
TK/SS
COMP
VFB
INTVCC
PGND EXTVCC
LTM4618
VOUT
FREQ
CLOCK SYNC 4
MODE/PLLIN
SGND
VFB
INTVCC
PGND EXTVCC
LTM4618
VOUT
FREQ
CLOCK SYNC 3
MODE/PLLIN
SGND
PGOOD
VIN
RUN
TK/SS
COMP
PGOOD
VIN
Figure 23. 4-Phase, Four Outputs (5V, 3.3V, 2.5V and 1.8V) with Tracking
INTVCC
PGND EXTVCC
LTM4618
MODE/PLLIN
CLOCK SYNC 2
INTVCC
PGND EXTVCC
VFB
VOUT
FREQ
CLOCK SYNC 1
LTM4618
SGND
PGOOD
VIN
+
MODE/PLLIN
SGND
PGOOD
VIN
C6 ON/OFF
0.22μF
RUN
CIN1
10μF
VIN
6V to 26.5V
R5
60.4k
VOUT1
48V
INPUT
R6
68.1k
R4
48.7k
C4
47pF
R3
28.7k
C3
47pF
4618 F23
COUT4
100μF
s3
VOUT4
1.8V/6A
VOUT3
2.5V/6A
COUT3
100μF
s3
LTM4618
TYPICAL APPLICATIONS
4618f
21
LTM4618
PACKAGE PHOTOGRAPH
PACKAGE DESCRIPTION
Pin Assignment Tables
(Arranged by Pin Function)
PIN NAME
PIN NAME
PIN NAME
PIN NAME
A1
A2
A3
A4
A5
A6
A7
N/C
FREQ
MODE/PLLIN
PGND
VIN
VIN
VIN
D1
D2
D3
D4
D5
D6
D7
VFB
PGOOD
INTVCC
PGND
PGND
PGND
PGND
G1
G2
G3
G4
G5
G6
G7
PGND
PGND
PGND
PGND
PGND
PGND
PGND
K1
K2
K3
K4
K5
K6
K7
VOUT
VOUT
VOUT
VOUT
PGND
SW
PGND
B1
B2
B3
B4
B5
B6
B7
TK/SS
RUN
SGND
PGND
VIN
VIN
VIN
E1
E2
E3
E4
E5
E6
E7
PGND
PGND
PGND
PGND
PGND
PGND
PGND
H1
H2
H3
H4
H5
H6
H7
PGND
PGND
PGND
PGND
PGND
PGND
PGND
L1
L2
L3
L4
L5
L6
L7
VOUT
VOUT
VOUT
VOUT
PGND
PGND
PGND
C1
C2
C3
C4
C5
C6
C7
COMP
SGND
SGND
EXTVCC
VIN
VIN
VIN
F1
F2
F3
F4
F5
F6
F7
PGND
PGND
PGND
PGND
PGND
PGND
PGND
J1
J2
J3
J4
J5
J6
J7
VOUT
VOUT
VOUT
VOUT
PGND
PGND
PGND
M1
M2
M3
M4
M5
M6
M7
VOUT
VOUT
VOUT
VOUT
PGND
PGND
PGND
4618f
22
4
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
2.540
1.270
2.540
SUGGESTED PCB LAYOUT
TOP VIEW
0.000
0.315
0.315
PACKAGE TOP VIEW
9.00
BSC
1.270
PAD “A1”
CORNER
3.810
3.810
aaa Z
Y
X
6.985
5.715
4.445
3.175
1.905
0.635
0.000
0.635
1.905
3.175
4.445
5.715
6.985
15.00
BSC
aaa Z
bbb Z
DETAIL B
4.22 – 4.42
DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
4
SYMBOL TOLERANCE
0.15
aaa
bbb
0.10
eee
0.05
6. THE TOTAL NUMBER OF PADS: 84
5. PRIMARY DATUM -Z- IS SEATING PLANE
LAND DESIGNATION PER JESD MO-222
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
DETAIL A
0.27 – 0.37
SUBSTRATE
eee S X Y
DETAIL B
0.630 ±0.025 SQ. 83x
3.95 – 4.05
MOLD
CAP
Z
(Reference LTC DWG # 05-08-1842 Rev Ø)
LGA Package
84-Lead (15mm × 9mm × 4.32mm)
TRAY PIN 1
BEVEL
COMPONENT
PIN “A1”
3s CHAMFER
0.22 s 45°
12.70
BSC
7
7.620
BSC
5
4
3
1.27
BSC
2
LTMXXXXXX
μModule
PACKAGE BOTTOM VIEW
6
1
M
L
K
J
H
G
F
E
D
C
B
A
LGA 84 0409 REV Ø
3
PADS
SEE NOTES
DIA (0.630)
PAD 1
PACKAGE IN TRAY LOADING ORIENTATION
DETAIL A
LTM4618
PACKAGE DESCRIPTION
4618f
23
LTM4618
TYPICAL APPLICATION
5V Input, 2.5V at 6A Design, 500kHz Operation
31.6k
VIN 5V
4.5V ≤ VIN ≤ 6V
VIN
CIN
10μF
s2
C1
0.1μF
R1
¥ R2 ´
r 1.22V
VIN • ¦
§ R1 R2 µ¶
INTVCC
VIN
MODE/PLLIN
EXTVCC
FREQ
VOUT
COMP
LTM4618
VFB
TK/SS
PGOOD
RUN
SGND
10k
C2
47pF
VOUT
COUT 2.5V/6A
100μF
s3
28.7k
PGND
4618 TA02
UVLO FUNCTION
R2
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTM4603
6A DC/DC μModule Regulator with PLL
and Output Tracking/Margining
4.5V to 20V Input, 0.6V to 5V Output, 15mm × 15mm × 2.8mm LGA Package
LTM4604A
4A DC/DC μModule Regulator
2.375V to 5.5V Input, 0.8V to 5V Output, Tracking
LTM4608A
8A DC/DC μModule Regulator
2.7V to 5.5V Input, 0.6V to 5V Output, PLL, Tracking
LTM4612
36VIN DC/DC μModule Regulator
4.5V to 36V Input, 3.3V to 15V Output, PLL, Tracking, Margining
LTM4619
Dual 4A DC/DC μModule Regulator
4.5V to 26.5V Input, Dual 0.8V to 5V Output, PLL, Tracking
LTM8025
36VIN, 3A DC/DC μModule Regulator
3.6V ≤ VIN ≤ 36V; 0.8V ≤ VOUT ≤ 24V; 9mm × 15mm × 4.32mm LGA Package
4618f
24 Linear Technology Corporation
LT 0710 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2010