BUK9880-55A N-channel TrenchMOS logic level FET Rev. 02 — 12 April 2007 Product data sheet 1. Product profile 1.1 General description N-channel enhancement mode power Field-Effect Transistor (FET) in a plastic package using NXP General Purpose Automotive (GPA) TrenchMOS technology. 1.2 Features n Very low on-state resistance n 150 °C rated n Q101 compliant n Logic level compatible 1.3 Applications n Automotive systems n Motors, lamps and solenoids n General purpose power switching n 12 V and 24 V loads 1.4 Quick reference data n EDS(AL)S ≤ 36 mJ n ID ≤ 7 A n RDSon = 68 mΩ (typ) n Ptot ≤ 8 W 2. Pinning information Table 1. Pinning Pin Description 1 gate (G) 2 drain (D) 3 source (S) 4 solder point; connected to drain (D) Simplified outline Symbol D 4 G 1 2 3 SOT223 (SC-73) mbb076 S BUK9880-55A NXP Semiconductors N-channel TrenchMOS logic level FET 3. Ordering information Table 2. Ordering information Type number BUK9880-55A Package Name Description Version SC-73 plastic surface-mounted package with increased heatsink; 4 leads SOT223 4. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS drain-source voltage VDGR drain-gate voltage (DC) VGS gate-source voltage ID drain current Conditions RGS = 20 kΩ Min Max Unit - 55 V - 55 V - ±15 V Tsp = 25 °C; VGS = 5 V; see Figure 2 and 3 - 7 A Tsp = 100 °C; VGS = 5 V; see Figure 2 - 4 A IDM peak drain current Tsp = 25 °C; pulsed; tp ≤ 10 µs; see Figure 3 - 30 A Ptot total power dissipation Tsp = 25 °C; see Figure 1 - 8 W Tstg storage temperature −55 +150 °C Tj junction temperature −55 +150 °C Source-drain diode IDR reverse drain current Tsp = 25 °C - 7 A IDRM peak reverse drain current Tsp = 25 °C; pulsed; tp ≤ 10 µs - 30 A - 36 mJ - - Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche unclamped inductive load; ID = 6 A; VDS ≤ 55 V; energy RGS = 50 Ω; VGS = 5 V; starting at Tj = 25 °C EDS(AL)R repetitive drain-source avalanche energy [1] [1] Conditions: a) Maximum value not quoted. Repetitive rating defined in Figure 16. b) Single-pulse avalanche rating limited by Tj(max) of 150 °C. c) Repetitive avalanche rating limited by an average junction temperature of 145 °C. d) Refer to application note AN10273 for further information. BUK9880-55A_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 12 April 2007 2 of 12 BUK9880-55A NXP Semiconductors N-channel TrenchMOS logic level FET 03aa17 120 003aab787 8 ID (A) Pder (%) 6 80 4 40 2 0 0 50 100 150 Tsp (°C) 0 200 0 50 100 150 200 Tsp (°C) VGS ≥ 5 V P tot P der = ------------------------ × 100 % P tot ( 25°C ) Fig 1. Normalized total power dissipation as a function of solder point temperature Fig 2. Continuous drain current as a function of solder point temperature 03nc54 103 ID (A) 102 RDSon = VDS / ID tp = 10 µs 10 100 µs 1 ms 1 tp δ= T P DC 10 ms 100 ms 10-1 t tp T 10-2 10-1 1 10 102 VDS (V) Tsp = 25 °C; IDM is single pulse. Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage BUK9880-55A_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 12 April 2007 3 of 12 BUK9880-55A NXP Semiconductors N-channel TrenchMOS logic level FET 5. Thermal characteristics Table 4. Thermal characteristics Symbol Parameter Rth(j-a) Rth(j-sp) Conditions Min Typ Max Unit thermal resistance from junction to ambient - 70 - K/W thermal resistance from junction to solder point - - 15 K/W 03nc55 102 Zth(j-sp) (K/W) 10 δ = 0.5 0.2 1 0.1 0.05 δ= P 0.02 tp T 10-1 Single Shot t tp T 10-2 10-6 10-5 10-4 10-3 10-2 10-1 1 10 tp (s) 102 Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration BUK9880-55A_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 12 April 2007 4 of 12 BUK9880-55A NXP Semiconductors N-channel TrenchMOS logic level FET 6. Characteristics Table 5. Characteristics Tj = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Tj = 25 °C 55 - - V Tj = −55 °C 50 - - V Static characteristics V(BR)DSS VGS(th) IDSS drain-source breakdown voltage ID = 250 µA; VGS = 0 V gate-source threshold voltage drain leakage current ID = 1 mA; VDS = VGS; see Figure 9 and 10 Tj = 25 °C 1 1.5 2 V Tj = 150 °C 0.6 - - V Tj = −55 °C - - 2.3 V VDS = 55 V; VGS = 0 V Tj = 25 °C - 0.05 10 µA Tj = 150 °C - - 500 µA - 2 100 nA VGS = ±10 V; VDS = 0 V IGSS gate leakage current RDSon drain-source on-state resistance VGS = 5 V; ID = 8 A; see Figure 7 and 8 Tj = 25 °C - 68 80 mΩ Tj = 150 °C - - 147 mΩ VGS = 4.5 V; ID = 8 A - - 89 mΩ VGS = 10 V; ID = 8 A - 62 73 mΩ ID = 10 A; VDD = 44 V; VGS = 5 V; see Figure 14 - 11 - nC - 1.6 - nC - 4.6 - nC - 438 584 pF - 87 104 pF - 62 85 pF - 8 - ns Dynamic characteristics QG(tot) total gate charge QGS gate-source charge QGD gate-drain charge Ciss input capacitance Coss output capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz; see Figure 12 Crss reverse transfer capacitance td(on) turn-on delay time tr rise time - 118 - ns td(off) turn-off delay time - 20 - ns tf fall time - 32 - ns VDS = 30 V; RL = 1.2 Ω; VGS = 5 V; RG = 10 Ω Source-drain diode VSD source-drain voltage IS = 15 A; VGS = 0 V; see Figure 15 - 0.85 1.2 V trr reverse recovery time - 33 - ns Qr recovered charge IS = 20 A; dIS/dt = −100 A/µs; VGS = −10 V; VR = 30 V - 60 - nC BUK9880-55A_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 12 April 2007 5 of 12 BUK9880-55A NXP Semiconductors N-channel TrenchMOS logic level FET 03nc51 60 ID (A) 03nc50 80 VGS (V) = 10 RDSon (mΩ) 7 6 40 5 60 4 20 3.4 3 2.4 2.2 0 40 0 2 4 6 8 VDS (V) 10 Tj = 25 °C 4 6 8 VGS (V) 10 Tj = 25 °C; ID = 10 A Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values 03nc52 180 RDSon (mΩ) 150 2 3 3.2 3.4 3.6 3.8 4 Fig 6. Drain-source on-state resistance as a function of gate-source voltage; typical values 03nc24 2 a 1.8 VGS (V) = 5 1.6 1.4 120 1.2 1 90 0.8 60 0.6 0.4 30 0.2 0 0 10 20 30 ID (A) 40 Tj = 25 °C 0 -60 20 60 100 140 180 Tj (°C) R DSon a = ----------------------------R DSon ( 25°C ) Fig 7. Drain-source on-state resistance as a function of drain current; typical values Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature BUK9880-55A_2 Product data sheet -20 © NXP B.V. 2007. All rights reserved. Rev. 02 — 12 April 2007 6 of 12 BUK9880-55A NXP Semiconductors N-channel TrenchMOS logic level FET 03aa33 2.5 VGS(th) (V) 2 1.5 03aa36 10-1 ID (A) max 10-2 typ 10-3 min max 10-4 min 1 typ 10-5 0.5 0 -60 10-6 0 60 120 Tj (°C) 180 0 1 2 3 VGS (V) Tj = 25 °C; VDS = VGS ID = 1 mA; VDS = VGS Fig 9. Gate-source threshold voltage as a function of junction temperature 03nc48 12 Fig 10. Sub-threshold drain current as a function of gate-source voltage 10 1200 C (pF) 1000 8 800 gfs (S) 03nc53 Ciss 6 600 4 400 2 200 Coss Crss 0 0 5 10 15 ID (A) 20 Tj = 25 °C; VDS = 25 V 0 10-2 1 10 VDS (V) 102 VGS = 0 V; f = 1 MHz Fig 11. Forward transconductance as a function of drain current; typical values Fig 12. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values BUK9880-55A_2 Product data sheet 10-1 © NXP B.V. 2007. All rights reserved. Rev. 02 — 12 April 2007 7 of 12 BUK9880-55A NXP Semiconductors N-channel TrenchMOS logic level FET 03nc49 15 03nc47 5 VGS (V) ID (A) 4 10 VDS = 14 V 3 VDS = 44 V 2 5 Tj = 150 °C 1 Tj = 25 °C 0 0 0 1 2 3 4 VGS (V) 0 5 10 QG (nC) 15 Tj = 25 °C; ID = 10 A VDS = 25 V Fig 13. Transfer characteristics: drain current as a function of gate-source voltage; typical values Fig 14. Gate-source voltage as a function of gate charge; typical values 03nc46 60 003aab771 10 IAL (A) IS (A) (1) 1 40 (2) (3) 10-1 20 Tj = 150 °C Tj = 25 °C 0 0.0 0.5 1.0 1.5 VSD (V) 2.0 VGS = 0 V 10-2 10-3 10-2 10-1 1 tAL (ms) 10 See Table note 1 of Table 3 “Limiting values”. (1) Single-pulse; Tj = 25 °C. (2) Single-pulse; Tj = 125 °C. (3) Repetitive. Fig 15. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values Fig 16. Single-pulse and repetitive avalanche rating; avalanche current as a function of avalanche time BUK9880-55A_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 12 April 2007 8 of 12 BUK9880-55A NXP Semiconductors N-channel TrenchMOS logic level FET 7. Package outline Plastic surface-mounted package with increased heatsink; 4 leads D SOT223 E B A X c y HE v M A b1 4 Q A A1 1 2 3 Lp bp e1 w M B detail X e 0 2 4 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp b1 c D E e e1 HE Lp Q v w y mm 1.8 1.5 0.10 0.01 0.80 0.60 3.1 2.9 0.32 0.22 6.7 6.3 3.7 3.3 4.6 2.3 7.3 6.7 1.1 0.7 0.95 0.85 0.2 0.1 0.1 OUTLINE VERSION REFERENCES IEC SOT223 JEDEC JEITA SC-73 EUROPEAN PROJECTION ISSUE DATE 04-11-10 06-03-16 Fig 17. Package outline SOT223 (SC-73) BUK9880-55A_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 12 April 2007 9 of 12 BUK9880-55A NXP Semiconductors N-channel TrenchMOS logic level FET 8. Revision history Table 6. Revision history Document ID Release date Data sheet status Change notice Supersedes BUK9880-55A_2 20070412 Product data sheet - BUK9880_55A-01 Modifications: BUK9880_55A-01 (9397 750 07736) • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Section 4 “Limiting values”: corrected VGS value from ±10 V to ±15 V. 20010207 Product specification BUK9880-55A_2 Product data sheet - - © NXP B.V. 2007. All rights reserved. Rev. 02 — 12 April 2007 10 of 12 BUK9880-55A NXP Semiconductors N-channel TrenchMOS logic level FET 9. Legal information 9.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 9.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS — is a trademark of NXP B.V. 10. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] BUK9880-55A_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 12 April 2007 11 of 12 BUK9880-55A NXP Semiconductors N-channel TrenchMOS logic level FET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 11 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . 11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 12 April 2007 Document identifier: BUK9880-55A_2