CYPRESS CY7C421

CY7C421512 × 9 Asynchronous FIFO
CY7C421
512 × 9 Asynchronous FIFO
512 × 9 Asynchronous FIFO
Features
■
Asynchronous First-In First-Out (FIFO) Buffer Memories
❐ 512 × 9 (CY7C421)
■
Dual-Ported RAM Cell
■
High Speed 50 MHz Read and Write Independent of Depth and
Width
■
Low Operating Power: ICC = 35 mA
■
Empty and Full Flags (Half Full Flag in Standalone)
■
TTL Compatible
■
Retransmit in Standalone
■
Expandable in Width
■
PLCC, 7 × 7 TQFP, 300-Mil Molded SOJ
■
Pb-free Packages Available
■
Pin Compatible and Functionally Equivalent to IDT7201, and
AM7201
data is read in the same sequential order that it was written. Full
and empty flags are provided to prevent overflow and underflow.
Three additional pins are also provided to facilitate unlimited
expansion in width, depth, or both. The depth expansion
technique steers the control signals from one device to another
in parallel. This eliminates the serial addition of propagation
delays, so that throughput is not reduced. Data is steered in a
similar manner.
The read and write operations may be asynchronous; each can
occur at a rate of 50 MHz. The write operation occurs when the
write (W) signal is LOW. Read occurs when read (R) goes LOW.
The nine data outputs go to the high impedance state when R is
HIGH.
A Half Full (HF) output flag that is valid in the standalone and
width expansion configurations is provided. In the depth
expansion configuration, this pin provides the expansion out
(XO) information that is used to tell the next FIFO that it is
activated.
Functional Description
The CY7C421 is a first-in first-out (FIFO) memory offered in
300-mil wide SOJ, TQFP & PLCC packages and it is 512 words
by 9 bits wide. Each FIFO memory is organized such that the
In the standalone and width expansion configurations, a LOW on
the retransmit (RT) input causes the FIFO to retransmit the data.
Read enable (R) and write enable (W) must both be HIGH during
retransmit, and then R is used to access the data.
The CY7C421 is fabricated using an advanced 0.65-micron
P-well CMOS technology. Input ESD protection is greater than
2000 V and latch up is prevented by careful layout and guard
rings.
Selection Guide
512 × 9
-15
-20
Frequency (MHz)
40
33.3
Maximum Access Time (ns)
15
20
ICC1 (mA)
35
35
Cypress Semiconductor Corporation
Document Number: 38-06001 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 7, 2012
CY7C421
Logic Block Diagram
DATA INPUTS
(D0–D 8)
W
WRITE
CONTROL
RAM ARRAY
512 x 9
WRITE
POINTER
READ
POINTER
THREESTATE
BUFFERS
DATA OUTPUTS
(Q0–Q 8)
R
RESET
LOGIC
READ
CONTROL
FLAG
LOGIC
XI
Document Number: 38-06001 Rev. *H
EXPANSION
LOGIC
MR
FL/RT
EF
FF
XO/HF
Page 2 of 21
CY7C421
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Maximum Ratings ............................................................. 6
Operating Range ............................................................... 6
Electrical Characteristics ................................................. 6
Electrical Characteristics ................................................. 6
Capacitance ...................................................................... 6
AC Test Loads and Waveforms ....................................... 7
Switching Characteristics ................................................ 8
Switching Waveforms ...................................................... 9
Architecture .................................................................... 13
Dual-Port RAM .......................................................... 13
Resetting the FIFO .................................................... 13
Writing Data to the FIFO ........................................... 13
Reading Data from the FIFO ..................................... 13
Document Number: 38-06001 Rev. *H
Standalone/Width Expansion Modes ........................ 13
Depth Expansion Mode ............................................. 13
Use of the Empty and Full Flags ............................... 14
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Diagrams .......................................................... 16
Acronyms ........................................................................ 19
Document Conventions ................................................. 19
Units of Measure ....................................................... 19
Document History Page ................................................. 20
Sales, Solutions, and Legal Information ...................... 21
Worldwide Sales and Design Support ....................... 21
Products .................................................................... 21
PSoC Solutions ......................................................... 21
Page 3 of 21
CY7C421
Pin Configurations
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
D4
D5
D6
D7
FL/RT
MR
EF
XO/HF
Q7
Q6
Q5
Q4
32 3130 29 28 27 26 25
D1
D0
NC
NC
XI
FF
Q0
Q1
1
2
3
4
5
6
7
8
Document Number: 38-06001 Rev. *H
24
23
22
21
20
19
18
17
7C421
D7
FL/RT
NC
NC
MR
EF
XO/HF
Q7
9 10 11 12 13 14 15 16
R
Q2
Q3
Q8
GND
R
Q4
1
2
3
4
5
6
7
7C421
8
9
10
11
12
13
14
Q6
XO/HF
Q7
Q6
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
Q3
Q8
GND
Q5
D3
D8
W
NC
Vcc
D4
D5
D6
D7
NC
FL/RT
MR
EF
Q3
Q8
GND
NC
R
Q4
Q5
D2
D1
D0
XI
FF
Q0
Q1
NC
Q2
4 3 2 1 323130
5
29
6
28
7
27
8
26
7C421
9
25
10
24
11
23
12
22
13
21
14 15 1617 181920
D5
D6
Figure 3. 32-pIn TQFP (Top View)
D3
D8
W
VCC
D4
Figure 2. 28-pin DIP (Top View)
D2
Figure 1. 32-pin PLCC/LCC (Top View)
Page 4 of 21
CY7C421
Pin Definitions
Signal Name
Description
I/O
Function
W
Write Signal
I
Write into the FIFO
R
Read Signal
I
Read from the FIFO
D0–D8
Input Data
I
Data into the FIFO
Q0–Q8
Output Data
O Data Out from the FIFO
XI
Expansion In
I
XO
Expansion Out
O Cascaded: Connected to XI of next device
Non-Cascaded: Connected to VCC
HF
Half Full Flag
O Half-full flag: When HF is LOW, half of the FIFO is full.
FF
Full Flag
O When FF is LOW, the FIFO is full.
EF
Empty Flag
O When EF is LOW, the FIFO is empty.
MR
Master Reset
I
FIFO Reset
RT
Retransmit
I
Causes FIFO to retransmit the data
FL
First Load
I
Width expansion: Connected to VCC
Depth expansion: when Gnd indicates that part is first to be loaded all others connected to
VCC
VCC
Power
I
Voltage Supply
GND
Ground
I
Ground
Document Number: 38-06001 Rev. *H
Cascaded: Connected to XO of pervious device
Non-Cascaded: Connected to VCC
Page 5 of 21
CY7C421
Maximum Ratings
Power Dissipation ........................................................ 1.0 W
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.[1]
Storage Temperature ............................... –65 °C to +150 °C
Ambient Temperature
with Power Applied .................................. –55 °C to +125 °C
Supply Voltage to Ground Potential .............–0.5 V to +7.0 V
DC Voltage Applied to Outputs
in High Z State .............................................–0.5 V to +7.0 V
DC Input Voltage .........................................–0.5 V to +7.0 V
Output Current, into Outputs (LOW) ........................... 20 mA
Static Discharge Voltage
(per MIL–STD–883, Method 3015) ......................... > 2000 V
Latch Up Current ................................................... > 200 mA
Operating Range
Range
Ambient Temperature[2]
VCC
0 °C to +70 °C
5 V  10%
–40 °C to +85 °C
5 V  10%
Commercial
Industrial
Electrical Characteristics
Over the Operating Range
Parameter
Description
VOH
VOL
VIH
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
VIL
IIX
IOZ
IOS
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Output Short Circuit Current [4]
All Speed Grades
Test Conditions
Min
2.4
–
2.0
2.2
VCC = Min, IOH = –2.0 mA
VCC = Min, IOL = 8.0 mA
Commercial
Industrial
Max
–
0.4
VCC
VCC
0.8
+10
+10
–90
[3]
GND < VI < VCC
R > VIH, GND < VO < VCC
VCC = Max, VOUT = GND
–10
–10
–
Unit
V
V
V
V
A
A
mA
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
ICC
Operating Current
VCC = Max, IOUT = 0 mA,
f = fMAX
ICC1
Operating Current
ISB1
Standby Current
VCC = Max, IOUT = 0 mA,
f = 20 MHz
All Inputs = VIH Min
ISB2
Power Down Current
All Inputs > VCC – 0.2 V
-15
-20
Commercial
Industrial
Commercial
Min
–
–
–
Max
65
100
35
Min
–
–
–
Max
55
90
35
Commercial
Industrial
Commercial
Industrial
–
–
–
–
10
15
5
8
–
–
–
–
10
15
5
8
Unit
mA
mA
mA
mA
Capacitance
Parameter [5]
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = 4.5 V
Max
6
6
Unit
pF
pF
Notes
1. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power up.
2. TA is the “instant on” case temperature.
3. VIL(Min) = –2.0 V for pulse durations of less than 20 ns.
4. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
5. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-06001 Rev. *H
Page 6 of 21
CY7C421
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
R1 500 
5V
R1 500 
5V
OUTPUT
ALL INPUT PULSES
3.0 V
OUTPUT
R2
333 
30 pF
INCLUDING
JIGAND
SCOPE
(a)
R2
333 
5 pF
INCLUDING
JIGAND
SCOPE
GND
 3 ns
90%
10%
90%
10%
 3 ns
(b)
Equivalent to:
THÉVENIN EQUIVALENT
200
OUTPUT
2V
Document Number: 38-06001 Rev. *H
Page 7 of 21
CY7C421
Switching Characteristics
Over the Operating Range
Parameter [6]
tRC
tA
tRR
tPR
tLZR[7]
tDVR[7, 8]
tHZR[7, 8]
tWC
tPW
tHWZ[7]
tWR
tSD
tHD
tMRSC
tPMR
tRMR
tRPW
tWPW
tRTC
tPRT
tRTR
tEFL
tHFH
tFFH
tREF
tRFF
tWEF
tWFF
tWHF
tRHF
tRAE
tRPE
tWAF
tWPF
tXOL
tXOH
Description
Read Cycle Time
Access Time
Read Recovery Time
Read Pulse Width
Read LOW to Low Z
Data Valid after Read HIGH
Read HIGH to High Z
Write Cycle Time
Write Pulse Width
Write HIGH to Low Z
Write Recovery Time
Data Setup Time
Data Hold Time
MR Cycle Time
MR Pulse Width
MR Recovery Time
Read HIGH to MR HIGH
Write HIGH to MR HIGH
Retransmit Cycle Time
Retransmit Pulse Width
Retransmit Recovery Time
MR to EF LOW
MR to HF HIGH
MR to FF HIGH
Read LOW to EF LOW
Read HIGH to FF HIGH
Write HIGH to EF HIGH
Write LOW to FF LOW
Write LOW to HF LOW
Read HIGH to HF HIGH
Effective Read from Write HIGH
Effective Read Pulse Width after EF HIGH
Effective Write from Read HIGH
Effective Write Pulse Width after FF HIGH
Expansion Out LOW Delay from Clock
Expansion Out HIGH Delay from Clock
-15
Min
25
–
10
15
3
5
–
25
15
5
10
8
0
25
15
10
15
15
25
15
10
–
–
–
–
–
–
–
–
–
–
15
–
15
–
–
-20
Max
–
15
–
–
–
–
15
–
–
–
–
–
–
–
–
–
–
–
–
–
–
25
25
25
15
15
15
15
15
15
15
–
15
–
15
15
Min
30
–
10
20
3
5
–
30
20
5
10
12
0
30
20
10
20
20
30
20
10
–
–
–
–
–
–
–
–
–
–
20
–
20
–
–
Max
–
20
–
–
–
–
15
–
–
–
–
–
–
–
–
–
–
–
–
–
–
30
30
30
20
20
20
20
20
20
20
–
20
–
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V and output loading of the specified IOL/IOH and 30 pF load capacitance,
as in part (a) of Figure 4 on page 7, unless otherwise specified.
7. tHZR transition is measured at +200 mV from VOL and –200 mV from VOH. tDVR transition is measured at the 1.5V level. tHWZ and tLZR transition is measured at
100 mV from the steady state.
8. tHZR and tDVR use capacitance loading as in part (b) of Figure 4 on page 7.
Document Number: 38-06001 Rev. *H
Page 8 of 21
CY7C421
Switching Waveforms
Figure 5. Asynchronous Read and Write
tA
R
tRC
tPR
tA
tRR
tLZR
tDVR
tHZR
DATA VALID
Q0–Q 8
tPW
tWC
DATA VALID
tWR
W
tSD
tHD
DATA VALID
D0–D 8
DATA VALID
Figure 6. Master Reset
tMRSC [10]
tPMR
MR
R, W [9]
tRPW
tWPW
tEFL
tRMR
EF
tHFH
HF
tFFH
FF
Figure 7. Half-full Flag
HALF FULL
HALF FULL+1
HALF FULL
W
tRHF
R
tWHF
HF
Notes
9. W and R  VIH around the rising edge of MR.
10. tMRSC = tPMR + tRMR.
Document Number: 38-06001 Rev. *H
Page 9 of 21
CY7C421
Switching Waveforms (continued)
Figure 8. Last Write to First Read Full Flag
R
LAST WRITE
FIRST READ
ADDITIONAL
READS
FIRST WRITE
W
tRFF
tWFF
FF
Figure 9. Last Read to First Write Empty Flag
W
LAST READ
FIRST WRITE
ADDITIONAL
WRITES
FIRST READ
R
tWEF
tREF
EF
tA
Q0–Q8
VALID
VALID
Figure 10. Retransmit [11]
tRTC[12]
FL/RT
tPRT
R,W
tRTR
Notes
11. EF, HF and FF may change state during retransmit as a result of the offset of the read and write pointers, but flags are valid at tRTC.
12. tRTC = tPRT + tRTR.
Document Number: 38-06001 Rev. *H
Page 10 of 21
CY7C421
Switching Waveforms (continued)
Figure 11. Empty Flag and Read Data Flow-through Mode
D0–D8
W
tRAE
R
tREF
EF
tWEF
tHWZ
tRPE
tA
Q0–Q8
DATA VALID
Figure 12. Full Flag and Write Data Flow-through Mode
R
tWAF
tWPF
W
tRFF
tWFF
FF
tHD
D0–D8
DATA VALID
tA
Q0–Q8
tSD
DATA VALID
Document Number: 38-06001 Rev. *H
Page 11 of 21
CY7C421
Switching Waveforms (continued)
Figure 13. Expansion Timing Diagrams
WRITE TO LAST PHYSICAL
LOCATION OF DEVICE 1
WRITE TO FIRST PHYSICAL
LOCATION OF DEVICE 2
W
tWR
tXOL
XO1(XI2)[13]
tXOH
tSD
tHD
DATA VALID
D0–D 8
READ FROM LAST PHYSICAL
LOCATION OF DEVICE 1
tHD
tSD
DATA VALID
READ FROM FIRST PHYSICAL
LOCATION OF DEVICE 2
R
tRR
[13]
tXOL
tXOH
XO1(XI2)
tHZR
tLZR
tDVR
tDVR
DATA
VALID
Q0–Q 8
tA
DATA
VALID
tA
Note
13. Expansion Out of device 1 (XO1) is connected to Expansion In of device 2 (XI2).
Document Number: 38-06001 Rev. *H
Page 12 of 21
CY7C421
Architecture
Reading Data from the FIFO
The CY7C421 FIFO consist of an array of 512 words of 9 bits
each (implemented by an array of dual-port RAM cells), a read
pointer, a write pointer, control signals (W, R, XI, XO, FL, RT,
MR), and Full, Half Full, and Empty flags.
The falling edge of R initiates a read cycle provided EF is not
LOW. Data outputs (Q0–Q8) are in a high impedance condition
between read operations (R HIGH), when the FIFO is empty, or
when the FIFO is not the active device in the depth expansion
mode.
Dual-Port RAM
The dual-port RAM architecture refers to the basic memory cell
used in the RAM. The cell itself enables the read and write
operations to be independent of each other, which is necessary
to achieve truly asynchronous operation of the inputs and
outputs. A second benefit is that the time required to increment
the read and write pointers is much less than the time required
for data propagation through the memory, which is the case if
memory is implemented using the conventional register array
architecture.
Resetting the FIFO
Upon power up, the FIFO must be reset with a Master Reset
(MR) cycle. This causes the FIFO to enter the empty condition
signified by the Empty flag (EF) being LOW, and both the Half
Full (HF) and Full flags (FF) being HIGH. Read (R) and write (W)
must be HIGH tRPW/tWPW before and tRMR after the rising edge
of MR for a valid reset cycle. If reading from the FIFO after a reset
cycle is attempted, the outputs are in the high impedance state.
Writing Data to the FIFO
The availability of at least one empty location is indicated by a
HIGH FF. The falling edge of W initiates a write cycle. Data
appearing at the inputs (D0–D8) tSD before and tHD after the
rising edge of W are stored sequentially in the FIFO.
The EF LOW-to-HIGH transition occurs tWEF after the first
LOW-to-HIGH transition of W for an empty FIFO. HF goes LOW
tWHF after the falling edge of W following the FIFO actually being
Half Full. Therefore, the HF is active after the FIFO is filled to half
its capacity plus one word. HF remains LOW while less than one
half of total memory is available for writing. The LOW-to-HIGH
transition of HF occurs tRHF after the rising edge of R when the
FIFO goes from half full +1 to half full. HF is available in
standalone and width expansion modes. FF goes LOW tWFF
after the falling edge of W, during the cycle in which the last
available location is filled. Internal logic prevents FIFO overflow.
Writes to a full FIFO are ignored and the write pointer is not
incremented. FF goes HIGH tRFF after a read from a full FIFO.
When one word is in the FIFO, the falling edge of R initiates a
HIGH-to-LOW transition of EF. The rising edge of R causes the
data outputs to go to the high impedance state and remain such
until a write is performed. Reads to an empty FIFO are ignored
and do not increment the read pointer. From the empty condition,
the FIFO can be read tWEF after a valid write.
The retransmit feature is beneficial when transferring packets of
data. It enables the receiver to acknowledge receipt of data and
retransmit, if necessary.
The Retransmit (RT) input is active in the standalone and width
expansion modes. The retransmit feature is intended for use
when a number of writes equal to or less than the depth of the
FIFO have occurred since the last MR cycle. A LOW pulse on RT
resets the internal read pointer to the first physical location of the
FIFO. R and W must both be HIGH for tPRT and tRTR after
retransmit is asserted. With every read cycle after retransmit, the
data from the first physical location of FIFO is read until the read
pointer equals write pointer. Full, Half Full, and Empty flags are
governed by the relative locations of the read and write pointers
and are updated during a retransmit cycle. Data written to the
FIFO after activation of RT are also transmitted. Full depth of
FIFO data can be repeatedly retransmitted.
Standalone/Width Expansion Modes
Standalone and width expansion modes are set by grounding
Expansion In (XI) and tying First Load (FL) to VCC. FIFOs can be
expanded in width to provide word widths greater than nine in
increments of nine. During width expansion mode, all control line
inputs are common to all devices, and flag outputs from any
device can be monitored.
Depth Expansion Mode
Depth expansion mode (see Figure 14 on page 14) is entered
when, during a MR cycle, Expansion Out (XO) of one device is
connected to Expansion In (XI) of the next device, with XO of the
last device connected to XI of the first device. In the depth
expansion mode the First Load (FL) input, when grounded,
indicates that this part is the first to be loaded. All other devices
must have this pin HIGH. To enable the correct FIFO, XO is
pulsed LOW when the last physical location of the previous FIFO
is written to and pulsed LOW again when the last physical
location is read. Only one FIFO is enabled for read and one for
write at any particular time. All other devices are in standby.
FIFOs can also be expanded simultaneously in depth and width.
Consequently, any depth or width FIFO can be created of word
widths in increments of 9. When expanding in depth, a composite
FF must be created by ORing the FFs together. Likewise, a
composite EF is created by ORing the EFs together. HF and RT
functions are not available in depth expansion mode.
Document Number: 38-06001 Rev. *H
Page 13 of 21
CY7C421
Use of the Empty and Full Flags
For example, consider an empty FIFO that is receiving read
pulses. Because the FIFO is empty, the read pulses are ignored
by the FIFO, and nothing happens. Next, a single word is written
into the FIFO, with a signal that is asynchronous to the read
signal. The (internal) state machine in the FIFO goes from empty
to empty+1. However, it does this asynchronously with respect
to the read signal, so that the effective pulse width of the read
signal cannot be determined, because the state machine does
not look at the read signal until it goes to the empty+1 state.
Similarly, the minimum write pulse width may be violated by
trying to write into a full FIFO, and asynchronously performing a
read. The empty and full flags are used to avoid these effective
pulse width violations, but to do this and operate at the maximum
frequency, the flag must be valid at the beginning of the next
cycle.
To achieve maximum frequency, the flags must be valid at the
beginning of the next cycle. However, because they can be
updated by either edge of the read or write signal, they must be
valid by one-half of a cycle. Cypress FIFOs meet this
requirement.
The reason for why the flags should be valid by the next cycle is
complex. The “effective pulse width violation” phenomenon can
occur at the full and empty boundary conditions, if the flags are
not properly used. The empty flag must be used to prevent
reading from an empty FIFO and the full flag must be used to
prevent writing into a full FIFO.
Figure 14. Depth Expansion
XO
R
W
FF
9
EF
9
9
Q
CY7C421
D
FL
VCC
XI
XO
FULL
EF
FF
EMPTY
9
CY7C421
FL
XI
XO
*
FF
EF
9
CY7C421
MR
FL
XI
* FIRST DEVICE
Document Number: 38-06001 Rev. *H
Page 14 of 21
CY7C421
Ordering Information
Speed
(ns)
Package
Diagram
Ordering Code
Package Type
Operating
Range
15
CY7C421-15AXC
51-85063
32-pin Thin Quad Flat Pack (Pb-free)
Commercial
20
CY7C421-20JXC
51-85002
32-pin Plastic Leaded Chip Carriers (Pb-free)
Commercial
CY7C421-20VXC
51-85031
28-pin (300 Mils) Molded Small Outline J-Lead (Pb-free)
CY7C421-20JXI
51-85002
32-pin Plastic Leaded Chip Carrier (Pb-free)
Industrial
Ordering Code Definitions
CY 7 C 4
2
1 - XX
X
X
X
Temperature Range: X = C or I
C = Commercial; I = Industrial
X = Pb-free (RoHS Compliant)
Package Type: X = A or J or V
A = 32-pin TQFP
J = 32-pin PLCC
V = 28-pin Molded SOJ
Speed: XX = 15 ns or 20 ns
Depth: 1 = 512
Width: 2 = × 9
4 = FIFO
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-06001 Rev. *H
Page 15 of 21
CY7C421
Package Diagrams
Figure 15. 32-pin TQFP (7 × 7 × 1.0 mm) A3210 Package Outline, 51-85063
51-85063 *D
Document Number: 38-06001 Rev. *H
Page 16 of 21
CY7C421
Package Diagrams (continued)
Figure 16. 32-pin PLCC (0.453 × 0.553 Inches) J32 Package Outline, 51-85002
51-85002 *D
Document Number: 38-06001 Rev. *H
Page 17 of 21
CY7C421
Package Diagrams (continued)
Figure 17. 28-pin SOJ (300 Mils) V28.3 (Molded SOJ V21) Package Outline, 51-85031
51-85031 *E
Document Number: 38-06001 Rev. *H
Page 18 of 21
CY7C421
Acronyms
Acronym
Document Conventions
Description
Units of Measure
DIP
dual in-line package
FIFO
first-in first-out
°C
degree Celsius
I/O
input/output
MHz
megahertz
LCC
leadless chip carrier
µA
microampere
PLCC
plastic leaded chip carrier
mA
milliampere
RAM
random access memory
mm
millimeter
SOJ
small outline J-lead
mV
millivolt
TQFP
thin quad flat pack
ns
nanosecond
TTL
transistor-transistor logic
%
percent
pF
picofarad
V
volt
W
watt
Document Number: 38-06001 Rev. *H
Symbol
Unit of Measure
Page 19 of 21
CY7C421
Document History Page
Document Title: CY7C421, 512 × 9 Asynchronous FIFO
Document Number: 38-06001
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
106462
SZV
07/11/01
Change from Spec Number: 38-00079 to 38-06001
*A
122332
RBI
12/30/02
Updated Maximum Ratings (Added power up requirements).
*B
383597
PCX
See ECN
Added Pb-Free Logo
Updated Ordering Information (Added in Ordering Information:
CY7C419–10JXC, CY7C419–15JXC, CY7C419-15VXC, CY7C421–10JXC,
CY7C421–15AXC, CY7C421–20JXC, CY7C421–20VXC, CY7C425–10AXC,
CY7C425–10JXC, CY7C425–15JXC, CY7C425–20JXC, CY7C425–20VXC,
CY7C429–10AXC, CY7C429–15JXC, CY7C429–20JXC, CY7C433–10AXC,
CY7C433–10JXC, CY7C433–15JXC, CY7C433–20AXC, CY7C433–20JXC).
*C
2623658
VKN /
PYRS
12/17/08
Updated Ordering Information (Added CY7C421-20JXI, removed
CY7C419/25/29/33 from the ordering information table).
Removed 26-Lead CerDIP, 32-Lead RLCC, 28-Lead molded DIP packages
from the data sheet
Removed Military Information
*D
2714768
VKN /
AESA
06/04/2009
Corrected defective Logic Block diagram, Pinouts, and Package diagrams
*E
2896039
RAME
03/19/2010
Added Contents.
Updated Ordering Information (Removed inactive parts from the data sheet).
Updated Package Diagrams.
Updated links in Sales, Solutions, and Legal Information
*F
3110157
ADMU
12/14/2010
Added Ordering Code Definitions.
*G
3324980
ADMU
07/26/2011
Updated title to read as “CY7C421, 512 × 9 Asynchronous FIFO”.
Updated Features.
Updated Functional Description (Removed information about
CY7C420/424/425/428/429/432/433).
Updated Selection Guide (Removed speed bins -10, -25, -30, -40 and -65).
Updated Electrical Characteristics (Removed speed bins -10, -25, -30, -40 and
-65).
Updated Switching Characteristics (Removed speed bins -10, -25, -30, -40 and
-65).
Updated Architecture (Removed information about
CY7C420/424/425/428/429/432/433).
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Updated in new template.
*H
3697624
SMCH
08/07/2012
Added Pin Definitions.
Updated Architecture (Updated Reading Data from the FIFO (description)).
Document Number: 38-06001 Rev. *H
Description of Change
Page 20 of 21
CY7C421
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
cypress.com/go/memory
cypress.com/go/image
PSoC
Touch Sensing
cypress.com/go/psoc
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2001-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-06001 Rev. *H
Revised August 7, 2012
All products and company names mentioned in this document may be the trademarks of their respective holders.
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