LH5496/96H FEATURES • Fast Access Times: 15 */20/25/35/50/65/80 ns CMOS 512 × 9 FIFO PIN CONNECTIONS 28-PIN PDIP TOP VIEW 1 28 VCC D8 2 27 D4 D3 3 26 D5 D2 4 25 D6 D1 5 24 D7 • Full, Half-Full, and Empty Status Flags D0 6 23 FL/RT • Read Retransmit Capability XI 7 22 RS FF 8 21 EF Q0 9 20 XO/HF Q1 10 19 Q7 W • Full CMOS Dual Port Memory Array • Fully Asynchronous Read and Write • Expandable-in Width and Depth • TTL Compatible I/O • Packages: 28-Pin, 300-mil PDIP 28-Pin, 600-mil PDIP 32-Pin PLCC Q2 11 18 Q6 Q3 12 17 Q5 Q8 13 16 Q4 VSS 14 15 R 5496-1D • Pin and Functionally Compatible with IDT7201 Figure 1. Pin Connections for PDIP Packages FUNCTIONAL DESCRIPTION The LH5496/96H are dual port memories with internal addressing to implement a First-In, First-Out algorithm. Through an advanced dual port architecture, they provide fully asynchronous read/write operation. Empty, Full, and Half-Full status flags are provided to prevent data overflow and underflow. In addition, internal logic provides for unlimited expansion in both word size and depth. 32-PIN PLCC D0 7 27 NC Read and write operations automatically access sequential locations in memory in that data is read out in the same order that it was written, that is on a First-In, First-Out basis. Since the address sequence is internally predefined, no external address information is required for the operation of this device. A ninth data bit is provided for parity or control information often needed in communication applications. XI 8 26 FL/RT RS W NC VCC 2 1 32 31 30 D5 D8 3 D4 D3 4 D2 5 29 D6 D1 6 28 D7 FF 9 25 Q0 10 24 EF Q1 11 23 XO/HF NC 12 22 Q7 Q2 13 21 Q6 Q5 Q4 R NC VSS Q8 14 15 16 17 18 19 20 Q3 Empty, Full, and Half-Full status flags monitor the extent to which data has been written into the FIFO, and prevent improper operations (i.e., Read if the FIFO is empty, or Write if the FIFO is full). A retransmit feature resets the Read address pointer to its initial position, thereby allowing repetitive readout of the same data. Expansion In and Expansion Out pins implement an expansion scheme that allows individual FIFOs to be cascaded to greater depth without incurring additional latency (bubblethrough) delays. TOP VIEW 5496-2D Figure 2. Pin Connections for PLCC Package * LH5496 only. 1 CMOS 512 × 9 FIFO LH5496/96H RS RESET LOGIC W INPUT PORT CONTROL DATA INPUTS D0 - D8 WRITE POINTER OUTPUT PORT CONTROL DUAL-PORT RAM ARRAY R READ POINTER 512 x 9 ... DATA OUTPUTS Q0 - Q8 EF FF FLAG LOGIC FL/RT XI EXPANSION LOGIC XO/HF 5496-3 Figure 3. LH5496/96H Block Diagram PIN DESCRIPTIONS PIN PIN TYPE * D0 – D8 I Q0 – Q8 O/Z DESCRIPTION PIN TYPE * DESCRIPTION Input Data Bus XO/HF O Expansion Out/Half-Full Flag Output Data Bus XI I Expansion In W I Write Request FL/RT I First Load/Retransmit R I Read Request RS I Reset EF O Empty Flag VCC V Positive Power Supply FF O Full Flag VSS V Ground * I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level 2 PIN CMOS 512 × 9 FIFO LH5496/96H ABSOLUTE MAXIMUM RATINGS 1 PARAMETER RATING Supply Voltage to VSS Potential –0.5 V to 7 V Signal Pin Voltage to VSS Potential 3 –0.5 V to VCC + 0.5 V (not to exceed 7 V) DC Output Current 2 ±50 mA Storage Temperature Range –65oC to 150oC Power Dissipation (Package Limit) 1.0 W DC Voltage Applied To Outputs In High-Z State –0.5 V to Vcc + 0.5 V (not to exceed 7 V) NOTES: 1. Stresses greater than those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device. This is a device stress rating for transient conditions only. Functional operation at these or any other conditions above those indicated in the ‘Operating Range’ of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time. 3. Negative undershoots of 1.5 V in amplitude are permitted for up to 10 ns once per cycle. OPERATING RANGE SYMBOL PARAMETER MIN MAX UNIT 0 70 oC TA Temperature, Ambient, LH5496 TA Temperature, Ambient, LH5496H –40 85 oC VCC Supply Voltage 4.5 5.5 V VSS Supply Voltage 0 0 V –0.5 0.8 V 2.0 VCC + 0.5 V VIL Logic ‘0’ Input Voltage VIH Logic ‘1’ Input Voltage 1 NOTE: 1. Negative undershoots of 1.5 V in amplitude are permitted for up to 10 ns once per cycle. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT ILI Input Leakage Current VCC = 5.5 V, VIN = 0 V to VCC –10 10 µA ILO Output Leakage Current R ≥ V IH, 0 V ≤ VOUT ≤ VCC –10 10 µA VOH Output High Voltage IOH = –2.0 mA 2.4 VOL Output Low Voltage ICC ICC2 ICC3 Average Supply Current 1 Average Standby Current Power Down Current 1 1 V IOL = 8.0 mA 0.4 V Measured at f = 40 MHz 100 mA All Inputs = VIH 15 mA All Inputs = VCC – 0.2 V 5 mA NOTE: 1. ICC, ICC2, and ICC3 are dependent upon actual output loading and cycle rates. Specified values are with outputs open. 3 CMOS 512 × 9 FIFO LH5496/96H AC TEST CONDITIONS PARAMETER Input Pulse Levels RATING Input Rise and Fall Times (10% to 90%) 5 ns Input Timing Reference Levels 1.5 V Output Reference Levels 1.5 V Output Load, Timing Tests Figure 4 CAPACITANCE 1,2 PARAMETER 1.1 k Ω DEVICE UNDER TEST 680 Ω * 30 pF * INCLUDES JIG & SCOPE CAPACITANCES RATING CIN (Input Capacitance) 5 pF COUT (Output Capacitance) 7 pF NOTES: 1. Sample tested only. 2. Capacitances are maximum values at 25oC measured at 1.0 MHz with VIN = 0 V. 4 +5 V VSS to 3 V Figure 4. Output Load Circuit 5496-4 CMOS 512 × 9 FIFO LH5496/96H AC ELECTRICAL CHARACTERISTICS 1 (Over Operating Range) tA = 15 ns 2 tA = 20 ns tA = 25 ns tA = 35 ns tA = 50 ns tA = 65 ns SYMBOL PARAMETER MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tA = 80 ns MIN MAX UNIT READ CYCLE TIMING tRC Read Cycle Time 25 – 30 – 35 – 45 – 65 – 80 – 100 – ns tA Access Time – 15 – 20 – 25 – 35 – 50 – 65 – 80 ns tRR Read Recover Time 10 – 10 – 10 – 10 – 15 – 15 – 15 – ns tRPW Read Pulse Width 3 15 – 20 – 25 – 35 – 50 – 65 – 80 – ns tRLZ Data Bus Active from Read LOW 4 5 – 5 – 5 – 5 – 5 – 5 – 10 – ns tWLZ Data Bus Active from Write HIGH 4,5 10 – 10 – 10 – 10 – 10 – 10 – 20 – ns tDV Data Valid from Read Pulse HIGH 5 – 5 – 5 – 5 – 5 – 5 – 5 – ns tRHZ Data Bus High-Z from Read 4 HIGH – 15 – 15 – 15 – 15 – 20 – 30 – 30 ns tWC Write Cycle Time 25 – 30 – 35 – 45 – 65 – 80 – 100 – ns WRITE CYCLE TIMING 3 tWPW Write Pulse Width 15 – 20 – 25 – 35 – 50 – 65 – 80 – ns tWR Write Recovery Time 10 – 10 – 10 – 10 – 15 – 15 – 15 – ns tDS Data Setup Time 10 – 10 – 10 – 15 – 20 – 20 – 20 – ns tDH Data Hold Time 0 – 0 – 0 – 0 – 0 – 5 – 5 – ns RESET TIMING tRSC Reset Cycle Time 3 25 – 30 – 35 – 45 – 65 – 80 – 100 – ns tRS Reset Pulse Width 15 – 20 – 25 – 35 – 50 – 65 – 80 – ns tRSR Reset Recovery Time 10 – 10 – 10 – 10 – 15 – 15 – 15 – ns tRRSS Read HIGH to RS HIGH 15 – 20 – 25 – 35 – 50 – 65 – 80 – ns tWRSS Write HIGH to RS HIGH 15 – 20 – 25 – 35 – 50 – 65 – 80 – ns RETRANSMIT TIMING tRTC Retransmit Cycle Time 25 – 30 – 35 – 45 – 65 – 80 – 100 – ns tRT Retransmit Pulse Width 3 15 – 20 – 25 – 35 – 50 – 65 – 80 – ns tRTR Retransmit Recovery Time 10 – 10 – 10 – 10 – 15 – 15 – 15 – ns tEFL Reset LOW to Empty Flag LOW – 25 – 30 – 35 – 45 – 65 – 80 – 100 ns tHFH,FFH Reset LOW to Half-Full and Full Flags HIGH – 25 – 30 – 35 – 45 – 65 – 80 – 100 ns tREF Read LOW to Empty Flag LOW – 20 – 25 – 25 – 35 – 45 – 60 – 60 ns tRFF Read HIGH to Full Flag HIGH – 20 – 25 – 25 – 35 – 45 – 60 – 60 ns tWEF Write HIGH to Empty Flag HIGH – 20 – 25 – 25 – 35 – 45 – 60 – 60 ns tWFF Write LOW to Full Flag LOW – 20 – 25 – 25 – 35 – 45 – 60 – 60 ns tWHF Write LOW to Half-Full Flag LOW – 25 – 30 – 35 – 45 – 65 – 80 – 100 ns tRHF Read HIGH to Half-Full Flag HIGH – 25 – 30 – 35 – 45 – 65 – 80 – 100 ns tXOL Expansion Out LOW – 18 – 35 – 50 – 65 – 80 ns tXOH Expansion Out HIGH – tXI Expansion In Pulse Width 15 tXIR Expansion In Recovery Time tXIS Expansion in Setup Time FLAG TIMING EXPANSION TIMING – 20 – 25 18 – – 20 20 – 25 – 35 – 50 – 65 – 80 ns – 25 – 35 – 50 – 65 – 80 – ns 10 – 7 – 10 – 10 – 10 – 10 – 10 – 10 – ns 10 – 10 – 15 – 15 – 15 – 15 – ns NOTES: 1. LH5496 only. 2. All timing measurements performed at ‘AC Test Condition’ levels. 5 CMOS 512 × 9 FIFO LH5496/96H OPERATIONAL DESCRIPTION Reset The device is reset whenever the Reset pin (RS) is taken to a LOW state. The reset operation initializes both the read and write address pointers to the first memory location. The XI and FL pins are also sampled at this time to determine whether the device is in Single mode or Depth Expansion mode. A reset pulse is required when the device is first powered up. The Read (R) and Write (W) pins may be in any state when reset is initiated, but must be brought to a HIGH state tRPW and tWPW before the rising edge of RS. The reset operation forces the Empty Flag EF to be asserted (EF = LOW), and the Half-Full Flag HF and the Full FLag FF to be deasserted (HF = FF = HIGH); the Data Out pins (D0 – D8) are forced into a high-impedance state. Write A write cycle is initiated on the falling edge of the Write (W) pin. Data setup and hold times must be observed on the data in (D0 – D8) pins. A write operation is only possible if the FIFO is not full, (i.e. the Full flag pin is HIGH). Writes may occur independently of any ongoing read opertations. At the falling edge of the first write after the memory is half filled, the Half-Full flag will be asserted (HF = LOW) and will remain asserted until the difference between the write pointer and read pointer indicates that the remaining data in the device is less than or equal to one half the total capacity of the FIFO. The Half-Full flag is deasserted (HF = HIGH) by the appropriate rising edge of R. The Full flag is asserted (FF = LOW) at the falling edge of the write operation which fills the last available location in the FIFO memory array. The Full flag will inhibit further writes until cleared by a valid read. The Full flag is deasserted (FF = HIGH) after the next rising edge of R releases another memory location. Read A read cycle is initiated on the falling edge of the Read (R) pin. Read data becomes valid on the data out (Q0–Q8) pins after a time tA from the falling edge of R. After R goes HIGH, the data out pins return to a high-impedance state. Reads may occur independent of any ongoing write operations. A read is only possible if the FIFO is not empty (EF = HIGH). 6 The internal read and write address pointers are maintained by the device such that consecutive read operations will access data in the same order as it was written. The Empty flag is asserted (EF = LOW) after the falling edge of R which accesses the last available data in the FIFO memory. EF is deasserted (EF = HIGH) after the next rising edge of W loads another word of valid data. Data Flow-Through Read flow-through mode occurs when the Read (R) pin is brought LOW while the FIFO is empty, and held LOW in anticipation of a write cycle. At the end of the next write cycle, the Empty flag will be momentarily deasserted, and the data just written will become available on the data out pins after a maximum time of tWEF + tA. Additional writes may occur while the R pin remains LOW, but only data from the first write flows through to the outputs. Additional data, if any, can only be accessed by toggling R. Write flow-through mode occurs when the Write (W) pin is brought LOW while the FIFO is full, and held LOW in anticipation of a read cycle. At the end of the read cycle, the Full flag will be momentarily deasserted, but then immediately reasserted in response to W held LOW. Data is written into the FIFO on the rising edge of W which may occur tRFF + tWPW after the read. Retransmit The FIFO can be made to reread previously read data through the retransmit function. Retransmit is initiated by pulsing RT LOW. This resets the internal read address pointer to the first physical location in the memory while leaving the internal write address pointer unchanged. Data between the read and write pointers may be reaccessed by subsequent reads. Both R and W must be inactive (HIGH) during the retransmit pulse. Retransmit is useful if no more than 512 writes are performed between resets. Retransmit may affect the status of EF, HF, and FF flags, depending on the relocation of the read pointer. This function is not available in depth expansion mode. CMOS 512 × 9 FIFO LH5496/96H TIMING DIAGRAMS t RSC t RS RS R,W t RRSS t WRSS t RSR tEFL EF t FFH , t HFH FF,HF NOTES: 1. tRSC = tRS + tRSR. 2. W and R ≥ VIH around the rising edge of RS. 3. The Data Out pins (D0 - D8) are forced into a high-impedance state whenever EF = LOW. 5496-14 Figure 5. Reset Timing t RPW t RC t RR tA tA R t RLZ t RHZ t DV Q0 - Q8 VALID DATA OUT VALID DATA OUT t WC t WR t WPW W t DS D0 - D 8 t DH VALID DATA IN VALID DATA IN 5496-5 Figure 6. Asynchronous Write and Read Operation 7 CMOS 512 × 9 FIFO LH5496/96H TIMING DIAGRAMS (cont’d) LAST WRITE FIRST READ R W t WFF t RFF FF 5496-6 Figure 7. Full Flag from Last Write to First Read LAST READ FIRST WRITE W R t REF t WEF EF NOTE: The Data Out pins (D0 - D8) are forced into a high-impedance state whenever EF = LOW. Figure 8. Empty Flag from Last Read to First Write 8 5496-7 CMOS 512 × 9 FIFO LH5496/96H TIMING DIAGRAMS (cont’d) VALID DATA IN D0 - D 8 W tRPE R EF t REF t WEF t WLZ tA VALID DATA OUT Q0 - Q 8 NOTES: 1. tRPE = tRPW 2. tRPE: Effective Read Pulse Width after Empty Flag HIGH. 3. The Data Out pins (D0 - D8) are forced into a high-impedance state whenever EF = LOW. 5496-8 Figure 9. Read Data Flow-Through R tWPF W t RFF FF t WFF t DS t DH VALID DATA IN D0 - D 8 tA Q0 - Q8 VALID DATA OUT NOTES: 1. tWPF = tWPW 2. tWPF: Effective Write Pulse Width after Full Flag HIGH. 5496-9 Figure 10. Write Data Flow-Through 9 CMOS 512 × 9 FIFO LH5496/96H TIMING DIAGRAMS (cont’d) W t WEF EF t RPE R NOTES: 1. tRPE = tRPW 2. tRPE: Effective Read Pulse Width after Empty Flag HIGH. 3. The Data Out pins (D0 - D8) are forced into a high-impedance state whenever EF = LOW. 5496-10 Figure 11. Empty Flag Timing R t RFF FF t WPF W NOTES: 1. tWPF = tWPW 2. tWPF: Effective Write Pulse Width after Full Flag HIGH. 5496-11 Figure 12. Full Flag Timing MORE THAN HALF-FULL HALF-FULL OR LESS HALF-FULL OR LESS W R t WHF tRHF HF 5496-12 10 CMOS 512 × 9 FIFO LH5496/96H TIMING DIAGRAMS (cont’d) t RT RT t RTR R,W NOTES: 1. tRTC = tRT + tRTR 2. EF, HF and FF may change state during retransmit, but flags will be valid at tRTC. 5496-13 Figure 14. Retransmit Timing W WRITE TO LAST AVAILABLE LOCATION READ FROM LAST VALID LOCATION R t XOL t XOH t XOL t XOH XO 5496-15 Figure 15. Expansion Out Timing t XI t XIR XI t XIS W WRITE TO FIRST AVAILABLE LOCATION t XIS READ FROM FIRST VALID LOCATION R 5496-16 Figure 16. Expansion In Timing 11 CMOS 512 × 9 FIFO LH5496/96H OPERATIONAL MODES Width Expansion Single Device Configuration Word-width expansion is implemented by placing multiple LH5496/96H devices in parallel. Each LH5496/96H should be configured for standalone mode. In this arrangement, the behavior of the status flags is identical for all devices; so, in principle, a representative value for each of these flags could be derived from any one device. In practice, it is better to derive ‘composite’ flag values using external logic, since there may be minor speed variations between different actual devices. (See Figures 17 and 18.) When depth expansion is not required for the given application, the device is placed in Single mode by tying the Expansion In pin (XI) to ground. This pin is internally sampled during reset. HF DATA IN D0 - D8 R W WRITE 9 READ 9 DATA OUT Q0 - Q8 LH5496/96H FULL FLAG RESET FF EF RS RT EMPTY FLAG RETRANSMIT XI 5496-17 Figure 17. Single FIFO (512 × 9) DATA IN 18 HF HF 9 9 WRITE FULL FLAG RESET W FF W LH5496/96H LH5496/96H R READ EF RS RS XI R RT RT 9 9 XI EMPTY FLAG RETRANSMIT 18 DATA OUT 5496-18 Figure 18. FIFO Width Expansion (512 × 18) 12 CMOS 512 × 9 FIFO LH5496/96H are shared by all devices, while internal logic controls the steering of data. Only one FIFO will be enabled for any given read cycle, so the common Data Out pins of all devices are wire-ORed together. Likewise, the common Data In pins of all devices are tied together. OPERATIONAL MODES (cont’d) Depth Expansion Depth expansion is implemented by configuring the required number of FIFOs in Expansion mode. In this arrangement, the FIFOs are connected in a circular fashion with the Expansion Out pin (XO) of each device tied to the Expansion In pin (XI) of the next device. One FIFO in this group must be designated as the first load device. This is accomplished by tying the First Load pin (FL) of this device to ground. All other devices must have their FL pin tied to a high level. In this mode, W and R signals In Expansion mode, external logic is required to generate a composite Full or Empty flag. This is achieved by ORing the FF pins of all devices and ORing the EF pins of all devices respectively. The Half-Full flag and Retransmit functions are not available in Depth Expansion mode. XO R W DATA IN D 0 - D8 9 9 9 9 LH5496/96H FF EF RS FL DATA OUT Q 0 - Q8 Vcc XI XO 9 9 FF FULL LH5496/96H RS EF FL EMPTY Vcc XI XO 9 9 FF RS LH5496/96H RS EF FL XI 5496-19 Figure 19. FIFO Depth Expansion (1536 × 9) 13 CMOS 512 × 9 FIFO LH5496/96H OPERATIONAL MODES (cont’d) Compound Expansion A combination of width and depth expansion can be easily implemented by operating groups of depth expanded FIFOs in parallel. Bidirectional Operation LH5496/96H devices in parallel but opposite directions. The Data In pins of a device may be tied to the corresponding Data Out pins of another device operating in the opposite direction to form a single bidirectional bus interface. Care must be taken to assure that the appropriate read, write, and flag signals are routed to each system. Both depth and width expansion may be used in this configuration. Applications which require bidirectional data buffering between two systems can be realized by operating Q0 - Q17 Q0 - Q 8 R W RS DATA IN LH5496/96H DEPTH EXPANSION BLOCK LH5496/96H DEPTH EXPANSION BLOCK D9 - DN-1 D0 - DN-1 Q0 - QN-10 D18 - DN-1 Q0 - QN-1 DATA OUT LH5496/96H DEPTH EXPANSION BLOCK DN-9 - DN-1 5496-20 Figure 20. Compound FIFO Expansion Wa Rb EFb FFa LH5496/96H HFb RTb RS Da0 - 8 Qb0 - 8 XI SYSTEM A SYSTEM B Qa0 - 8 Db0 - 8 Ra EFa Wb LH5496/96H FFb HFa RTa RS XI 5496-21 Figure 21. Bidirectional FIFO Buffer 14 CMOS 512 × 9 FIFO LH5496/96H PACKAGE DIAGRAMS 28SK-DIP (DIP028-P-0300) DETAIL 28 15 7.05 [0.278] 6.65 [0.262] 1 0° TO 15° 14 0.35 [0.014] 0.15 [0.006] 35.00 [1.378] 34.40 [1.354] 3.65 [0.144] 3.25 [0.128] 7.62 [0.300] TYP. 4.40 [0.173] 4.00 [0.157] 3.40 [0.134] 3.00 [0.118] 2.54 [0.100] TYP. DIMENSIONS IN MM [INCHES] 0.51 [0.020] MIN. 0.56 [0.022] 0.36 [0.014] MAXIMUM LIMIT MINIMUM LIMIT 28DIP-1 28-pin, 300-mil PDIP 28DIP (DIP028-P-0600) 28 15 DETAIL 13.45 [0.530] 12.95 [0.510] 1 0° TO 15° 14 0.30 [0.012] 0.20 [0.008] 36.30 [1.429] 35.70 [1.406] 4.50 [0.177] 4.00 [0.157] 15.24 [0.600] TYP. 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 2.54 [0.100] TYP. DIMENSIONS IN MM [INCHES] 0.60 [0.024] 0.40 [0.016] 0.51 [0.020] MIN. MAXIMUM LIMIT MINIMUM LIMIT 28DIP-2 28-pin, 600-mil PDIP 15 CMOS 512 × 9 FIFO LH5496/96H 32PLCC (PLCC32-P-R450) 1.27 [0.050] 4 SIDES BSC 15.11 [0.595] 14.86 [0.585] 13.46 [0.530] 12.45 [0.490] 14.05 [0.553] 13.89 [0.547] 11.51 [0.453] 11.35 [0.447] DETAIL 12.57 [0.495] 12.32 [0.485] 0.10 [0.004] 0.81 [0.032] 0.66 [0.026] 3.56 [0.140] 3.12 [0.123] 2.41 [0.095] 1.52 [0.060] 10.92 [0.430] 9.91 [0.390] 0.38 [0.015] MIN MAXIMUM LIMIT DIMENSIONS IN MM (INCHES) MINIMUM LIMIT 0.53 [0.021] 0.33 [0.013] 32PLCC 32-pin, 450-mil PLCC ORDERING INFORMATION LH5496/96H Device Type X Temperature Range X Package - ## Speed 15 * 20 25 35 Access Time (ns) 50 65 80 Blank 28-pin, 600-mil Plastic DIP (DIP28-P-600) D 28-pin, 300-mil Plastic DIP (DIP28-P-300) U 32-pin Plastic Leaded Chip Carrier (PLCC32-P-R450) Blank Commercial (0° C to 70° C) H Industrial (-40° C to 85° C) CMOS 1K x 9 FIFO * LH5496 only Example: LH5496U-25 (CMOS 512 x 9 FIFO, 32-pin PLCC, 25 ns) 16 5496MD