CY7C1371DV33 18-Mbit (512 K × 36) Flow-Through SRAM with NoBL™ Architecture 18-Mbit (512 K × 36) Flow-Through SRAM with NoBL™ Architecture Features Functional Description ■ No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles ■ Supports up to 133-MHz bus operations with zero wait states ❐ Data is transferred on every clock ■ Pin-compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need to use OE ■ Registered inputs for flow through operation ■ Byte write capability ■ 3.3 V/2.5 V I/O power supply (VDDQ) ■ Fast clock-to-output times ❐ 6.5 ns (for 133-MHz device) ■ Clock enable (CEN) pin to enable clock and suspend operation ■ Synchronous self-timed writes ■ Asynchronous output enable ■ Available in JEDEC-standard Pb-free 100-pin TQFP and 165-ball FBGA packages ■ Three chip enables for simple depth expansion ■ Automatic power-down feature available using ZZ mode or CE deselect ■ IEEE 1149.1 JTAG-compatible boundary scan ■ Burst capability – linear or interleaved burst order ■ Low standby power The CY7C1371DV33 is a 3.3 V, 512 K × 36 synchronous flow through burst SRAM designed specifically to support unlimited true back-to-back read/write operations with no wait state insertion. The CY7C1371DV33 is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the clock enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133-MHz device). Write operations are controlled by the two or four byte write select (BWX) and a write enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous chip enables (CE1, CE2, CE3) and an asynchronous output enable (OE) provide for easy bank selection and output tristate control. To avoid bus contention, the output drivers are synchronously tristated during the data portion of a write sequence. Selection Guide 133 MHz Unit Maximum access time Description 6.5 ns Maximum operating current 210 mA Maximum CMOS standby current 70 mA Cypress Semiconductor Corporation Document Number: 001-75433 Rev. *A • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 26, 2013 CY7C1371DV33 Logic Block Diagram – CY7C1371DV33 ADDRESS REGISTER A0, A1, A A1 D1 A0 D0 MODE CLK CEN C CE ADV/LD C BURST LOGIC Q1 A1' A0' Q0 WRITE ADDRESS REGISTER ADV/LD BW A WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BW B BW C WRITE DRIVERS MEMORY ARRAY S E N S E A M P S BW D WE OE CE1 CE2 CE3 ZZ INPUT REGISTER D A T A S T E E R I N G O U T P U T B U F F E R S DQs DQP A DQP B DQP C DQP D E E READ LOGIC SLEEP CONTROL Document Number: 001-75433 Rev. *A Page 2 of 29 CY7C1371DV33 Contents Pin Configurations ........................................................... 4 Pin Definitions .................................................................. 6 Functional Overview ........................................................ 7 Single Read Accesses ................................................ 7 Burst Read Accesses .................................................. 7 Single Write Accesses ................................................. 7 Burst Write Accesses .................................................. 8 Sleep Mode ................................................................. 8 Interleaved Burst Address Table (MODE = Floating or VDD) .................................................. 8 Linear Burst Address Table (MODE = GND) ............... 8 ZZ Mode Electrical Characteristics .............................. 8 Truth Table ........................................................................ 9 Partial Truth Table for Read/Write .................................. 9 IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 10 Disabling the JTAG Feature ...................................... 10 Test Access Port (TAP) ............................................. 10 PERFORMING A TAP RESET .................................. 10 TAP REGISTERS ...................................................... 10 TAP Instruction Set ................................................... 10 TAP Controller State Diagram ....................................... 12 TAP Controller Block Diagram ...................................... 13 TAP Timing ...................................................................... 13 TAP AC Switching Characteristics ............................... 14 3.3 V TAP AC Test Conditions ....................................... 15 3.3 V TAP AC Output Load Equivalent ......................... 15 2.5 V TAP AC Test Conditions ....................................... 15 2.5 V TAP AC Output Load Equivalent ......................... 15 Document Number: 001-75433 Rev. *A TAP DC Electrical Characteristics and Operating Conditions ..................................................... 15 Identification Register Definitions ................................ 16 Scan Register Sizes ....................................................... 16 Identification Codes ....................................................... 16 Boundary Scan Order .................................................... 17 Maximum Ratings ........................................................... 18 Operating Range ............................................................. 18 Electrical Characteristics ............................................... 18 Capacitance .................................................................... 19 Thermal Resistance ........................................................ 19 AC Test Loads and Waveforms ..................................... 19 Switching Characteristics .............................................. 20 Switching Waveforms .................................................... 21 Ordering Information ...................................................... 24 Ordering Code Definitions ......................................... 24 Package Diagrams .......................................................... 25 Acronyms ........................................................................ 27 Document Conventions ................................................. 27 Units of Measure ....................................................... 27 Document History Page ................................................. 28 Sales, Solutions, and Legal Information ...................... 29 Worldwide Sales and Design Support ....................... 29 Products .................................................................... 29 PSoC Solutions ......................................................... 29 Page 3 of 29 CY7C1371DV33 Pin Configurations Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout A 81 A 82 A 83 A 84 ADV/LD 85 VSS 90 OE VDD 91 86 CE3 92 CEN BWA 93 87 BWB 94 WE BWC 95 88 BWD 96 CLK CE2 97 89 CE1 98 A 42 43 44 45 46 47 48 49 50 NC/36M A A A A A A A 41 NC/72M 40 37 A0 VSS 36 A1 VDD 35 A 39 34 A NC/144M 33 A 38 32 Document Number: 001-75433 Rev. *A NC/288M 31 A BYTE D 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE BYTE C DQPC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD 99 100 A CY7C1371DV33 DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA BYTE B BYTE A Page 4 of 29 CY7C1371DV33 Pin Configurations (continued) Figure 2. 165-ball FBGA (13 × 15 × 1.4 mm) pinout CY7C1371DV33 1 2 3 4 5 6 7 8 A B C D E F G H J K L M N P NC/576M NC/1G A CE1 BWC A CE2 BWD BWB CE3 CEN BWA CLK WE DQPC DQC NC DQC VDDQ VDDQ VSS VDD VSS VSS VSS VSS DQC DQC VDDQ VDD VSS DQC DQC NC DQD DQC VDDQ VDD DQC NC DQD VDDQ NC VDDQ VDD VDD VDD DQD DQD VDDQ DQD DQD VDDQ DQD DQPD DQD NC R MODE NC/144M NC/72M NC/36M 9 10 ADV/LD A A NC OE A A NC VSS VSS VSS VDD VDDQ VDDQ NC DQB DQPB DQB VSS VSS VDD VDDQ DQB DQB VSS VSS VSS VDD DQB VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ VDDQ NC VDDQ DQB VSS VSS VSS DQB NC DQA DQB ZZ DQA VDD VSS VSS VSS VDD VDDQ DQA DQA VDD VSS VSS VSS VDD VDDQ DQA DQA VDDQ VDDQ VDD VSS VSS NC VSS A A A A Document Number: 001-75433 Rev. *A 11 VSS NC VDD VSS VDDQ VDDQ DQA NC DQA DQPA TDI NC A1 TDO A A A NC/288M TMS A0 TCK A A A A Page 5 of 29 CY7C1371DV33 Pin Definitions Name A0, A1, A I/O Description InputAddress inputs used to select one of the address locations. Sampled at the rising edge of the CLK. synchronous A[1:0] are fed to the two-bit burst counter. InputByte write inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising BWA, BWB, BWC, BWD synchronous edge of CLK. WE InputWrite enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal synchronous must be asserted LOW to initiate a write sequence. ADV/LD InputAdvance/load input. Used to advance the on-chip address counter or load a new address. When HIGH synchronous (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD must be driven LOW to load a new address. CLK Input-clock Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. CE1 InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 synchronous and CE3 to select/deselect the device. CE2 InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 synchronous and CE3 to select/deselect the device. CE3 InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 synchronous and CE2 to select/deselect the device. OE InputOutput enable, asynchronous input, active LOW. Combined with the synchronous logic block inside asynchronous the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device has been deselected. CEN InputClock enable input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM. synchronous When deasserted HIGH the Clock signal is masked. While deasserting CEN does not deselect the device, use CEN to extend the previous cycle when required. ZZ InputZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition with asynchronous data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. DQs I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:D] are placed in a tristate condition.The outputs are automatically tristated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. DQPX I/OBidirectional data parity I/O lines. Functionally, these signals are identical to DQs. synchronous MODE Input strap pin Mode input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. VDD Power supply Power supply inputs to the core of the device. VDDQ VSS I/O power supply Ground Power supply for the I/O circuitry. Ground for the device. Document Number: 001-75433 Rev. *A Page 6 of 29 CY7C1371DV33 Pin Definitions (continued) Name I/O Description TDO JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not being used, this pin must be left unconnected. This pin is not available on TQFP packages. output synchronous TDI JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being input used, this pin can be left floating or connected to VDD through a pull up resistor. This pin is not available synchronous on TQFP packages. TMS JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being input used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. synchronous TCK JTAGclock Clock input to the JTAG circuitry. If the JTAG feature is not being used, this pin must be connected to VSS. This pin is not available on TQFP packages. NC – No connects. Not internally connected to the die. NC/(36 M, 72 M, 144 M, 288M, 576M, 1G)are address expansion pins and are not internally connected to the die. Functional Overview The CY7C1371DV33 is a synchronous flow through burst SRAM designed specifically to eliminate wait states during write-read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the clock enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. Maximum access delay from the clock rise (tCDV) is 6.5 ns (133-MHz device). Accesses can be initiated by asserting all three chip enables (CE1, CE2, CE3) active at the rising edge of the clock. If clock enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device is latched. The access can either be a read or write operation, depending on the status of the write enable (WE). BWX can be used to conduct byte write operations. Write operations are qualified by the write enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous chip enables (CE1, CE2, CE3) and an asynchronous output enable (OE) simplify depth expansion. All operations (reads, writes, and deselects) are pipelined. ADV/LD must be driven LOW after the device has been deselected to load a new address for the next operation. Single Read Accesses A read access is initiated when these conditions are satisfied at clock rise: ■ CEN is asserted LOW ■ CE1, CE2, and CE3 are all asserted active ■ The write enable input signal WE is deasserted HIGH ■ ADV/LD is asserted LOW. The address presented to the address inputs is latched into the address register and presented to the memory array and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers. The data is available within 6.5 ns (133-MHz Document Number: 001-75433 Rev. *A device) provided OE is active LOW. After the first clock of the read access, the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. On the subsequent clock, another operation (read/write/deselect) can be initiated. When the SRAM is deselected at clock rise by one of the chip enable signals, its output is tristated immediately. Burst Read Accesses The CY7C1371DV33 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four reads without reasserting the address inputs. ADV/LD must be driven LOW to load a new address into the SRAM, as described in the Single Read Accesses section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and wraps around when incremented sufficiently. A HIGH input on ADV/LD increments the internal burst counter regardless of the state of chip enable inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (read or write) is maintained throughout the burst sequence. Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are all asserted active, and (3) the write signal WE is asserted LOW. The address presented to the address bus is loaded into the address register. The write signals are latched into the control logic block. The data lines are automatically tristated regardless of the state of the OE input signal. This allows the external logic to present the data on DQs and DQPX. On the next clock rise the data presented to DQs and DQPX (or a subset for byte write operations, see truth table for details) inputs is latched into the device and the write is complete. Additional accesses (read/write/deselect) can be initiated on this cycle. The data written during the write operation is controlled by BWX signals. The CY7C1371DV33 provides byte write capability that is described in the truth table. Asserting the write enable input Page 7 of 29 CY7C1371DV33 (WE) with the selected byte write select input selectively writes to only the desired bytes. Bytes not selected during a byte write operation remains unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included to greatly simplify read/modify/write sequences, which can be reduced to simple byte write operations. pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Because the CY7C1371DV33 is a common I/O device, data must not be driven into the device while the outputs are active. The output enable (OE) can be deasserted HIGH before presenting data to the DQs and DQPX inputs. Doing so tristates the output drivers. As a safety precaution, DQs and DQPX are automatically tristated during the data portion of a write cycle, regardless of the state of OE. (MODE = Floating or VDD) Interleaved Burst Address Table Burst Write Accesses The CY7C1371DV33 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four write operations without reasserting the address inputs. ADV/LD must be driven LOW to load the initial address, as described in the Single Write Accesses section above. When ADV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BWX inputs must be driven in each cycle of the burst write, to write the correct bytes of data. First Address A1:A0 Second Address A1:A0 Third Address A1:A0 Fourth Address A1:A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table (MODE = GND) Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses First Address A1:A0 Second Address A1:A0 Third Address A1:A0 Fourth Address A1:A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit IDDZZ Sleep mode standby current ZZ > VDD– 0.2 V – 80 mA tZZS Device operation to ZZ ZZ > VDD – 0.2 V – 2tCYC ns tZZREC ZZ recovery time ZZ < 0.2 V 2tCYC – ns tZZI ZZ active to sleep current This parameter is sampled – 2tCYC ns tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 – ns Document Number: 001-75433 Rev. *A Page 8 of 29 CY7C1371DV33 Truth Table The truth table for CY7C1371DV33 follows. [1, 2, 3, 4, 5, 6, 7] Operation Address Used CE1 CE2 CE3 ZZ ADV/LD WE BWX OE CEN CLK DQ Deselect cycle None H X X L L X X X L L->H Tristate Deselect cycle None X X H L L X X X L L->H Tristate Deselect cycle None X L X L L X X X L L->H Tristate Continue deselect cycle None X X X L H X X X L L->H Tristate Read cycle (begin burst) External L H L L L H X L L L->H Data out (Q) Next X X X L H X X L L L->H Data out (Q) External L H L L L H X H L L->H Tristate Next X X X L H X X H L L->H Tristate External L H L L L L L X L L->H Data in (D) Write cycle (continue burst) Next X X X L H X L X L L->H Data in (D) NOP/write abort (begin burst) None L H L L L L H X L L->H Tristate Write abort (continue burst) Next X X X L H X H X L L->H Tristate Current X X X L X X X X H L->H – None X X X H X X X X X X Tristate Read cycle (continue burst) NOP/dummy read (begin burst) Dummy read (continue burst) Write cycle (begin burst) Ignore clock edge (stall) Sleep mode Partial Truth Table for Read/Write The partial truth table for Read/Write for CY7C1371DV33 follows. [1, 2, 8] Function (CY7C1371DV33) WE BWA BWB BWC BWD Read H X X X X Write no bytes written L H H H H Write byte A – (DQA and DQPA) L L H H H Write byte B – (DQB and DQPB) L H L H H Write byte C – (DQC and DQPC) L H H L H Write byte D – (DQD and DQPD) L H H H L Write all Bytes L L L L L Notes 1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWX = 0 signifies at least one byte write select is active, BWX = valid signifies that the desired byte write selects are asserted, see truth table for details. 2. Write is defined by BWX, and WE. See truth table for read/write. 3. When a write cycle is detected, all I/Os are tristated, even during byte writes. 4. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 5. CEN = H, inserts wait states. 6. Device powers up deselected and the I/Os in a tristate condition, regardless of OE. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = tristate when OE is inactive or when the device is deselected, and DQs and DQPX = data when OE is active. 8. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write is based on which byte write is active. Document Number: 001-75433 Rev. *A Page 9 of 29 CY7C1371DV33 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1371DV33 incorporates a serial boundary scan test access port (TAP).This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3 V or 2.5 V I/O logic levels. The CY7C1371DV33 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull up resistor. TDO must be left unconnected. Upon power-up, the device is up in a reset state which does not interfere with the operation of the device. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see TAP Controller State Diagram on page 12. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see Identification Codes on page 16). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the TAP Controller Block Diagram on page 13. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order on page 17 show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions on page 16. TAP Instruction Set Performing a TAP Reset Overview A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high Z state. Eight different instructions are possible with the three bit instruction register. All combinations are listed in the Identification Codes on page 16. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in detail below. TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the Document Number: 001-75433 Rev. *A Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction after it is shifted in, the TAP controller needs to be moved into the Update-IR state. Page 10 of 29 CY7C1371DV33 EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is supplied a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a high Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is Document Number: 001-75433 Rev. *A still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required – that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST Output Bus Tristate IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tristate mode. The boundary scan register has a special bit located at bit #89 (for 165-ball FBGA package). When this scan cell, called the “extest output bus tristate,” is latched into the preload register during the “Update-DR” state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a high Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR,” the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Page 11 of 29 CY7C1371DV33 TAP Controller State Diagram 1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 1 SELECT IR-SCAN 0 1 0 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 1 1 EXIT1-IR 0 1 0 PAUSE-DR 0 PAUSE-IR 1 0 1 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-DR UPDATE-IR 1 0 1 EXIT1-DR 0 1 0 1 0 The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Document Number: 001-75433 Rev. *A Page 12 of 29 CY7C1371DV33 TAP Controller Block Diagram 0 Bypass Register 2 1 0 TDI Selection Circuitry Selection Circuitry Instruction Register TDO 31 30 29 . . . 2 1 0 Identification Register x . . . . . 2 1 0 Boundary Scan Register TCK TAP CONTROLLER TMS TAP Timing Figure 3. TAP Timing 1 2 Test Clock (TCK) 3 t t TH t TMSS t TMSH t TDIS t TDIH TL 4 5 6 t CYC Test Mode Select (TMS) Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CARE Document Number: 001-75433 Rev. *A UNDEFINED Page 13 of 29 CY7C1371DV33 TAP AC Switching Characteristics Over the Operating Range Parameter [9, 10] Description Min Max Unit Clock tTCYC TCK clock cycle time 50 – ns tTF TCK clock frequency – 20 MHz tTH TCK clock HIGH time 20 – ns tTL TCK clock LOW time 20 – ns tTDOV TCK clock LOW to TDO valid – 10 ns tTDOX TCK clock LOW to TDO invalid 0 – ns Output Times Setup Times tTMSS TMS setup to TCK clock rise 5 – ns tTDIS TDI setup to TCK clock rise 5 – ns tCS Capture setup to TCK rise 5 – ns tTMSH TMS Hold after TCK clock rise 5 – ns tTDIH TDI Hold after clock rise 5 – ns tCH Capture hold after clock rise 5 – ns Hold Times Notes 9. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 10. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns. Document Number: 001-75433 Rev. *A Page 14 of 29 CY7C1371DV33 3.3 V TAP AC Test Conditions 2.5 V TAP AC Test Conditions Input pulse levels ...............................................VSS to 3.3 V Input pulse level ................................................. VSS to 2.5 V Input rise and fall times ...................................................1 ns Input rise and fall time ....................................................1 ns Input timing reference levels ......................................... 1.5 V Input timing reference levels ...................................... .1.25 V Output reference levels ................................................ 1.5 V Output reference levels .............................................. 1.25 V Test load termination supply voltage ............................ 1.5 V Test load termination supply voltage .......................... 1.25 V 3.3 V TAP AC Output Load Equivalent 2.5 V TAP AC Output Load Equivalent 1.25V 1.5V 50Ω 50Ω TDO TDO Z O= 50Ω Z O= 50Ω 20pF 20pF TAP DC Electrical Characteristics and Operating Conditions (0 °C < TA < +70 °C; VDD = 3.3 V ± 0.165 V unless otherwise noted) Parameter [11] VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH voltage Output HIGH voltage Output LOW voltage Output LOW voltage Description Min Max Unit IOH = –4.0 mA VDDQ = 3.3 V 2.4 – V IOH = –1.0 mA VDDQ = 2.5 V 2.0 – V IOH = –100 µA VDDQ = 3.3 V 2.9 – V VDDQ = 2.5 V 2.1 – V IOL = 8.0 mA VDDQ = 3.3 V – 0.4 V IOL = 1.0 mA VDDQ = 2.5 V – 0.4 V IOL = 100 µA VDDQ = 3.3 V – 0.2 V VDDQ = 2.5 V – 0.2 V VDDQ = 3.3 V 2.0 VDD + 0.3 V VDDQ = 2.5 V 1.7 VDD + 0.3 V VDDQ = 3.3 V –0.5 0.7 V VDDQ = 2.5 V –0.3 0.7 V –5 5 µA Input HIGH voltage Input LOW voltage Input load current Conditions GND < VIN < VDDQ Note 11. All voltages referenced to VSS (GND). Document Number: 001-75433 Rev. *A Page 15 of 29 CY7C1371DV33 Identification Register Definitions Instruction Field CY7C1371DV33 (512 K × 36) Revision number (31:29) 000 Description Describes the version number Device depth (28:24) 01011 Device width (23:18) 001001 Defines memory type and architecture Cypress device ID (17:12) 100101 Defines width and density Cypress JEDEC ID Code (11:1) 00000110100 ID register presence indicator (0) 1 Reserved for internal use Allows unique identification of SRAM vendor Indicates the presence of an ID register Scan Register Sizes Register Name Bit Size (× 36) Instruction 3 Bypass 1 ID 32 Boundary Scan Order (165-ball FBGA package) 89 Identification Codes Instruction Code Description EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to high Z state. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a high Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Document Number: 001-75433 Rev. *A Page 16 of 29 CY7C1371DV33 Boundary Scan Order 165-ball BGA [12, 13] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 D10 61 G1 2 N7 32 C11 62 D2 3 N10 33 A11 63 E2 4 P11 34 B11 64 F2 5 P8 35 A10 65 G2 6 R8 36 B10 66 H1 7 R9 37 A9 67 H3 8 P9 38 B9 68 J1 9 P10 39 C10 69 K1 10 R10 40 A8 70 L1 11 R11 41 B8 71 M1 12 H11 42 A7 72 J2 13 N11 43 B7 73 K2 14 M11 44 B6 74 L2 15 L11 45 A6 75 M2 16 K11 46 B5 76 N1 17 J11 47 A5 77 N2 18 M10 48 A4 78 P1 19 L10 49 B4 79 R1 20 K10 50 B3 80 R2 21 J10 51 A3 81 P3 22 H9 52 A2 82 R3 23 H10 53 B2 83 P2 24 G11 54 C2 84 R4 25 F11 55 B1 85 P4 26 E11 56 A1 86 N5 27 D11 57 C1 87 P6 28 G10 58 D1 88 R6 29 F10 59 E1 89 Internal 30 E10 60 F1 Notes 12. Balls which are NC (No Connect) are pre-set LOW. 13. Bit# 89 is pre-set HIGH. Document Number: 001-75433 Rev. *A Page 17 of 29 CY7C1371DV33 Maximum Ratings DC input voltage ................................. –0.5 V to VDD + 0.5 V Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied .......................................... –55 °C to +125 °C Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD DC voltage applied to outputs in tristate ...........................................–0.5 V to VDDQ + 0.5 V Current into outputs (LOW) ........................................ 20 mA Static discharge voltage (MIL-STD-883, method 3015) ................................. > 2001 V Latch up current ..................................................... > 200 mA Operating Range Range Industrial Ambient Temperature –40 °C to +85 °C VDD VDDQ 3.3 V– 5% / 2.5 V – 5% to + 10% VDD Electrical Characteristics Over the Operating Range Parameter [14, 15] VDD VDDQ VOH VOL VIH VIL IX Description Test Conditions Min Max Unit 3.135 3.135 2.375 2.4 2.0 – – 2.0 1.7 –0.3 –0.3 –5 3.6 VDD 2.625 – – 0.4 0.4 VDD + 0.3 V VDD + 0.3 V 0.8 0.7 5 V V V V V V V V V V V A Input = VSS –30 – A Input = VDD – 5 A Input = VSS –5 – A Power supply voltage I/O supply voltage For 3.3 V I/O For 2.5 V I/O Output HIGH voltage For 3.3 V I/O, IOH = –4.0 mA For 2.5 V I/O, IOH = –1.0 mA Output LOW voltage For 3.3 V I/O, IOL = 8.0 mA For 2.5 V I/O, IOL = 1.0 mA Input HIGH voltage [14] For 3.3 V I/O For 2.5 V I/O Input LOW voltage [14] For 3.3 V I/O For 2.5 V I/O Input leakage current except ZZ GND VI VDDQ and MODE Input current of MODE Input current of ZZ – 30 A IDD VDD operating supply current VDD = Max, IOUT = 0 mA, f = fMAX = 1/tCYC 7.5 ns cycle, 133 MHz – 210 mA ISB1 Automatic CE power-down current – TTL inputs VDD = Max, device deselected, VIN VIH or VIN VIL, f = fMAX, inputs switching 7.5 ns cycle, 133 MHz – 140 mA ISB2 Automatic CE power-down current – CMOS inputs VDD = Max, device deselected, 7.5 ns cycle, VIN 0.3 V or VIN > VDD – 0.3 V, 133 MHz f = 0, inputs static – 70 mA ISB3 Automatic CE power-down current – CMOS inputs VDD = Max, device deselected, 7.5 ns cycle, VIN 0.3 V or VIN > VDDQ – 0.3 V, 133 MHz f = fMAX, inputs switching – 130 mA ISB4 Automatic CE power-down current – TTL inputs VDD = Max, device deselected, 7.5 ns cycle, VIN VDD – 0.3 V or VIN 0.3 V, 133 MHz f = 0, inputs static – 80 mA Input = VDD Notes 14. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2). 15. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document Number: 001-75433 Rev. *A Page 18 of 29 CY7C1371DV33 Capacitance Parameter [16] Description 100-pin TQFP 165-ball FBGA Unit Package Package Test Conditions TA = 25 C, f = 1 MHz, VDD = 3.3 V, VDDQ = 2.5 V CIN Input capacitance CCLK Clock input capacitance CIO Input/output capacitance 5 9 pF 5 9 pF 5 9 pF Thermal Resistance Parameter [16] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) 100-pin TQFP 165-ball FBGA Unit Package Package Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, according to EIA/JESD51. 28.66 20.7 C/W 4.08 4.0 C/W AC Test Loads and Waveforms Figure 4. AC Test Loads and Waveforms 3.3 V I/O Test Load R = 317 3.3 V OUTPUT OUTPUT RL = 50 Z0 = 50 GND 5 pF R = 351 VT = 1.5 V INCLUDING JIG AND SCOPE (a) ALL INPUT PULSES VDDQ 10% 90% 10% 90% 1ns 1ns (c) (b) 2.5 V I/O Test Load R = 1667 2.5 V OUTPUT OUTPUT RL = 50 Z0 = 50 GND 5 pF R = 1538 VT = 1.25 V (a) ALL INPUT PULSES VDDQ INCLUDING JIG AND SCOPE (b) 10% 90% 10% 90% 1ns 1ns (c) Note 16. Tested initially and after any design or process change that may affect these parameters. Document Number: 001-75433 Rev. *A Page 19 of 29 CY7C1371DV33 Switching Characteristics Over the Operating Range Parameter [17, 18] Description tPOWER[19] 133 MHz Unit Min Max 1 – ms Clock tCYC Clock cycle time 7.5 – ns tCH Clock HIGH 2.1 – ns tCL Clock LOW 2.1 – ns Output Times tCDV Data output valid after CLK rise – 6.5 ns tDOH Data output hold after CLK rise 2.0 – ns 2.0 – ns – 4.0 ns – 3.2 ns 0 – ns – 4.0 ns [20, 21, 22] tCLZ Clock to low Z tCHZ Clock to high Z [20, 21, 22] tOEV OE LOW to output valid tOELZ tOEHZ OE LOW to output low Z [20, 21, 22] OE HIGH to output high Z [20, 21, 22] Setup Times tAS Address setup before CLK rise 1.5 – ns tALS ADV/LD setup before CLK rise 1.5 – ns tWES WE, BWX setup before CLK rise 1.5 – ns tCENS CEN setup before CLK rise 1.5 – ns tDS Data input setup before CLK rise 1.5 – ns tCES Chip enable setup before CLK rise 1.5 – ns tAH Address hold after CLK rise 0.5 – ns tALH ADV/LD hold after CLK rise 0.5 – ns tWEH WE, BWX hold after CLK rise 0.5 – ns Hold Times tCENH CEN hold after CLK rise 0.5 – ns tDH Data input hold after CLK rise 0.5 – ns tCEH Chip enable hold after CLK rise 0.5 – ns Notes 17. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V. 18. Test conditions shown in (a) of Figure 4 on page 19 unless otherwise noted. 19. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation can be initiated. 20. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 4 on page 19. Transition is measured ±200 mV from steady-state voltage. 21. At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high Z prior to low Z under the same system conditions. 22. This parameter is sampled and not 100% tested. Document Number: 001-75433 Rev. *A Page 20 of 29 CY7C1371DV33 Switching Waveforms Figure 5. Read/Write Waveforms [23, 24, 25] 1 2 3 t CYC 4 5 6 7 8 9 A5 A6 A7 10 CLK t CENS t CENH t CES t CEH t CH t CL CEN CE ADV/LD WE BW X A1 ADDRESS t AS A2 A4 A3 t CDV t AH t DOH t CLZ DQ D(A1) t DS D(A2) Q(A3) D(A2+1) t OEV Q(A4+1) Q(A4) t OELZ W RITE D(A1) W RITE D(A2) D(A5) Q(A6) D(A7) W RITE D(A7) DESELECT t OEHZ t DH OE COM M AND t CHZ BURST W RITE D(A2+1) READ Q(A3) READ Q(A4) DON’T CARE BURST READ Q(A4+1) t DOH W RITE D(A5) READ Q(A6) UNDEFINED Notes 23. For this waveform ZZ is tied LOW. 24. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 25. Order of the burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional. Document Number: 001-75433 Rev. *A Page 21 of 29 CY7C1371DV33 Switching Waveforms (continued) Figure 6. NOP, STALL AND DESELECT Cycles [26, 27, 28] 1 2 A1 A2 3 4 5 A3 A4 6 7 8 9 10 CLK CEN CE ADV/LD WE BW [A:D] ADDRESS A5 t CHZ D(A1) DQ Q(A2) Q(A3) D(A4) Q(A5) t DOH COMMAND WRITE D(A1) READ Q(A2) STALL READ Q(A3) WRITE D(A4) DON’T CARE STALL NOP READ Q(A5) DESELECT CONTINUE DESELECT UNDEFINED Notes 26. For this waveform ZZ is tied LOW. 27. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 28. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle. Document Number: 001-75433 Rev. *A Page 22 of 29 CY7C1371DV33 Switching Waveforms (continued) Figure 7. ZZ Mode Timing [29, 30] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes 29. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device. 30. DQs are in high Z when exiting ZZ sleep mode. Document Number: 001-75433 Rev. *A Page 23 of 29 CY7C1371DV33 Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (MHz) 133 Ordering Code Package Diagram Part and Package Type CY7C1371DV33-133AXI 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free CY7C1371DV33-133BZI 51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Operating Range lndustrial Ordering Code Definitions CY 7 C 1371 D V33 - 133 XX X I Temperature range: I = Industrial = –40 °C to +85 °C X = Pb-free Package Type: XX = A or BZ A = 100-pin TQFP (3 chip enable); BZ = 165-ball FBGA Speed Grade: 133 MHz V33 = 3.0 V to 3.6 V Die Revision: D 90 nm Part Identifier: 1371 = FT, 512 Kb × 36 (18 Mb) Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-75433 Rev. *A Page 24 of 29 CY7C1371DV33 Package Diagrams Figure 8. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050 51-85050 *D Document Number: 001-75433 Rev. *A Page 25 of 29 CY7C1371DV33 Package Diagrams (continued) Figure 9. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180 51-85180 *F Document Number: 001-75433 Rev. *A Page 26 of 29 CY7C1371DV33 Acronyms Acronym Document Conventions Description Units of Measure CMOS complementary metal oxide semiconductor CE chip enable °C degree Celsius CEN clock enable MHz megahertz EIA electronic industries alliance µA microampere JEDEC joint electron devices engineering council mA milliampere FBGA fine-pitch ball grid array mm millimeter I/O input/output ms millisecond JTAG joint test action group mV millivolt NoBL No Bus Latency ns nanosecond OE output enable ohm SRAM static random access memory % percent TCK test clock pF picofarad TDI test data input V volt TMS test mode select W watt TDO test data output TQFP thin quad flat pack WE write enable Document Number: 001-75433 Rev. *A Symbol Unit of Measure Page 27 of 29 CY7C1371DV33 Document History Page Document Title: CY7C1371DV33, 18-Mbit (512 K × 36) Flow-Through SRAM with NoBL™ Architecture Document Number: 001-75433 Rev. ECN No. Submission Date Orig. of Change Description of Change ** 3534577 02/28/2012 PRIT New data sheet. *A 3914173 02/26/2013 PRIT Updated Package Diagrams: spec 51-85180 – Changed revision from *E to *F. Document Number: 001-75433 Rev. *A Page 28 of 29 CY7C1371DV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive psoc.cypress.com/solutions cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2012-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-75433 Rev. *A Revised February 26, 2013 Page 29 of 29 NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this document may be the trademarks of their respective holders.