CYV270M0104EQ Adaptive Video Cable Equalizer Features Functional Description ■ Adaptive cable equalization ■ SMPTE 259M Compliant ■ Supports DVB-ASI at 270 Mbps ■ Multi standard operation from 143 Mbps to 360 Mbps ■ Maximum cable length adjustment The CYV270M0104EQ is an adaptive video cable equalizer designed to equalize and restore signals received over 75Ω coaxial cable. The equalizer is designed to meet SMPTE 259M data rates and is optimized for performance at 270 Mbps. The CYV270M0104EQ is optimized to equalize up to 350m of Belden 1694A and Canare L-5CFB coaxial cable at 270 Mbps. The CYV270M0104EQ connects seamlessly to the HOTLink II family of transceiver devices and HOTLink receiver devices. ■ Carrier detect and mute functionality ■ Equalizer bypass mode ■ Seamless connection with HOTLink II™ Family and HOTLink® Receiver ■ Equalizes up to 350m of Belden 1694A and Canare L-5CFB coaxial cable at 270 Mbps ■ Low power: 160 mW at 3.3V ■ Single 3.3V supply ■ 16-pin Quad Flat Pb-free (QFN) package ■ 0.18 μm CMOS technology ■ Pb-free and RoHS compliant ■ Pin compatible to existing QFN equalizer devices ■ Uses Cypress CLEANLink™ technology The CYV270M0104EQ has DC restoration to compensate for the DC content of the SMPTE pathological patterns. The maximum cable length adjust (MCLADJ) sets the approximate maximum cable length to equalize. The CYV270M0104EQ’s differential serial outputs (SDO, SDO) mute, when the approximate cable length set by MCLADJ is reached and carrier detect (CD) is tied to MUTE. The MUTE pin controls muting of the equalizer outputs. Power consumption is typically 160 mW at 3.3V. Equalizer System Connection Diagram HOTLink II Serializer Cypress Semiconductor Corporation Document Number: 001-12875 Rev. ** CYV270M0104EQ Adaptive Cable Equalizer Serial Links Cable Driver Copper Cable Connections • 198 Champion Court • HOTLink II Deserializer San Jose, CA 95134-1709 • 408-943-2600 Revised October 25, 2007 [+] Feedback CYV270M0104EQ Equalizer Block Diagram CYV270M0104EQ Adaptive Video Cable Equalizer Block Diagram CYV270M0104EQ Adaptive Video Cable Equalizer Block Diagram MCLADJ Cable Length Analog Adjustor and Mute Threshold Block Carrier Detect and Mute Control Block MUTE CD DC Restore BYPASS SDI, SDI Equalizer Differential Output SDO, SDO Pinouts SDI 3 GND 4 Document Number: 001-12875 Rev. ** CD MUTE VCC 13 CYV270M0104EQ (Marked CY01EQ On Package) 5 6 7 8 MCLADJ 2 14 BYPASS SDI 15 AGC 1 16 AGC GND VCC Figure 1. Pin Diagram - 16 Pin QFN (Top View) 12 GND 11 SDO 10 SDO 9 GND Center Pad (bottom of package) Page 2 of 9 [+] Feedback CYV270M0104EQ Table 1. Pin Descriptions - CYV270M0104EQ Adaptive Video Cable Equalizer Name IO Characteristics Signal Description Control Signals MUTE LVTTL Input Mute. When the MUTE pin is set LOW, the equalizer’s differential serial outputs are not muted. When the MUTE pin is set HIGH, the equalizer’s differential serial outputs are muted. The BYPASS setting is ignored when MUTE is HIGH. Connecting CD to the MUTE pin enables automatic muting of the equalizer when the signal is lost. Do not leave an unused MUTE pin floating. Always drive it to a known state. CD LVTTL Output Carrier Detect. When the incoming data stream is present and maximum cable length set by MCLADJ is not exceeded, CD outputs a voltage less than 0.8V. When the incoming data stream is not present or maximum cable length set by MCLADJ is exceeded, CD outputs a voltage greater than 2.8V. Connecting CD to the MUTE pin enables automatic muting of the equalizer when the signal is lost. MCLADJ Analog Input Maximum Cable Length Adjust. The maximum cable length to equalize is set by the voltage applied to the MCLADJ input. When the maximum cable length set by MCLADJ is reached, the CD indicator deasserts. If MCLADJ functionality is not required, then this pin should be left floating or tied to ground to allow maximum equalized cable length. BYPASS LVTTL Input Equalizer Bypass. When BYPASS is set HIGH, the signal presented at the equalizer’s differential serial inputs (SDI, SDI) is routed to the equalizer’s differential serial outputs (SDO, SDO) without performing equalization. When BYPASS is set LOW, the incoming video data stream is equalized and presented at the equalizer‘s serial differential outputs (SDO, SDO). When MUTE is set HIGH, the BYPASS setting is ignored and the serial outputs are muted. AGC, AGC Analog Automatic Gain Control. Place a 1 μF capacitor between the AGC and AGC pins. SDO, SDO Differential Output Differential Serial Outputs. The equalized serial video data stream is presented at the SDO/SDO differential serial CML output. SDI, SDI Differential Input Differential Serial Inputs. SDI/SDI accepts either a single-ended or differential serial video data stream over 75Ω coaxial cable. VCC Power Power Supply for Device. Connect to +3.3V DC. GND Gnd Connect to Ground. Center Pad – Connect to PCB Ground for Maximum Thermal Dissipation. Power Document Number: 001-12875 Rev. ** Page 3 of 9 [+] Feedback CYV270M0104EQ Equalizer Operation MUTE The CYV270M0104EQ is an adaptive video cable equalizer that equalizes standard definition (SD) serial digital interface (SDI) video data streams. The CYV270M0104EQ equalizer is optimized to equalize up to 350m of Belden 1694A and Canare L-5CFB cable at 270 Mbps. The device contains one power supply and typically consumes 160 mW power at 3.3V. The adaptive equalizer meets the SMPTE 259M and DVB-ASI video standards. It meets all pathological requirements for SMPTE 259M as defined by RP178. The CYV270M0104EQ Video Cable Equalizer is auto adaptive from 143 Mbps to 360 Mbps. MUTE is an input pin that controls the muting of the equalizer’s output. The CYV270M0104EQ equalizer has multiple variable gain equalization stages that reverse the effects of the cable. This equalization is achieved by separate regulation of the lower and higher frequency components in the signal to give a clean output eye diagram. The CYV270M0104EQ has DC restoration for compensating the DC content of the SMPTE pathological patterns. SDI, SDI CYV270M0104EQ accepts single-ended or differential serial video data streams over 75Ω coaxial cable. It is recommended to AC couple the SDI and SDI inputs because they are internally biased to 1.2V. SDO, SDO The CYV270M0104EQ has differential serial output interface drivers that use Current Mode Logic (CML) drivers to provide source matching for the transmission line. These outputs are either AC coupled or DC coupled to HOTLink II receivers. MCLADJ If MUTE is set LOW, then the equalizer serial outputs are not muted. If MUTE is set HIGH, then the equalizer serial outputs are muted. When MUTE is active, the BYPASS setting is also ignored. Connecting CD to MUTE enables automatic muting of the equalizer when the signal is lost. Do not leave the MUTE pin floating. Always drive it to a known state. Carrier Detect (CD) Carrier Detect is an active LOW output pin that indicates the presence of a valid incoming data signal. When the incoming data signal is present and maximum cable length does not exceed the length that is set by MCLADJ, CD outputs a voltage less than 0.8V. When the incoming data stream is not present or maximum cable length exceeds the length that is set by MCLADJ, CD outputs a voltage greater than 2.8V. Connecting CD to MUTE enables automatic muting of the equalizer when the signal is lost. BYPASS The CYV270M0104EQ has a bypass mode that enables the user to bypass the equalizer’s equalization and DC restoration functions. When BYPASS is set HIGH, the signal presented at the equalizer’s differential serial inputs (SDI, SDI) is routed to the equalizer’s differential serial outputs (SDO, SDO) without equalizing. Maximum Cable Length Adjust (MCLADJ) sets the approximate maximum amount of cable to equalize. When the maximum cable length set by MCLADJ is reached, the CD pin deasserts. To enable automatic muting of the device when the signal is lost, tie CD directly to MUTE. When BYPASS is set LOW, the incoming video data stream is equalized and presented at the equalizer‘s differential serial outputs (SDO, SDO). The graph in Figure 2 on page 7 illustrates the voltage required at MCLADJ input to equalize various Belden 1694A cables. The same graph applies for Canare L-5CFB cables. If MCLADJ functionality is not required, this pin should be left floating or tied to ground to allow maximum equalized cable length. Place a 1 μF capacitor between the AGC and AGC pins of the CYV270M0104EQ equalizer. Document Number: 001-12875 Rev. ** AGC Page 4 of 9 [+] Feedback CYV270M0104EQ Maximum Ratings Power Up Requirements Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. The CYV270M0104EQ contains one power supply. The voltage on any input or IO pin must not exceed the power pin during power up. Storage Temperature .................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................ –55°C to +125°C Operating Range Supply Voltage to Ground Potential................–0.5V to +3.8V Range Ambient Temperature VCC DC Voltage Applied to Outputs in High Z State ....................................... –0.5V to VCC + 0.5V Commercial 0°C to +70°C +3.3V ±5% DC Input Voltage ................................... –0.5V to VCC + 0.5V Electro Static Discharge (ESD) HBM........................ > 2000V (JEDEC EIA/JESD-A114A) Latch Up Current .................................................... > 200 mA DC Electrical Characteristics Parameter Description Min Typ Max Unit – 3.135 3.3 3.465 V – 125 160 190 mW – 38 48 60 mA Load = 50Ω – VCC – ΔVSDO/2 = 2.9 – V Input Common Mode Voltage[1] (Bypass = High) – 1 1.4 V Input Common Mode Voltage[1] (Bypass = Low) – 0 2.9 V Floating MCLADJ DC Voltage[1] – Supply Voltage[1] Power Consumption[2] IS Supply Current[1] VCMOUT Output Common Mode Voltage[1] VCMIN VCC PD – – VCD(OH) MCLADJ Range[3] CD Output Voltage[1] VCD(OL) Test Conditions 1.3 – 0.4 0.72 Carrier Not Present 2.8 – Carrier Present VMUTE MUTE Input Voltage Required to Force Outputs to Mute[1] Min to Mute VMUTE MUTE Input Voltage Required to Force Active[1] Max to Activate 1.02 V – – V – 0.8 V – V 1 V 2.5 – V – Notes 1. Production test. 2. Calculated results from production test. 3. Not tested. Based on characterization. Document Number: 001-12875 Rev. ** Page 5 of 9 [+] Feedback CYV270M0104EQ AC Electrical Characteristics Parameter Description Test Conditions [1] Min Typ – – Serial Input Data Rate – 143 VSDI Input Voltage Swing Single-ended, at the transmitter, SD data rate 500[5] ΔVSDO Output Voltage Swing[1] Differentialp-p, 50Ω load 450 – Output Jitter for Various Cable Lengths and Data Rates 270 Mbps Belden 1694A: 0-350m Canare L-5CFB: 0-350m 800 mV transmit amplitude Equalizer pathological pattern – – Output Rise/Fall Time[3, 4] 20% - 80% 80 – Mismatch in Rise/Fall Distortion[3, 4] – Duty Cycle – Overshoot[3, 4] – Time[3, 4] Input Return – SD color bar pattern Loss[3] Max Unit 360 Mbps 1200 mV 700 950 mV 0.2[1] – UI 120 350 ps – – 30 ps – 0.03 – UI – – – 10 % – -15 – – dB 2.5 – kΩ Input Resistance[3, 4] Single-ended – – Input Capacitance[3, 4] Single-ended – 1 – pF – Output Resistance[3, 4] Single-ended – 50 – Ω – Notes 4. Not tested. Guaranteed by design simulations. 5. Based on characterization across temperature and voltage with 350m of Belden 1694A and Canare L-5CFB cable, transmitting SMPTE Equalizer Pathological Test Pattern. Document Number: 001-12875 Rev. ** Page 6 of 9 [+] Feedback CYV270M0104EQ Typical Performance Graphs (Unless otherwise stated, VCC = 3.3V, TA = 25°C) Figure 2. MCLADJ Input Voltage vs Belden 1694A Cable Length at SD-SDI Data Rate 2.7 2.6 2.5 VOLTAGE (V) 2.4 2.3 2.2 2.1 2 1.9 1.8 1.7 0 50 100 150 200 250 300 350 CABLE LENGTH (m ) Typical Application Circuit Figure 3. Interfacing CYV270M0104EQ to the HOTLink II SerDes +3.3V +3.3V C10 2 Z0 9 R18 Z0 Document Number: 001-12875 Rev. ** GND CD VCC VCC 8 7 1μF R16 C15 GND SDI SDI GND 6 5 3 4 BNC JACK 75Ω 1 2 75Ω 1μF L2 C16 6.4nH 37.4Ω R15 R14 75Ω CYV270M0104EQ MCLADJ C YV15G0101DXB SDO 0.01μF AGC Z0 GND SDO MUTE 12 11 10 AGC FRAMCHAR RFEN RFMODE DECMODE RXCKSEL RXMODE RXRATE 13 14 15 16 BYPASS IN1- C12 0.01μF MCLADJ RXLE SDASEL LPEN INSEL IN1+ C11 + LFI RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 RXOP RXST2 RXST1 RXST0 RXCLK+ RXCLKRXCLKC+ 1μF Page 7 of 9 [+] Feedback CYV270M0104EQ Ordering Information Ordering Code Package Marking Package Name CYV270M0104EQ-LXC CY01EQ LY16A Operating Range Package Type Pb-free 16-Pin QFN 0 to 70°C Package Dimension Figure 4. 16-Pin QFN (4x4 mm) Package LY16A 0.05 3.90 4.10 C 2.50 REF. 1.00 MAX. 0.05 MAX. 3.70 3.80 0.80 MAX. PIN1 ID 0.20 R. 0.35±0.05 0.20 REF. N 2.50 N REF. 1 2 1.90 2.00 3.90 4.10 3.70 3.80 1 2 E-PAD 0.45 0.30-0.50 0.42±0.18 (4X) 0°-12° C SEATING PLANE 0.65 1.90 2.00 TOP VIEW SIDE VIEW DIMENSION IN mm MIN. MAX. REFERENCE JEDEC MO-220 PKG. WEIGHT 0.04gms Document Number: 001-12875 Rev. ** PART # BOTTOM VIEW 001-04468-*A LF16A STANDARD PKG. LY16A LEAD FREE PKG. Page 8 of 9 [+] Feedback CYV270M0104EQ Document History Page Document Title: CYV270M0104EQ Adaptive Video Cable Equalizer Document Number: 001-12875 REV. ECN NO. ISSUE DATE ORIG. OF CHANGE ** 1396423 SEE ECN UKK/AESA DESCRIPTION OF CHANGE New datasheet © Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-12875 Rev. ** Revised October 25, 2007 Page 9 of 9 PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. HOTLink is a registered trademark and HOTLink II and CLEANLink are trademarks of Cypress Semiconductor. All other trademarks or registered trademarks referenced herein are property of the respective corporations. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback