ZARLINK ZL10060LDF1

ZL10060
MOPLL with IF AGC Amplifier
Data Sheet
Features
November 2005
•
Highly integrated mixer/oscillator PLL and IF AGC
amplifier for multi band analog/digital terrestrial
tuners and/or cable tuners
•
Low phase noise PLL frequency synthesizer
•
AGC output level detect with digital controlled
TOP threshold
•
>50 dB Desired/Undesired ratio without pre
filtering
•
Separate analog and digital IF outputs
•
>41 dB IF AGC Control range
•
Power down modes to support power reduction
initiatives
•
Four independent GPO
•
48 pin QFN Package
Ordering Information
ZL10060LDG1 48 Pin QFN* Trays
ZL10060LDF1 48 Pin QFN* Tape and Reel
*Pb Free Matte Tin
-20°C to +85°C
Description
The ZL10060 is a 3 band MOPLL with IF AGC
amplifier. It down-converts the RF channel to a
standard IF followed by filtering and IF AGC
amplification for the digital channel. Each band
consists of a low noise preamplifier/mixer and local
oscillator with an external varactor tuned tank circuit.
An IF level detector is included for control of the RF
AGC. The Take Over Point and time constant are both
programmable.
Applications
The ZL10060 has high signal level handling
performance providing excellent performance in the
presence of high level unwanted signals.
•
DVB-T receiver systems
•
ISDB-T receiver systems
•
DVB-C cable receiver systems
•
Terrestrial analog receivers
All chip control is via I2C bus.
If higher performance is required, an alternative part,
ZL10063 is available with image reject down
conversion.
Band
Pass
Filter
Input
IF SAW
Digital
IF SAW
Analog
Analog IF
Digital IF
Digital
Demod
IF AGC
PLL
GPO
AGC
Det
I2C
Control
Tuning
RF AGC
Demod
ZL10060
LNA and Tracking
Filters
RF
Analog
VCO Tank
Circuits
Loop
Filter
Figure 1 - Basic Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2005, Zarlink Semiconductor Inc. All Rights Reserved.
I2C
ZL10060
Data Sheet
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 RF Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 SAW Driver Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3 AGC Detector and ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 IF AGC Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.5 VCO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.6 PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.7 General Purpose Switching Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.8 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.0 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Programmable Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 PLL Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5 Control Register - Byte 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6 Control Register - Byte 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.7 Control Register - Byte 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.8 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.0 Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.0 PIn Circuit Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.0 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.0 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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Zarlink Semiconductor Inc.
ZL10060
Data Sheet
List of Figures
Figure 1 - Basic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3 - Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4 - Low Band (VHF1) External Tank Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5 - Mid Band (VHF3) External Tank Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6 - High Band (UHF) External Tank Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7 - Typical Application Circuit (DVB-T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8 - Crystal Oscillator Circuit (4 MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9 - Interstage Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10 - Noise Figure Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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Zarlink Semiconductor Inc.
ZL10060
Data Sheet
List of Tables
Table 1 - Pin Names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2 - Programmable Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3 - Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4 - Address Bit MA1 and MA0 Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5 - Byte 2- LO Divider (MSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6 - Byte 3 LO Divider (LSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 7 - Byte 4 PLL Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 8 - Charge Pump Current Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 9 - Reference Divide Ratio Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 10 - Byte 5 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 11 - Band Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 12 - Internal Circuit Block Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 13 - GPPO Output Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 14 - Byte 6 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 15 - AGC Decay Current Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 16 - AGC Threshold Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 17 - Byte 7 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 18 - ADC Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 19 - Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 20 - Read Data Format (MSB is transmitted first) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 21 - AGC Activity Flag Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 22 - ADC Output Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 23 - Optimum CP and LO Trim Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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Zarlink Semiconductor Inc.
Data Sheet
IFOPB
IFOP
VeeIF
VccIF
XTAL
XCAP
VccIF
SDB
SD
VccDIG
PUMP
DRIVE
ZL10060
1
IFIPB
IFIP
VccOSC
VeeOSC
LHIPB
LHOPB
LHOP
LHIP
LMOPB
LMOP
LLOPB
LLOP
ZL10060
SIPB
SIP
GPP0
GPP1
GPP2
VeeRF
LOIP
IPREF
MIDIP
HIIP
HIIPB
GPP3
IFAGC
SAB
SA
ADC
SDA
SCL
ADD
AGCOP
CNOPB
CNOP
CONT
VccRF
Vee
(PACKAGE
PADDLE)
Figure 2 - Pin Diagram
Pin No.
Port Name
Function
1
IFAGC
IF amplifier AGC input
2
SAB
SAW filter driver output (analog)
3
SA
SAW filter driver output (analog)
4
ADC
External ADC input
5
SDA
I2C bus serial data input/output
6
SCL
I2C bus serial clock input
7
ADD
I2C bus address selection input
8
AGCOP
AGC output
9
CNOPB
Analog converter output
10
CNOP
Analog converter output
11
CONT
Paddle (Ground)
12
VccRF
RF section supply
13
SIPB
SAW filter driver input
14
SIP
SAW filter driver input
15
GPP0
General purpose switching port
16
GPP1
General purpose switching port
Table 1 - Pin Names
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Zarlink Semiconductor Inc.
ZL10060
Pin No.
Port Name
Data Sheet
Function
17
GPP2
General purpose switching port
18
VeeRF
RF section ground
19
LOIP
Low band input
20
IPREF
Reference input for low and mid bands
21
MIDIP
Mid band input
22
HIIP
High band input
23
HIIPB
High band inverse input
24
GPP3
General purpose switching port
25
LLOP
Low band local oscillator output
26
LLOPB
Low band local oscillator inverse output
27
LMOP
Mid band local oscillator output
28
LMOPB
Mid band local oscillator inverse output
29
LHIP
High band local oscillator input
30
LHOP
High band local oscillator output
31
LHOPB
High band local oscillator inverse output
32
LHIPB
High band local oscillator inverse input
33
VeeOSC
Oscillator section ground
34
VccOSC
Oscillator supply
35
IFIP
IF amplifier input
36
IFIPB
IF amplifier inverse input
37
DRIVE
Loop amplifier drive output
38
PUMP
Loop amplifier charge pump output
39
VccDIG
Digital section supply
40
SD
SAW filter driver output (digital)
41
SDB
SAW filter driver output (digital)
42
VccIF
IF amplifier section supply
43
XCAP
Reference oscillator feedback input
44
XTAL
Reference oscillator crystal drive
45
VccIF
IF amplifier section supply
46
VeeIF
IF section ground
47
IFOP
IF amplifier output
48
IFOPB
IF amplifier inverse output
Vee
Global ground
Paddle
Table 1 - Pin Names (continued)
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Zarlink Semiconductor Inc.
ZL10060
Data Sheet
Figure 3 - Detailed Block Diagram
1.0
Functional Description
The ZL10060 is a three-band RF mixer oscillator with on-board frequency synthesizer and IF AGC amplifier,
integrating all tuner active circuitry after the tracking filter in a single package.
It is intended for use in all band terrestrial tuners, and requires a minimum external component count. It contains all
elements required for RF down conversion to a standard IF with the exception of external VCO tank circuits.
In normal application the RF input is interfaced to the selected mixer oscillator preamplifier through the tuner prefilter and AGC stages. The ZL10060 provides an RF AGC control signal, which can be used to control the RF gain.
The preamplifier output feeds the mixer stage where the required channel is down converted to the IF frequency.
The local oscillator frequency for the down conversion is obtained from the on board PLL and local oscillator, with
an external varactor tuned tank.
The downconverted signal is then passed through an external filter into a SAW filter driver amplifier. This provides
two output channels for hybrid analog and digital applications.
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Zarlink Semiconductor Inc.
ZL10060
Data Sheet
An AGC IF amplifier is included which provides an output signal to a digital demodulator.
The device is controlled through an I2C compatible interface.
1.1
RF Converter
The ZL10060 contains three input stages to cover the VHF1, VHF3 and UHF frequency bands. The inputs would
normally be driven by front end amplifiers and tracking filters. All three inputs are differential, however, the VHF1
and VHF3 inputs would normally be single ended. These inputs therefore can share a common input reference pin.
The UHF input should be driven with a differential signal. The inputs are all high impedance. The differential
converter IF output is then passed through an external interstage filter. This can be tuned for 36 MHz for DVB-T
applications but can also be used at 44 MHz and 57 MHz to be compatible with other TV standards. The
recommended filter circuit is shown in Figure 9. The design of this filter provides an impedance transformation as
well as rejection of adjacent channels. A 0.5 dB Chebychev filter with 10 MHz bandwidth is recommended. This
gives a flat response across the pass band and takes into account normal component tolerances.
1.2
SAW Driver Amplifier
The output of the interstage filter then passes to the SAW filter drive amplifier. This provides further amplification
and interfaces to the SAW filter. Two SAW filter drive outputs are provided for hybrid analog and digital applications.
Both output stages are identical however the digital output (SD, SDB) should always be used for digital applications
as the pin out of the device has been optimized to give the best isolation performance in this configuration. Output
selection is programmable however it should be noted that the unselected output is not powered off but operates at
a lower power level which means that a signal will still be present on the output.
The differential outputs will drive a balanced SAW filter with a tuning inductor to resonate with the SAW filter input
capacitance. The SAW filter can also be driven without the tuning inductor but with the addition of 350 ohm resistors
to ground on the SAW driver outputs to increase the output drive capability. This will increase total current
consumption by 14 mA.
1.3
AGC Detector and ADC
The ZL10060 contains a broadband AGC detector circuit which provides an output to provide gain control for the
RF frontend gain stages. The detector input signal is derived from the signal level in the SAW driver amplifier. The
composite signal at this point is the wanted signal plus adjacent channels (N +/- 1, N +/- 2, N +/- 3). The AGC
detector threshold point at which the agc output becomes active can be programmed to one of eight levels via the
I2C interface. When the composite level reaches the agc threshold, the agc output pin will be active. The AGC
attack current is fixed, however, the decay current can be programmed to two levels. The agc output can only drive
a high impedance e.g., a dual gate FET. If RF gain control uses a PiN diode then a simple buffer circuit will be
required.
An AGC flag output is also available through the I2C interface. This indicates when the AGC output is active i.e.,
less than 4 volts.
The agc output level can also be monitored by an on chip 3 bit ADC. Although the ADC is 3 bits, only 5 levels are
available. Alternatively the ADC can be programmed to measure the voltage on an external pin (ADC Pin 4).
1.4
IF AGC Amplifier
The AGC amplifier amplifies the output of the SAW filter for the digital channel and provides a differential output to
the demodulator. The analog gain control signal is normally derived from the demodulator. At least 41 dB of gain
control is provided.
The AGC amplifier can be powered down independently of the rest of the device if not required. This mode could be
used in analog applications to reduce overall power consumption.
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Zarlink Semiconductor Inc.
ZL10060
1.5
Data Sheet
VCO
Separate VCO’s are provided for each band. The oscillator circuits are on chip however the tank circuitry is
external. All three oscillators are differential. The typical external tank circuits are shown in Figures 4, 5 and 6. It is
essential to take care to minimize track lengths and parasitics when designing the PCB layout to obtain best
performance. The close-in phase noise of the local oscillator can be optimized at the programmed operating
frequency by a programming bit which increases bias current in the VCO.
.
R_bias
LLOPB
Vvar
Cs pF
L1 nH
LLOP
R_bias
Figure 4 - Low Band (VHF1) External Tank Circuit
R_bias
LMOPB
Vvar
Cs pF
L1 nH
LMOP
R_bias
Figure 5 - Mid Band (VHF3) External Tank Circuit
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Zarlink Semiconductor Inc.
ZL10060
Data Sheet
Cp
LHIPB
Cp
LHOPB
L1 nH
Cp
R_bias
Vvar
LHOP
Cs pF
LHIP
Cp
R_damp
R_bias
Figure 6 - High Band (UHF) External Tank Circuit
1.6
PLL Frequency Synthesizer
The PLL frequency synthesizer section contains all the elements necessary, with the exception of a frequency
reference and loop filter to control a varicap tuned local oscillator, to form a complete PLL frequency synthesized
source. The device allows for operation with a high comparison frequency and is fabricated in high speed logic,
which enables the generation of a loop with good phase noise performance. It can be operated with comparison
frequencies appropriate for frequency offsets as required in digital terrestrial (DTT) receivers.
The LO input signal from the selected oscillator section is routed to an internal preamplifier, which provides gain
and reverse isolation from the divider signals. The output of the preamplifier interfaces directly to the 15-bit
programmable divider, which is of MN+A architecture, with a 16/17 dual modulus prescaler. The A counter is 4-bits,
and the M counter is 11 bits.
The output of the programmable divider is fed to the phase comparator where it is compared in both phase and
frequency domain with the comparison frequency which is derived either from the on-board crystal controlled
oscillator, or from an external reference source. In both cases the reference frequency is divided down to the
comparison frequency by the reference divider, which is programmable into 1 of 16 ratios.
The output of the phase detector feeds a charge pump and loop amplifier section, which when used with an
external loop filter, integrates the current pulses into the varactor control voltage.
The programmable divider output, Fpd, divided by two and the reference divider output, Fcomp, can be switched to
port P0 by programming the device into a test mode.
The PLL includes a lock detect circuit. The lock detect output is available by reading the Status byte on the I2C
interface
1.7
General Purpose Switching Ports
The ZL10060 has four output switching ports. Three of these ports (GPP[3:1]) incorporate a 10 kohm pull up
resistor. The remaining port (GPP0) is an open collector switch. These ports can be used for switching external RF
input stages for example. Ports GPP[1:0] can also be used as test outputs for debug purposes.
1.8
I2C Interface
The ZL10060 is controlled by an I2C data bus and is compatible with both 3.3 V and 5 V control levels.
Data and Clock are fed in on the SDA and SCL lines respectively as defined by I2C bus format. The device can
either accept data (write mode), or send data (read mode). The LSB of the address byte (R/W) sets the device into
write mode if it is low, and read mode if it is high. The device can be programmed to respond to 1 of 4 addresses,
10
Zarlink Semiconductor Inc.
ZL10060
Data Sheet
which enables the use of more than one device in an I2C bus system. The address is selected by applying a voltage
to the ‘ADD’ input.
When the device receives a valid address byte, it pulls the SDA line low during the acknowledge period, and during
following acknowledge periods after further data bytes are received. When the device is programmed into read
mode, the controller accepting the data must pull the SDA line low during all status byte acknowledge periods to
read another status byte. If the controller fails to pull the SDA line low during this period, the device generates an
internal STOP condition, which inhibits further reading.
2.0
Programming
The ZL10060 is fully programmable through the I2C interface. The device can also output data to the controller.
2.1
Programmable Features
Feature
Description
RF programmable
divider
Programs PLL main divider
Reference
programmable divider
Programs PLL reference divider to set required frequency step
Band selection
Selects RF input and appropriate LO oscillator.
AGC Threshold
Sets the Input Power Level Threshold at which the AGC detector starts to generate a
control level.
AGC Decay
Sets the AGC decay current.
Charge pump current
Selects one of the four charge pump current settings.
IF amplifier function
The IF amplifier can be enabled independently of other circuit blocks.
SAWF output select
Select the analog or digital SAW driver output.
Ports GPP[3:1]
These are configured as NPN buffers with 10 kohm pull-up resistors to Vcc.
Logic ‘1’ = on
Logic ‘0’ = off; default on power up
PORT GPP0
This is configured as a NPN open collector buffer. Logic ‘1’ = on
Logic ‘0’ = off; default on power up
VCO Trim
Adjusts the VCO bias current to provide optimum phase noise performance.
ADC input Select
Select either the internal AGC detect output level or the external level applied to the
ADC input pin.
Programmable power
The ZL10060 has various power saving modes.
Test modes
Test modes to monitor and control internal PLL signals.
Table 2 - Programmable Features
2.2
Register Map
There are a total of 7 write registers, the first of which is the Address register. The control registers are described in
detail in the following section. The MSB of each register is written first.
After reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines
whether the byte is interpreted as a byte 2 or 4, a logic '0' indicating byte 2, and a logic '1' indicating byte 4. Having
11
Zarlink Semiconductor Inc.
ZL10060
Data Sheet
interpreted this byte as either byte 2 or 4 the following data byte will be interpreted as byte 3 or 5 respectively. Byte
5 will be followed by byte 6 or a stop condition. Byte 6 will be followed by byte 7 or a stop condition. Byte 7 will be
followed by a stop condition or a byte 2 or byte 4 as described above. Further data bytes can be programmed
following the above-described protocol. A STOP condition can be generated after any data byte, if however it
occurs during a byte transmission, the previous byte data is retained. To facilitate smooth fine tuning, the frequency
data bytes are only accepted by the device after all 15 bits of frequency data have been received, or after the
generation of a STOP condition.
MSB
LSB
ACK
7
6
5
4
3
2
1
0
Address
1
1
0
0
0
MA1
MA0
0
A
Byte 1
Programmable
divider
0
D14
D13
D12
D11
D10
D9
D8
A
Byte 2W
Programmable
divider
D7
D6
D5
D4
D3
D2
D1
D0
A
Byte 3W
Control data
1
C1
C0
R4
R3
R2
R1
R0
A
Byte 4W
Control data
BS1
BS0
SL1
SL0
P3
P2
P1
P0
A
Byte 5W
Control Data
LO1
LO0
ATC
IFE
X
AT2
AT1
AT0
A
Byte 6W
Control Data
SAS
X
AGD
ADS
T3
T2
T1
T0
A
Byte 7W
Table 3 - Control Registers
A
Acknowledge bit
MA1, MA0
Address bits
D14-D0
Programmable division ratio control bits
R4-R0
Reference division ratio select
C1, C0
Charge pump current select
BS1-BS0
Band select bits
SL1-SL0
Power down modes
SAS
SAWF drive output select
P3-P0
P3-P0 port output states
ADS
ADC input select
ATC
AGC Decay Current
AGD
AGC Disable
AT2:AT0
AGC Onset threshold Control
LO1:LO0
LO trim control bits
T3-T0
Test mode control bits
IFE
IF AGC amplifier enable
X
Don’t Care
12
Zarlink Semiconductor Inc.
ZL10060
Data Sheet
Details of the programming registers are shown in the following sections. Default values on power up are also
shown.
2.3
Address Register
The ZL10060 address (MA1, MA0) are determined by the voltage set at the address pin (ADD) as shown in Table 4.
Address Select (Byte 1)
MA1
MA0
Address Input Voltage Level
0
0
0 - 0.1Vcc (Connect to Vee)
0
1
0.2Vcc – 0.3Vcc (Open circuit)
1
0
0.4 Vcc – 0.6 Vcc (30KΩ to Vcc)
1
1
0.9 Vcc - 1.0 Vcc (Connect to Vcc)
Table 4 - Address Bit MA1 and MA0 Settings
2.4
PLL Registers
Bytes 2,3 and 4 are used to program the PLL.
Bit Field
Name
Default
Description
7
-
0
Must be set to 0
6:0
D[14:8]
0
MSB bits of LO Divider register.
Table 5 - Byte 2- LO Divider (MSB)
Bit Field
Name
Default
7:0
D[7:0]
0
Description
LSB bits of LO Divider register.
Table 6 - Byte 3 LO Divider (LSB)
The LO frequency will not be updated until both Byte 1 and Byte 2 have been programmed.
Bit Field
Name
Default
Description
7
-
1
Must be set to 1
6:5
C[1:0]
0
Charge pump current.
4:0
R[4:0]
10011
Reference divider control.
Table 7 - Byte 4 PLL Control
The charge pump current values are selected from the following table:
C1
C0
Current
µA
0
0
+-155
Table 8 - Charge Pump Current Selection
13
Zarlink Semiconductor Inc.
ZL10060
C1
C0
Data Sheet
Current
µA
0
1
+-330
1
0
+-690
1
1
+-1450
Default State on power up = 00
Table 8 - Charge Pump Current Selection
The reference divider ratio can be selected from the following table:
R4
R3
R2
R1
R0
Ratio
0
0
0
1
1
16
0
0
1
0
0
32
0
0
1
0
1
64
0
0
1
1
0
128
0
1
0
1
1
20
0
1
1
0
0
40
0
1
1
0
1
80
0
1
1
1
0
160
1
0
0
1
1
24
1
0
1
0
0
48
1
0
1
0
1
96
1
0
1
1
0
192
1
1
0
1
1
28
1
1
1
0
0
56
1
1
1
0
1
112
1
1
1
1
0
224
Default State on power up = 10011
Table 9 - Reference Divide Ratio Settings
14
Zarlink Semiconductor Inc.
ZL10060
2.5
Data Sheet
Control Register - Byte 5
Bit Field
Name
Default
Description
7:6
BS[1:0]
11
Band Switching
5:4
SL[1:0]
01
Power-up modes
3:0
P[3:0]
0
General Purpose Output ports
Table 10 - Byte 5 Control
The band switching is controlled as shown below:
BS1
BS0
Band Selected
0
0
LO Band
0
1
MID Band
1
0
HI band
1
1
All off
Default state on power up = 11
Table 11 - Band Selection
The various power-up modes are shown below. The IF AGC amplifier is controlled separately The I2C interface and
crystal oscillator circuit is active in all modes.
Power Mode
Section Status
I2C interface
and registers
Crystal
oscillator
PLL & VCO
Converter and IF
stages
Sleep
Enabled
Enabled
Disabled
Disabled
0
PLL and
VCO enabled
Enabled
Enabled
Enabled
Disabled
1
Full
Enabled
Enabled
Enabled
Enabled
SL1
SL0
0
X
1
1
Table 12 - Internal Circuit Block Control
The ZL10060 has four output ports. Ports [3:1] have an internal 10 kohm pull up resistor to Vcc. GPP0 is open
collector.
Function
Bit
0
1
GPP0 output Enable
P0
Off (High Impedance)
On (Current Sink)
GPP1 output Enable
P1
Off
On (Current Sink)
GPP2 output Enable
P2
Off
On (Current Sink)
GPP3 output Enable
P3
Off
On (Current Sink)
Table 13 - GPPO Output Port Control
15
Zarlink Semiconductor Inc.
ZL10060
2.6
Data Sheet
Control Register - Byte 6
Bit Field
Name
Default
Description
7
LO1
0
VCO Bias Trim
6
LO0
0
Not used
5
ATC
0
AGC Decay current select
4
IFE
0
IF AGC Amplifier enable (1 = On)
3
X
0
Not used
2:0
AT[2:0]
0
AGC Threshold Select
Table 14 - Byte 6 Control
The VCO bias trim adjusts the VCO bias to give optimum close-in phase noise. In general this should be set to 1 for
the lower third of the VCO frequency range.
The AGC attack current is fixed at 100 µA however the agc decay current can be programmed to one of two values
as shown below. If the PLL is unlocked (FL = 0), then the ATC control is over-ridden and the AGC decay current is
set to 10µA. When the PLL locks (FL = 1) the decay current reverts to the programmed ATC value.
ATC
AGC Decay Current (µA)
0
10.0
1
0.3
Table 15 - AGC Decay Current Setting
16
Zarlink Semiconductor Inc.
ZL10060
Data Sheet
The AGC threshold can be programmed using the AT[2:0] bits. Note that the programmed value is dBµV peak.
AT2
AT1
AT0
AGC Threshold
(peak signal in dBµV into detector)
0
0
0
120
0
0
1
118
0
1
0
116
0
1
1
114
1
0
0
112
1
0
1
110
1
1
0
107
1
1
1
104
Default state on power up = 000
Table 16 - AGC Threshold Selection
2.7
Control Register - Byte 7
Bit Field
Name
Default
Description
7
SAS
1
Digital SAW Drive Output Select (1 = Digital)
6
X
0
Not used
5
AGD
1
AGC Detector Enable (0 = Enabled)
4
ADS
0
ADC Input select
3:0
T[3:0]
0
Test Bits
Table 17 - Byte 7 Control
The ADC input selection is shown in the table below
ADS
ADC Function
0
AGC Output
1
External ADC input
Table 18 - ADC Input Selection
The test bits T[3:0] allow internal PLL signals to be monitored and also to manually control charge pump current
and AGC detector output. This facilities may be useful during debug. The test bit selection is shown below. The
reserved test modes should not be used.
T3
T2
T1
T0
Test Mode Description
0
0
0
0
Normal operation
0
0
0
1
Reserved Test Mode
0
0
1
0
AGC Sink, Force Iagc = -100 µA
0
0
1
1
AGC Source, Force Iagc = 10 µA
P0 = Output of AGC bias DAC
Table 19 - Test Modes
17
Zarlink Semiconductor Inc.
ZL10060
Data Sheet
T3
T2
T1
T0
Test Mode Description
0
1
0
0
Reserved Test Mode
0
1
0
1
Reserved Test Mode
0
1
1
0
Reserved Test Mode
0
1
1
1
Reserved Test Mode
1
0
0
0
Reserved Test Mode
1
0
0
1
Charge pump sink *
Status byte FL set to logic ‘0’
1
0
1
0
Charge pump source *
Status byte FL set to logic ‘0’
1
0
1
1
Charge pump disabled *
Status byte FL set to logic ‘1’
1
1
0
0
Port P0 = Fpd/2
1
1
0
1
Charge pump sink *
Status byte FL set to logic ‘0’
Port P0 = Fcomp
1
1
1
0
Charge pump source *
Status byte FL set to logic ‘0’
Port P0 = Fcomp
1
1
1
1
Charge pump disabled *
Status byte FL set to logic ‘1’
Port P0 = Fcomp
Table 19 - Test Modes (continued)
2.8
Read Mode
When the device is in read mode, the status byte read from the device takes the form shown in Table 20.
MSB
Address
Status Byte
LSB
ACK
7
6
5
4
3
2
1
0
1
1
0
0
0
MA1
MA0
1
A
Byte 1
POR
FL
1
1
AGF
V2
V1
V0
A
Byte 2R
Table 20 - Read Data Format (MSB is transmitted first)
The following describes data read through the read byte;
•
Bit 7 (POR) is the power-on reset indicator, and this is set to a logic '1' if the Vcc supply to the device has
dropped below 3 V (at 25°C), e.g., when the device is initially turned ON. The POR is reset to '0' when the
read sequence is terminated by a STOP command. When POR is set high this indicates that the
programmed information may have been corrupted and the device reset to power up condition.
•
Bit 6 (FL) is the PLL lock flag and indicates whether the device is phase locked, a logic '1' is present if the
device is locked, and a logic '0' if the device is unlocked. The FL bit is set after 64 consecutive comparison
cycles in lock.
18
Zarlink Semiconductor Inc.
ZL10060
•
Data Sheet
Bit 3 (AGF) is the AGC detector flag and indicates whether the AGC detector is active.
AGF
AGC Activity Flag
0
AGC active, VAGC < 4 V
External RF LNA gain is reduced
1
AGC not active, VAGC >4 V
External RF LNA gain is at maximum
Table 21 - AGC Activity Flag Settings
•
Bits 2:0 (V2:V0) contain the ADC output data. The ADC output is sampled on the ACK clock of the read
address byte.
Input Level (V)
V2
V1
V0
< 0.32 Vcc
0
0
0
0.32Vcc to 0.48Vcc
0
0
1
0.48Vcc to 0.64Vcc
0
1
0
0.64Vcc to 0.80Vcc
0
1
1
> 0.80Vcc
1
0
0
Table 22 - ADC Output Values
19
Zarlink Semiconductor Inc.
1.5uH
L13
IN-
gnd
Figure 7 - Typical Application Circuit (DVB-T)
Driver Output
Analog SAW
Digital Demodulator
IF Output to
1
IN+
X6874D
SF1
5
4
4.000MHz
10nF
C50
10nF
40
39
38
37
46
45
44
43
48
gnd 47
+5V
150pF
C18
gnd
41
+5V
42
IFAGC
ADC
C51
10nF
10nF
C35
47pF
nm
nm
gnd
C22
10nF
1nF
C27
1nF
C26
+5V
C23
27pF
C28
C19
R27
R26
10nF
C33
gnd
gnd X1
10nF
C1
10nF
C15
10nF
C37
OP-
OP+
C54
10k
R7
18k
gnd
BCW33
IFOPB
IFOP
VeeIF
VccIF
XTAL
XCAP
VccIFO
SDB
SD
VccDIG
PUMP
100nF
C46
100pF
C32
0R
R13
gnd
TR1
DRIVE
R16
20k
R8
36
IFINB
100pF
220pF
34
C20
gnd
gnd
+5V
33
10nF
IFIN
2
GND
3
35
IFAGC
1
6R8
R14
2n5H (air)
L6
BB555
D3
2p2F 2p2F
IC1
ZL1006X
ZL10060
2p2F
10nF
C34
gnd
gnd
3k3
R6
1k
R3
2p2F
C11
6R8
R15
gnd
C13 C12 C14
10nF
C30
27pF
C16
1k
32
LHIPB
C17a
SAB
2
VccOSC
SA
3
VeeOSC
ADC
4
1k
SDA
5
31
LHOPB
SCL
6
gnd
7
8.2nF
LHIP
R5
12n5H (air)
L4
68pF
C10
BB640
D2
LMOP
+30V
LMOPB
30
LHOP
ADD
29
AGCout
8
gnd
SIPB
SDA
SIP
GPP0
GPP1
GPP2
VeeRF
LOIP
RFINB
MIDIP
HIIP
HIIPB
C47 gnd
100pF
SCL
3k3
GPP3
+5V
I2C
AGC Out
1k
R1
R4
25
LLOP
R9
LLOPB
C21
CNOPB
9
28
CNOP
10
27
Conti nuity
11
26
VccRF
12
Zarlink Semiconductor Inc.
Gnd
20
10nF
C49
gnd
0
TP
13
14
15
16
17
18
19
20
gnd
1nF
21 C8
22
23
24
100nH (air)
L2
100pF
C2
BB640
D1
gnd
3k3
R2
Coil Data
1nF
1nF
100pF
100pF
12pF
C39
12pF
nm
C6
680nH
C25 L10
X5
nm
nm
18pF
18pF
12pF
C48
12pF
C38
680nF
L9
gnd gnd
1nF
C24
+5V
0R
X7
0R
X6
gnd
1
2
3
X2
X3
gnd gnd
nm
X4
C4
Interstage Filter
GPP0
GPP1
GPP2
C7
C5
C3
C40
GPP3
680nF
L11
6
4
+30V
+5V
IFAGC
gnd
gnd
gnd
10nF
C53
L6: 2n5H as 16mm 24 swg En Cu formed into 5/4 turns on 2mm dia
space wound
L4: 12.5nH as 30mm 24 swg En Cu formed into 2.5 turns on 2mm dia
space wound
L2: 100nH as 8.5 turns 24 swg (0.56mm) En Cu on 2.5mm dia
close wound
gnd
TP3
+
10uF
C56
2u2F
gnd
+ C36
RF IN (VHF 1)
RF IN (VHF 3)
RF IN (UHF)
1
2
3
4
3.0
PLL loop filter
ZL10060
Data Sheet
Applications Information
A typical applications circuit is shown in the following diagram.
ZL10060
Data Sheet
The low (VHF1) and Mid (VHF3) bands are single ended however the high band (UHF) should be differential. All IF
signals are differential.
It is essential to have good RF layout around the RF stages, i.e., RF inputs and the VCOs. Track lengths around the
VCO’s should be minimized to reduce track inductance.
The layout should be organized to give good isolation between the IF signal paths. In particular good isolation is
required between the outputs and inputs of the IF AGC amplifier. Isolation across the SAW filter is also important to
ensure rejection of unwanted adjacent signals. This can be achieved by routing input and output tracks on opposite
sides of the board.
It is also important to have good isolation between the high level IF signal and the crystal oscillator circuit to
minimize any interactions. Care should be taken when locating IF tuning inductors to ensure there is no radiation to
other parts of the circuit.
The crystal oscillator can also provide a clock signal to the demodulator. This can be done by taking the oscillator
signal from the crystal series capacitor (27 pF) as shown in the following diagram.
Figure 8 - Crystal Oscillator Circuit (4 MHz)
21
Zarlink Semiconductor Inc.
ZL10060
Data Sheet
The interstage filter between the converter outputs provides some rejection of adjacent channels (N +/- 2).The
recommended values are shown in Figure 9. The choice of components is important not only to give a flat response
but also to provide an impedance transformation.
The specified noise figure for the low and mid bands assumes that there will be a network before the device to provide
image rejection. In a tuner this would be part of the input tracking filters but for test purposes a network is shown in
Figure 10.
R source
R source
Vcc
SAWF Drive Amplifier Input
L1
CNOPB
SIP
Cc
C1
L1
L2
C1
Rterm
C2
Rterm
C1
Cc
CNOP
IF
0.5 dB
BW
MHz
MHz
Rsource
Rterm
L1
L2
C1
Cc
C2
36
12
700
350
560
560
18
12
8.2
Type
0.5 dB Chebycheff
SIPB
Component values
Figure 9 - Interstage Filter
22
Zarlink Semiconductor Inc.
ZL10060
50
Data Sheet
C1
Vs
1nF
L1
MIDIP/LOIP
IPREF
C2
DUT
1nF
Gnd
Frequency
Band
C1
L1
C2
MHz
pF
nH
pF
90
46
20
299
20
LOW
200
156
8
65
8
MID
240
196
8
41
8
MID
500
446
2.1
21
4
LO
RF IN
MHz
LOW
Figure 10 - Noise Figure Measurement Conditions
The optimum charge pump and LO trim settings for the application circuit shown in Figure 8 are shown in the table
below. These give the optimum phase noise performance for the circuit shown. The changes in charge pump
current compensate for frequency and VCO gain variations.
Frequency Range
Charge Pump Setting
CP
LO Trim
LO1
VHF1 50 -110 MHz
01
1
VHF1 100 -160 MHz
10
1
VHF3 160 - 250 MHz
10
1
VHF3 250 - 350 MHz
01
0
VHF3 350 - 450 MHz
10
0
UHF 450 - 500 MHz
00
1
UHF 500 - 700 MHz
01
1
UHF 700 - 800 MHz
10
1
UHF 800 - 850 MHz
11
1
Table 23 - Optimum CP and LO Trim Settings
23
Zarlink Semiconductor Inc.
ZL10060
4.0
Pin
No.
1
Data Sheet
PIn Circuit Information
Pin
Name
IFAGC
Port
Sense
Input
Function
Schematic
IF AGC control
IFA G C
3K
V REF
3K
2,
3
SAB,
SA
Output,
Output
SAW filter driver output A inverse
SAW filter driver output A
V cc
SA
50
4
ADC
Input
ADC input
V cc
A D C
5
SDA
Bi-directional I2C bus serial data input/output
V cc
SDA
6
SCL
Input
I2C bus serial clock input
V cc
SCL
24
Zarlink Semiconductor Inc.
SAB
ZL10060
Pin
No.
7
Pin
Name
ADD
Port
Sense
Input
Data Sheet
Function
Schematic
I2C address select
V cc
63k
3k
ADD
21k
8
AGCOP Output
AGC output
V cc
100
AGCOP
1K
9,
10
CNOPB, Output,
CNOP
Output
Converter Output inverse
Converter Output
Vcc
500
500
CNOPB
CNOP
11
Cont
-
Paddle
-
12
VccRF
Supply
RF section supply
-
13,
14
SIPB
SIP
Input,
Input
SAW filter driver input inverse,
SAW filter driver input
V cc
S IP
S IP B
15
GPP0
Output
250
1 .1 K
Switching port/Test output 1
GPP0
25
Zarlink Semiconductor Inc.
ZL10060
Pin
No.
16
Pin
Name
GPP1
Port
Sense
Output
Data Sheet
Function
Schematic
Switching port/Test output 2
V cc
10K
GPP1
GPP2
GPP3
17
GPP2
Output
Switching port
As GPP1 (pin16)
18
VeeRF
Supply
RF section ground
-
19,
20,
21
LOIP
IPREF
MIDIP
Input,
Input,
Input
Low band input,
Mid- and Low-band i/p reference,
Mid-band input
22,
23
HIIP,
HIIPB
Input,
Input
Hi-band input,
Hi-band input inverse
24
GPP3
Output
Switching Port
25,
26
LLOP,
LLOPB
Output
Low band oscillator output,
Low-band oscillator output inverse
LO IP
IP R E F
M ID IP
H IIP
H IIP B
As GPP1 (pin16)
LLOP
LLOPB
27,
28
LMOP, Output,
LMOPB Output
Mid-band oscillator output,
Mid-band oscillator output inverse
LMOP
LMOPB
26
Zarlink Semiconductor Inc.
ZL10060
Pin
No.
29,
30,
31,
32
Pin
Name
LHIP,
LHOP,
LHOPB,
LHIPB
Port
Sense
Input,
Output,
Output,
Input
Data Sheet
Function
Schematic
High band oscillator input,
High-band oscillator output,
High-band oscillator output inverse,
High-band oscillator input inverse
Vcc
350
LHOPB
350
LHOP
LHIP
33
VeeOSC Supply
LO ground
-
34
VccOSC Supply
LO supply
-
35,
36
IFIP,
IFIPB
IF AGC amp input,
IF AGC amp input inverse
Input,
Input
LHIPB
IF IP
37,
38
DRIVE,
PUMP
Output,
Output
Loop amplifier drive output,
Loop amp charge pump output
IF IP B
Vcc
PUMP
DRIVE
340
39
VccDIG Supply
Digital section supply
40,
41
SD,
SDB
SAW filter driver output D,
SAW filter driver o/p D inverse
Output,
Output
V cc
SD
50
42
VccIF
Supply
SAWF output supply
43
XCAP
Input
Reference osc feedback input
SDB
V cc
110
XTAL
XCAP
0 .2 m A
44
XTAL
Output
Reference osc crystal drive
27
Zarlink Semiconductor Inc.
See XCAP (pin 43)
ZL10060
Pin
No.
Pin
Name
Port
Sense
Data Sheet
Function
Schematic
45
VccIF
Supply
IF AGC supply
-
46
VeeIF
Supply
IF AGC ground
-
47,
48
IFOP,
IFOPB
Output,
Output
IF AGC amp output,
IF AGC amp inverse output
Vcc
IF O P
Paddle Vee
-
-
-
28
Zarlink Semiconductor Inc.
ZL10060
5.0
Data Sheet
Absolute Maximum Ratings
All voltages are referred to Vee at 0 V.
Characteristic
Supply voltage
Min.
Max.
Units
-0.3
6
V
Conditions
dBµV Transient condition only
RF input voltage
117
Maximum voltage on SDA, SCL
5.5
V
Vcc = 0 to 5.5V
Vcc+0.3
V
The voltage on any pin must not exceed 6 V
20
mA
150
oC
125
oC
Power applied
C/W
Package paddle soldered to ground
Max voltage on all remaining signal pins
-0.3
Total port current
Storage temperature
-55
Junction temperature
Package thermal resistance
(chip to ambient)
27
o
ESD protection
2.0
kV
All pins except 9,10
Mil-std 883B method 3015 cat1
1.25
kV
Pins 9, 10 only
6.0
Operating Range
All voltages are referred to Vee at 0 V.
Characteristic
Min.
Max.
Units.
Supply voltage
4.5
5.5
V
Functional operation,
specification not guaranteed
Supply voltage
4.75
5.25
V
Full specification
o
Ambient Temperature
-20
85
Low Band Input Frequency
50
170
MHz
Mid Band Input Frequency
140
460
MHz
High Band Input Frequency
400
900
MHz
C
29
Zarlink Semiconductor Inc.
Conditions
ZL10060
7.0
Data Sheet
Electrical Characteristics
Test conditions (unless otherwise stated). T = 25oC, Vee= 0 V, Vcc = 5 V, IF Frequency = 36 MHz. All signals are differential with the exception of
VHF1 and VHF3 inputs.
Characteristic
Min.
Typ.
Max.
Units
Conditions
Normal operation
117
140
mA
Total Current – UHF band
All switching ports off
All sections active
110
134
mA
Total Current - VHF Bands
All switching ports off
All sections active except
AGC IF amplifier
92
mA
UHF Band. Switching ports off
85
mA
VHF Bands. Switching ports off
Sleep Mode
9
mA
Crystal oscillator and data interface
enabled
33
mA
PLL and crystal oscillator enabled
Supply current
Composite system to SAW Filter driver outputs
VHF1 Band
Conversion gain
29
32
35
dB
RFin = 54 MHz. Single ended input
Conversion gain
29
32
35
dB
RFin = 155 MHz. Single ended input
9
11
dB
Rs = 50 Ω, SSB with input matching
network. See Figure 10.
Noise Figure
OPIP3
135
146
dBµV
Two output tones at 110 dBµV
Output level causing 1%
cross modulation
113
120
dBµV
Note 2
Output level causing 1.5 kHz
FM
113
120
dBµV
Note 3
2.5
kHz
Transmission repetition rate of 20
msec minimum with no change to
previously loaded data, at 100 kHz
SCL rate
I2C bus transmission induced
LO frequency modulation
N+5 Direct modulation of
VCO
-40
dBc
Local oscillator sidebands induced by
an input carrier at 80 dBµV offset from
local oscillator by 100 kHz
Supply ripple spurious
-40
dBc
Residual FM induced on local
oscillator by 20 mVp-p ripple on Vcc at
500 kHz
Local oscillator leakage to
any band input
dBµV
30
30
Zarlink Semiconductor Inc.
ZL10060
Characteristic
Min.
Typ.
IPIP2
134
143
dBµV
Two input tones at 87 dBµV at
90 MHz and 66 MHz with local
oscillator at 114 MHz
IPIP3
112
120
dBµV
Desired = 54 MHz at 45 dBµV
Undesired = 60 and 72 MHz at
87 dBµV
IPIP3
112
119
dBµV
Desired = 155 MHz at 45 dBµV
Undesired = 161 and 173 MHz at
87 dBµV
P1dB
93
106
dBµV
100
Ω
10
nH
Output Impedance
Max.
Data Sheet
Units
Phase Noise, SSB
Conditions
PLL Loop Bandwidth ~ 3 kHz
fcomp = 166.7 kHz
1 kHz
-90
-70
dBc/Hz
10 kHz
-95
-86
dBc/Hz
100 kHz
-115
-106
dBc/Hz
-135
dBc/Hz
-50
dBc
10 MHz
Reference spurs
-90
Phase Noise, SSB
Noise Floor
Narrow PLL Loop Bandwidth
fcomp = 62.5 kHz
10 kHz
-97
dBc/Hz
100 kHz
-115
dBc/Hz
Composite system to SAW Filter driver outputs
VHF3 Band
Conversion gain
29
32
35
dB
RFin = 164 MHz Single ended input
Conversion gain
29
32
35
dB
RFin = 442 MHz Single ended input
9
11
dB
Rs = 50 Ω, SSB with input matching
network. See Figure 10.
Noise Figure
OPIP3
135
146
dBµV
Two output tones at 110 dBµV
Output level causing 1%
cross modulation
113
120
dBµV
Note 2
Output level causing 1.5 kHz
FM
113
120
dBµV
Note 3
31
Zarlink Semiconductor Inc.
ZL10060
Characteristic
Min.
I2C bus transmission induced
LO frequency modulation
Typ.
Max.
2.5
N+5 Direct modulation of
VCO
-
Supply ripple spurious
Local oscillator leakage to
any band input
Data Sheet
Units
Conditions
kHz
Transmission repetition rate of 20
msec minimum with no change to
previously loaded data, at 100 kHz
SCL rate
-40
dBc
Local oscillator sidebands induced by
an input 750 MHz carrier at 80 dBµV
offset from local oscillator by 100 kHz.
-40
dBc
Residual FM induced on local
oscillator by 20 mVp-p ripple on Vcc at
500 kHz
30
dBµV
IPIP2
134
143
dBµV
Two input tones at 89 dBµV at
198 MHz and 398 MHz with local
oscillator at 240 MHz
IPIP3
112
122
dBµV
Desired = 165 MHz at 45 dBµV
Undesired = 171 and 183 MHz at
89 dBµV
IPIP3
112
119
dBµV
Desired = 438 MHz at 45 dBµV
Undesired = 444 and 456 MHz at
89 dBµV
P1dB
-95
107
dBµV
100
Ω
10
nH
Output Impedance
Phase Noise, SSB
PLL Loop Bandwidth ~ 3 kHz
fcomp = 166.7 kHz
1 kHz
-87
-70
dBc/Hz
10 kHz
-92
-86
dBc/Hz
100 kHz
-114
-106
dBc/Hz
-135
dBc/Hz
-50
dBc
10 MHz
Reference spurs
-90
Phase Noise, SSB
Noise Floor
Narrow PLL Loop Bandwidth
fcomp = 62.5 kHz
10 kHz
-94
dBc/Hz
100 kHz
-114
dBc/Hz
Composite system to SAW Filter driver outputs
UHF Band
Conversion gain
35
38
41
dB
32
Zarlink Semiconductor Inc.
RFin = 450 MHz
ZL10060
Characteristic
Conversion gain
Data Sheet
Min.
Typ.
Max.
Units
35
38
41
dB
RFin = 866 MHz
6
8
dB
Rs = 50 Ω, No image correction
Noise Figure
Conditions
OPIP3
135
146
dBµV
Two output tones at 110 dBµV
Output level causing 1%
cross modulation
113
120
dBµV
Note 2
Output level causing 1.5 kHz
FM
113
120
dBµV
Note 3
2.5
kHz
Transmission repetition rate of
20 msec minimum with no change to
previously loaded data, at 100 kHz
SCL rate
I2C bus transmission induced
LO frequency modulation
N+5 Direct modulation of
VCO
-30
dBc
Local oscillator sidebands induced by
an input 750 MHz carrier at 80 dBµV
offset from local oscillator by 100 kHz
Supply ripple spurious
-40
dBc
Residual FM induced on local
oscillator by 20 mVp-p ripple on Vcc at
500 kHz
Local oscillator leakage to
any band input
60
dBµV
IPIP2
125
159
dBµV
Two input tones at 89 dBµV at
198 MHz and 398 MHz with local
oscillator at 240 MHz
IPIP3
108
115
dBµV
Desired = 438 MHz at 45 dBµV
Undesired = 444 and 456 MHz at
85 dBµV
IPIP3
108
112
dBµV
Desired = 858 MHz at 45 dBµV
Undesired = 864 and 876 MHz at
85 dBµV
P1dB
91
99
dBµV
100
Ω
10
nH
Output Impedance
Phase Noise, SSB
PLL Loop Bandwidth ~ 3 kHz
fcomp = 166.7 kHz
1 kHz
-78
-70
dBc/Hz
10 kHz
-89
-84
dBc/Hz
100 kHz
-113
-106
dBc/Hz
-135
dBc/Hz
-50
dBc
10 MHz
Reference spurs
-80
33
Zarlink Semiconductor Inc.
Noise Floor
ZL10060
Characteristic
Min.
Typ.
Max.
Data Sheet
Units
Phase Noise, SSB
Conditions
Narrow PLL Loop Bandwidth
fcomp = 62.5 kHz
10 kHz
-91
dBc/Hz
100 kHz
-113
dBc/Hz
AGC Detector and ADC
Operating frequency range
16
AGC Threshold Level
72
dBµV
120
ADC leakage current
60
-60
AGC source current
AGC sink current
VADC = 4.0 V
nA
VADC = 0.5V
See Table 15
10
13.3
µA
0.25
0.33
0.43
µA
-65
-100
-145
µA
1
20
AGCOP output voltage range
AGC attack current, triggered by
detected level exceeding AGC attack
point
µsec
1
AGC input level response
AT[2:0] = 0
nA
6.8
AGC sink current 90% rise
and fall time
AGCOP output impedance
MHz
0.5
4
dB
Change in input level for AGC sink
current to change from high
impedance to 90% of maximum
value, with AGC operative
MΩ
AGC inactive
V
Minimum gain required
V
Maximum gain required
External AGC voltage
0.5
Vcc-0.4
V
Maximum external voltage range
which can be applied to AGCOP
when disabled
AGCOP leakage current
-50
50
nA
Over normal operating range
V
See Table 22
V
See Table 22
V
AGF flag set to 1
ADC step size, LSB
0.16Vc
c
ADC step size accuracy
0.01Vc
c
AGCout_flag
High threshold
AGCout_flag
Low threshold
Vcc0.66
Vcc0.76
34
Zarlink Semiconductor Inc.
AGF flag set to 0
ZL10060
Characteristic
Min.
Typ.
Max.
Data Sheet
Units
Conditions
IF amplifier
Supply Current
25
Frequency range
16
Input impedance
1.5
Gain
(Voltage conversion gain,
differential source to
maximum load as defined
below)
2
72
MHz
2.8
kΩ
1.5
pF
61
66
70
dB
VIFAGC = 3.0 V
48
57
65
dB
VIFAGC = 2.2 V
21
25
29
dB
VIFAGC = 1.2 V
8
17
22
dB
VIFAGC = 0.5 V
6.3
8.5
Noise Figure
AGC range
41
48
AGC control slope
25
31
AGC input current
Gain variation within channel
OPIP3
mA
130
Rs=50 Ω
dB
38
dB/V
50
µA
0.25
dB
dBµV
141
Output impedance
120
Ω
Maximum load condition
4.7
kΩ
15
pF
1.2≤VAGC≤2.2
Channel bandwidth 8 MHz within
operating frequency range, with
maximum load as defined below
Two output tones at 109 dBµV within
output channel
Gain range = 21 dB to maximum
Differential load
I2C BUS
SDA SCL
Input high voltage
2.55
5.5
V
Input low voltage
0
1.4
V
10
µA
Vin=5.5 V, Vcc=5.25 V
10
µA
Vin=5.5 V, Vcc=0 V
µA
Vin= 0 V, Vcc=5.25 V
Input current High
Input Current Low
Hysteresis
SDA output voltage
SCL clock rate
-10
0.4
V
0.4
V
Isink=3 mA
0.6
V
Isink=6 mA
100
kHz
35
Zarlink Semiconductor Inc.
ZL10060
Characteristic
Min.
Typ.
Max.
Data Sheet
Units
ADD (address) select
Conditions
See Table 4
Input high current
1
mA
Vin=VccD
Input low current
-0.5
mA
Vin=Vee
PLL Synthesizer
Charge pump output current
See Table 8
VPUMP=2 V
Charge pump output leakage
Charge pump drive output
current
+-3
±10
nA
Note 4
mA
VDRIVE=0.7 V
16
MHz
Application as in Figure 13 with
4 MHz crystal
150
Ω
4 MHz parallel resonant crystal
0.5
Crystal frequency
4
Recommended crystal series
ESR
25
External reference input
frequency
4
20
MHz
Sine wave coupled through 10 nF
capacitor
0.2
2
Vpp
Sine wave coupled through 10nF
capacitor
Vpp
Recommended level for optimum
phase noise at 4 MHz
External reference drive level
70
0.5
Phase detector comparison
frequency
RF division ratio
31.25
250
240
32767
kHz
Switching ports GPP3-GPP0
Sink current
Pull up resistor GPP3- GPP1
Leakage current
10
mA
Vport = 0.4
kΩ
10
10
µA
Vport = Vcc, Port P0 only
Note 1:
0 dBm =107 dBµV. All input levels are specified as voltage that would be present if input signal generator was terminated in
50 ohms
Note 2:
Wanted signal (picture carrier) = 101 dBmV at output. Undesired signal (sound carrier) at 5.25 MHz offset modulated with
1 kHz 80% AM. Increase undesired signal to give 1% AM on wanted signal.
Note 3:
Wanted signal at 101 dBmV. Unwanted signal at 5.25 MHz offset modulated with 1 kHz 50% AM. Increase undesired signal to
give 1.5 kHz FM on wanted signal
Note 4:
Current into PUMP pin with 20 µA current from DRIVE pin
36
Zarlink Semiconductor Inc.
D
D2
A
D1
A1
E1
E
E2
L
b
e
SEATING PLANE
Package Code
c Zarlink Semiconductor 2003 All rights reserved.
ISSUE
1
ACN
DATE
APPRD.
25-02-2004
Previous package codes
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However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
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certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
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Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
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TECHNICAL DOCUMENTATION - NOT FOR RESALE