CY25701 Programmable High Frequency Crystal Oscillator with Spread Spectrum (SSXO) and No Spread Spectrum (XO) Option Features Benefits ■ Crystal Oscillator with Spread Spectrum Clock (SSXO) ■ ■ No Spread Spectrum (XO) Option ■ Wide operating output clock frequency range of 10 –166 MHz ■ Programmable spread spectrum with nominal 31.5 kHz modulation frequency Provides a wide range of spread percentages for maximum electromagnetic interference (EMI) reduction to meet regulatory agency electromagnetic compliance (EMC) requirements. Reduces development and manufacturing costs and time-to-market. ■ ■ Center spread: ±0.25% to ±2.0% This versatile programming feature enables the user to switch between SSXO (with Spread) and XO (without Spread) functions with ease. ■ Down spread: –0.5% to –4.0% ■ Internal PLL to generate up to 166 MHz output. ■ No spread: ± 0.0% ■ Suitable for most PC, consumer, and networking applications ■ Integrated phase-locked loop (PLL) ■ Application compatibility in standard and low-power systems ■ 85 ps typical cycle-to-cycle jitter with SSCLK = 133 MHz ■ ■ 3.3V operation ■ Output enable function ■ Package available in 4-Pin ceramic LCC SMD In house programming of samples and prototype quantities is available using CY3672 programming kit and CY3724 socket adapters. Production quantities are available through Cypress’ value added distribution partners or by using third party programmers from BP Microsystems, and HiLo Systems, and others. ■ Pb-free package ■ Industrial temperature from –40°C to 85°C Pin Configuration Logic Block Diagram CY25701 4-pin Ceramic SMD RFB PLL with MODULATION CONTROL 4 VDD SSCLK OE 1 VSS 2 3 C XIN PROGRAMMABLE CONFIGURATION C XOUT OUTPUT DIVIDERS and MUX 3 SSCLK 1 OE 4 2 VDD VSS Cypress Semiconductor Corporation Document Number: 001-07313 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 24, 2007 CY25701 Pin Definition Pin Name Description 1 OE Output Enable pin: Active HIGH. If OE = 1, SSCLK is enabled 2 VSS Power supply ground 3 SSCLK Spread spectrum clock output (with or without spread) 4 VDD 3.3V power supply Functional Description Programming Description The CY25701 is a Spread Spectrum Crystal Oscillator (SSXO) IC used to reduce the EMI found in today’s high speed digital electronic systems. Factory and Field Programmable CY25701 The device uses a Cypress proprietary PLL and Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the embedded input crystal. By frequency modulating the clock, the measured EMI at the fundamental and harmonic frequencies are greatly reduced. This reduction in radiated energy can significantly reduce the cost of complying with regulatory agency (EMC) requirements and improve time-to-market without degrading system performance. The CY25701 uses a programmable configuration memory array to synthesize output frequency and spread%. The spread percentage is programmed to either center spread or down spread with various spread percentages. The range for center spread is from ±0.25% to ±2.00%. The range for down spread is from –0.5% to –4.0%. Contact the factory for smaller or larger spread percentage amounts if required. Refer to Table 2 for spread selection and no spread values. The frequency modulated SSCLK output is programmable from 10 to 166 MHz. The CY25701 is available in a 4-pin ceramic SMD package with an operating temperature range of –40 to 85°C. Factory and field programming is available for samples and manufacturing by Cypress and its distributors. Submit your request to the local Cypress Field Application Engineer (FAE) or sales representative. Once the request is processed, you will receive a new part number, samples, and data sheet with the programmed values. This part number is used for additional sample request and the production orders. Contact your local Cypress FAE or sales representative for details. Additional information on the CY25701 is available at the Cypress web site www.cypress.com. Output Frequency, SSCLK Output (SSCLK, pin 3) The modulated frequency at the SSCLK output is produced by synthesizing from the embedded crystal oscillator frequency input. The range of synthesized clock is from 10 to 166 MHz. Spread Percentage (SSCLK, pin 3) The SSCLK spread is programmable to various spread percentage values from ±0.25% to ±2.0% for center spread and from –0.5% to –4.0% for down spread. Refer to Table 2 for available spread options. Enter ±0.0% (No spread) for XO (crystal oscillator) without spread option. Frequency Modulation (SSCLK, pin 3) The default frequency modulation is programmed at 31.5 kHz for all SSCLK frequencies from 10 to 166 MHz. Alternate frequency modulations at 30.1 kHz or 32.9 kHz are selectable using CyberClocksOnline™ software. Contact the factory for other alternate modulation frequencies if required. Table 1. Programming Data Requirement Pin Function Output Frequency Spread Percent Code Frequency Modulation Pin Name SSCLK SSCLK SSCLK Pin# 3 3 3 Units MHz % kHz Program Value ENTER DATA ENTER DATA ENTER DATA 31.5 Note 1. ±0.0% or Code “Z” for XO (No-Spread) option. Document Number: 001-07313 Rev. *B Page 2 of 8 CY25701 Table 2. Spread Percent Selection Center Spread Down Spread Code A B C D E F Z Percentage ±0.25% ±0.5% ±0.75% ±1.0% ±1.5% ±2.0% ±0.0% Code G H J K L M Z Percentage –0.5% –1.0% –1.5% –2.0% –3.0% –4.0% ±0.0% Absolute Maximum Ratings Storage Temperature (Non-condensing) .... –55°C to +100°C Supply Voltage (VDD).....................................–0.5V to +7.0V DC Input Voltage ................................... –0.5V to VDD + 0.5V Junction Temperature ................................ –40°C to +125°C Data Retention @ Tj = 125°C.................................>10 years Package Power Dissipation...................................... 350 mW Operating Conditions Min Typ Max Unit VDD Parameter Supply voltage Description 3.00 3.30 3.60 V TA Ambient temperature (commercial) –20 – 70 °C TA Ambient temperature (industrial) –40 – 85 °C CLOAD Max. load capacitance @ pin 3 – – 15 pF FSSCLK SSCLK output frequency, CLOAD = 15 pF 10 – 166 MHz FMOD Spread Spectrum Modulation Frequency 30.0 31.5 33.0 kHz TPU Power up time for VDD to reach minimum specified voltage (power ramp must be monotonic) 0.05 – 500 ms Min Typ Max Unit 10 12 – mA DC Electrical Characteristics Parameter Description Condition IOH Output high current (pin 3) VOH = VDD – 0.5, VDD = 3.3V (source) IOL Output low current (pin 3) VOL = 0.5, VDD= 3.3V (sink) 10 12 – mA VIH Input high voltage (pin 1) CMOS levels, 70% of VDD 0.7VDD – VDD V VIL Input low voltage (pin 1) CMOS levels, 30% of VDD – – 0.3VDD V IIH Input high current (pin 1) Vin = VDD – – 10 μA IIL Input low current (pin 1) Vin = VSS IOZ Output leakage current (pin 3) Three-state output, OE = 0  – – 10 μA –10 – 10 μA Input capacitance (pin 1) Pin 1, or OE – 5 7 pF IVDD Supply current VDD = 3.3V, SSCLK = 10 to 166 MHz, CLOAD = 0, OE = VDD – – 50 mA Δf/f Initial accuracy at room temp. TA = 25°C, 3.3V –25 – 25 ppm Freq. stability over temp. range TA = –20°C to 70°C, 3.3V –25 – 25 ppm Freq. stability over voltage range 3.0 to 3.6V –12 – 12 ppm Aging –5 – 5 ppm CIN Document Number: 001-07313 Rev. *B TA = 25°C, First year Page 3 of 8 CY25701 AC Electrical Characteristics Parameter Description Condition Min Typ Max Unit DC Output Duty Cycle SSCLK, Measured at VDD/2 45 50 55 % tR Output Rise Time 20%–80% of VDD, CL = 15 pF – – 2.7 ns tF Output Fall Time 20%–80% of VDD, CL = 15 pF – – 2.7 ns TCCJ1 Cycle-to-Cycle Jitter SSCLK (Pin 3) SSCLK ≥133 MHz, Measured at VDD/2 – 85 200 ps 25 MHz ≤ SSCLK <133 MHz, Measured at VDD/2 – 215 400 ps SSCLK < 25 MHz, Measured at VDD/2 – – 1% of 1/SSCK s TOE1 Output Disable Time (pin1 = OE) Time from falling edge on OE to stopped outputs (Asynchronous) – 150 350 ns TOE2 Output Enable Time (pin1 = OE) Time from rising edge on OE to outputs at a valid frequency (Asynchronous) – 150 350 ns TLOCK PLL Lock Time Time for SSCLK to reach valid frequency – – 10 ms Application Circuit Figure 1. Application Circuit Diagram 0.1 µF Power 4 3 VDD SSCLK CY25701 OE 1 VSS 2 VDD Note 2. Guaranteed by characterization, not fully tested. 3. Jitter is configuration dependent. Actual jitter depends upon output frequencies, spread percentage, temperature, and output load. For more information, see the application note, “Jitter in PLL Based Systems: Causes, Effects, and Solutions” available at http://www.cypress.com/clock/appnotes.html or contact your local Cypress Field Application Engineer. Document Number: 001-07313 Rev. *B Page 4 of 8 CY25701 Switching Waveforms Figure 2. Duty Cycle Waveform Cycle Timing (DC = t1A/t1B) t1A SSCLK t1B Figure 3. Output Rise/Fall Time Waveform VDD SSCLK 0V Tr Tf Output Rise time (Tr) = (0.6 x VDD)/SR1 (or SR3) Output Fall time (Tf) = (0.6 x VDD)/SR2 (or SR4) Refer to AC Electrical Characteristics table for SR (Slew Rate) values. Figure 4. Output Enable/Disable Timing Waveforms OUTPUT ENABLE VDD VIH VIL 0V TOE2 High Impedance SSCLK (Asynchronous) TOE1 Document Number: 001-07313 Rev. *B Page 5 of 8 CY25701 Informational Graphs  172.5 161.5 169.5 169 168.5 168 167.5 167 166.5 166 165.5 165 164.5 164 163.5 163 160.5 162.5 171.5 Spread Spectrum Profile: Fnom=166MHz, Fmod=30kHz, Spread%= -4% 170.5 169.5 168.5 167.5 166.5 Fnominal 165.5 164.5 163.5 162.5 Spread Spectrum Profile: Fnom=166MHz, Fmod=30kHz, Spread%= +/-1% Fnominal 159.5 0 20 68.5 40 60 80 100 120 Time (us) 140 160 180 Spread Spectrum Profile: Fnom=66MHz, Fmod=30kHz, Spread%= -4% 68 0 200 20 67.5 40 60 80 100 120 Time (us) 140 160 180 200 Spread Spectrum Profile: Fnom=66MHz, Fmod=30kHz, Spread%= +/-1% 67 67.5 67 66.5 66.5 Fnominal 66 Fnominal 66 65.5 65.5 65 64.5 65 64 64.5 63.5 0 20 40 60 80 100 120 Time (us) 140 160 180 200 0 20 40 60 80 100 120 Time (us) 140 160 180 200 Notes 4. The “Informational Graphs” are meant to convey typical performance levels. No performance specifications are implied or guaranteed. Refer to the tables on pages three and four for device specifications. Document Number: 001-07313 Rev. *B Page 6 of 8 CY25701 Ordering Information Part Number Package Description Product Flow Lead-free (Pb-free) CY25701FLXCT CY25701FLXIT 4-Lead Ceramic LCC SMD -Tape and Reel  Commercial, –20° to 70°C 4-Lead Ceramic LCC SMD -Tape and Reel Industrial, –40° to 85°C CY25701LXCZZZT 4-Lead Ceramic LCC SMD -Tape and Reel Commercial, –20° to 70°C CY25701LXIZZZT 4-Lead Ceramic LCC SMD -Tape and Reel Industrial, –40° to 85°C  Actual Marking CY25701FLX* CY25701LX* F=Field Programmable Marketing Part Number (CY25701) C Y 2 X * L Pin 1 mark L = LCC X = Pb free Temp 5 Marketing Part Number (CY25701) L = LCC F C Y 2 5 7 0 Y W W X * z z z Y W W 7 0 1 YWW = Date Code (Year & WW) Pin 1 mark X = Pb free Temp 1 L zzz = Programmable Dash Code YWW = Date Code (Year & WW) Package Drawings and Dimensions Notes 5. “FLX” suffix is used for products programmed in the field by Cypress distributors. 6. “ZZZ” denotes the assigned product dash number. This number is assigned by the factory after the output frequency and spread percent programming data is received from the customer. 7. Temp can be C (Com’l) or I (Industrial). Document Number: 001-07313 Rev. *B Page 7 of 8 CY25701 Document History Page Document Title: CY25701 Programmable High-frequency Crystal Oscillator with Spread Spectrum(SSXO) and No Spread Spectrum(XO) Option Document Number: 001-07313 REV. ECN NO. Issue Date Orig. of Change ** 442944 See ECN RGL Description of Change New data sheet *A 487736 See ECN KKVTMP Added Industrial temp *B 1414203 See ECN DPF/VED Replaced the Package Drawing and Dimension figure on page seven and various copy edits; the reference to the software is now CyberClocksOnlineTM rather than CyberClocks software. © Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. 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Document Number: 001-07313 Rev. *B Revised August 24, 2007 Page 8 of 8 PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders.