MAXIM MAX13326_12

EVALUATION KIT AVAILABLE
MAX13325/MAX13326
Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic
General Description
Features
The MAX13325/MAX13326 dual audio line drivers provide
a reliable differential interface between automotive audio
components. The devices feature differential inputs and
outputs, integrated output diagnostics, and are controlled
using an I2C interface or operate in stand-alone mode.
The outputs can deliver up to 4VRMS into 100I loads.
S Comprehensive Programmability and Diagnostics
Using I2C Interface
The MAX13325 buffers analog audio signals for transmission over long cable distances with a fixed gain of
12dB, whereas the MAX13326 provides a 0dB fixed
gain. The diagnostics on the outputs report conditions
on a per channel basis, including short to GND, short
to battery, overcurrent, overtemperature, and excessive
offset. The output amplifiers can drive capacitive loads
up to 4nF to ground and 3nF differentially.
The outputs are protected according to IEC 61000-4-2
Q8kV Contact Discharge, and Q15kV Air Gap. The
MAX13325/MAX13326 are specified from -40NC to
+105NC and are available in a 28-pin TSSOP package
with an exposed pad.
Applications
Automotive Radio and Rear Seat Entertainment
S Autoretry Function in Stand-Alone Mode
S Drive Capacitive Loads ≤ 3nF Differentially, ≤ 4nF
to Ground
S 112dB Signal-to-Noise Ratio
S Low 0.002% THD at 4VRMS into 2.7kI Loads
S High PSRR (70dB at 1kHz)
S High CMRR (80dB at 1kHz)
S Low Output Noise (3µVRMS), MAX13326
S Excellent Channel-to-Channel Matching
S Load-Dump Transient Protection
S Protected Output Against Various Short-Circuit
Conditions
S ESD Protection for ±8kV Contact Discharge,
±15kV Air Gap
S Long-Distance Drive Capability Typically Up to
15m or Greater
S Noise-Rejecting Differential Inputs and Outputs
S Low-Power Shutdown Mode < 10µA
Professional Remote Audio Amplifiers
S Hardware or Software MUTE Function
S 28-Pin TSSOP Package with Exposed Pad
Typical Operating Circuit
Ordering Information
VSUP
C1
470nF
+5V
VL
C6
100nF
CP
CM
D2**
+12V
* OPTIONAL
C2
1 µF
R1
1kI
Q1
CHOLD
D1
ADD1
CHARGE
PUMP
SDA
FLAG
TO
MICROPROCESSOR
AND
DIGITAL CONTROL
BIAS
MUTE
FROM AUDIO
SOURCE
C3
1µF
PGND
I2C INTERFACE
SHDN
C7
2.2µF
BIAS
C4
10µF
CSS
C5
220nF
OUTLP
INLP
OUTPUT
DIAGNOSTIC
ESD
PROTECTION
-40NC to
+105NC
12
MAX13326GUI/V+ 28 TSSOP-EP*
-40NC to
+105NC
0
1nF
1nF
OUTRP
INRP
RIGHT
C10
2.2µF
MAX13325GUI/V+ 28 TSSOP-EP*
1nF
OUTLM
INLM
C8
2.2µF
FROM AUDIO
SOURCE
GAIN
(dB)
/V denotes an automotive qualified part.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
GND
LEFT
C9
2.2µF
PINPACKAGE
VDD
ADD0
SCL
TEMP RANGE
PART
1nF
1nF
OUTRM
INRM
MAX13325
MAX13326
1nF
*OPTIONAL : NEEDED FOR AUTOMOTIVE LOAD DUMP PROTECTION ONLY
**USE D2 WHEN CHARGE PUMP IS OFF AND EXTERNAL SUPPLY IS PROVIDED TO C HOLD
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-5136; Rev 4; 9/12
MAX13325/MAX13326
Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic
ABSOLUTE MAXIMUM RATINGS
VDD to PGND.........................................................-0.3V to +28V
CHOLD ..................................................................-0.3V to +28V
VL to GND................................................................-0.3V to +6V
GND, PGND .........................................................-0.3V to +0.3V
OUT_ to PGND......................................................... -0.3V to 28V
IN_, BIAS to AGND...................................-0.3V to (VDD + 0.3V)
SCL, SDA, ADD0, ADD1, MUTE, SHDN,
FLAG to GND...........................................................-0.3V to +6V
OUT_ Short Circuit to PGND or VDD..........................Continuous
Short Circuits Between Any OUT_.............................Continuous
Continuous Power Dissipation (TA = +70NC) (multilayer board)
28-Pin TSSOP (derate 27mW/NC above +70NC)......2162.2mW
Operating Temperature Range......................... -40NC to +105NC
Storage Temperature Range............................. -65NC to +150NC
Junction Temperature......................................................+150NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow).......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
Junction-to-Ambient Thermal Resistance (qJA)...........37°C/W
Junction-to-Case Thermal Resistance (qJC)..................2°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(VDD = 14.4V, VL = 5V, RL = J, load impedance from OUT_+ to OUT_-, TA = TJ = -40NC to +105NC, typical values are TA = +25NC,
unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
50
V
AMPLIFIER DC CHARACTERISTICS
Transient Supply Voltage
(Load Dump)
Operating Supply Voltage Range
VDDMAX
Using external nMOS-RTR020N05, 300ms
duration
VDD
4.5
18
VL
2.7
5.5
V
VDD OVLO Threshold
VDDOV
Rising edge
18.5
19.2
V
VDD UVLO Threshold
VDDUV
Falling edge
3.3
3.5
V
VLUV
Falling edge
2.2
2.4
V
VL UVLO Threshold
Supply Current
Logic Supply Current
Shutdown Supply Current
IDD
IL
ISHDN
TA = +25NC, no load
39
TA = -40NC to +105NC, no load
VL = 5V
IDD
1.7
TA = +25NC
0.5
TA = -40NC to +105NC
0.5
IL
Turn-On Time (from Shutdown)
Differential Input Resistance
RIN
Signal-Path Gain (Note 3)
AV
mA
mA
10
2
220
SHDN = VL, CCSS = 220nF
RINDIF
Single-Ended Input Impedance
2 < 0.1
MUTE = VL
Turn-On Time (from Mute)
mA
50
FA
FA
ms
6
ms
Measure across input
18
24
30
Each input to ground (MAX13325)
15
20
25
Each input to ground (MAX13326)
12
16
20
MAX13325
11.8
12
12.2
MAX13326
-0.2
0
+0.2
kI
kI
dB
Maxim Integrated
MAX13325/MAX13326
Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 14.4V, VL = 5V, RL = J, load impedance from OUT_+ to OUT_-, TA = TJ = -40NC to +105NC, typical values are TA = +25NC,
unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Channel-to-Channel Gain
Tracking
Differential Mode Output Balance
OUT_+ to OUT_- (Note 4)
MAX
UNITS
Q0.4
dB
-40
MUTE = GND, TA = +25NC
Q0.5
Q10
MUTE = VL, TA = +25NC
Q0.2
Q3
50
52.5
%
92
115
kI
Output Offset Voltage
(OUT_+ to OUT_-)
VOOS
BIAS Voltage
VBIAS
Relative to VDD
BIAS Impedance
ZBIAS
IBIAS = Q10FA
Output-Voltage Swing Differential
69
VDD = 14.4V, VIN = Q14.4V, RL = 1kI
Q12.5
VDD = 5.0V, VIN = Q5V, RL = 1kI
Q4.2
VDD = 4.5V to 18V
Power-Supply Rejection Ratio
PSRR
Common-Mode Rejection Ratio
CMRR
dB
-80
V
-96
VDD = 14.5V, +500mVP-P ripple at 1kHz
-95
VDD = 14.5V, +500mVP-P ripple at 10kHz
-80
VIN = 1VRMS, 100Hz to 10kHz
-48
mV
dB
-80
dB
AMPLIFIER AC CHARACTERISTICS
Total Harmonic Distortion Plus
Noise (Note 5)
Total Harmonic Distortion Plus
Noise at VDD = 5V (Note 5)
THD+N
THD+N
VOUT = 4VRMS, RL = 2.7kI
0.002
VOUT = 4VRMS, RL = 1kI
0.004
VOUT = 4VRMS, RL = 100I, VDD = 8V
0.03
VOUT = 7VRMS, RL = 1kI
0.2
VOUT = 1VRMS, RL = 2.7kI
0.01
VOUT = 1VRMS, RL = 1kI
0.02
VOUT = 2VRMS, RL = 1kI
0.8
Capacitive-Load Stability
%
3
No sustained
oscillation
Capacitive-Load Drive Capability
Signal-to-Noise Ratio (Note 5)
%
SNR
CLOAD to GND
4
CLOAD differential
3
MAX13325, gain = 12dB, VOUT = 4VRMS,
A-weighted
112
MAX13326, gain = 0dB, VOUT = 4VRMS,
A-weighted
122
Unity-Gain Bandwidth
Output Slew Rate
Output-Voltage Noise
MHz
V/Fs
10
3
VIN = 1VRMS, 1kHz
To achieve soft mute, CCSS = 220nF
Mute Attenuation
3
2.5
A-weighted, MAX13326
Mute Time
nF
dB
A-weighted, MAX13325
Crosstalk
nF
FV
-110
dB
4
ms
VIN = 1VRMS, 1kHz
-75
dB
Click-and-Pop Level (Note 6)
KCP
Into and out of mute
-70
dBV
Click-and-Pop Level (Note 6)
KCP
Into and out of shutdown, 1kI
-45
dBV
Maxim Integrated
3
MAX13325/MAX13326
Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 14.4V, VL = 5V, RL = J, load impedance from OUT_+ to OUT_-, TA = TJ = -40NC to +105NC, typical values are TA = +25NC,
unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
VDD = 4.5V, ISOURCE = 6.6mA
3.2
4.0
VDD = 18V, ISOURCE = 6.6mA
4.5
MAX
UNITS
CHARGE PUMP
Charge-Pump Overdrive Voltage,
VCHOLD – VDD (Hard Mode)
VCPH
VCHOLD - VDD (Soft Mode)
VCPS
VDD unconnected, ISOURCE = 40FA,
VL = 3.3V
2.1
VL = 5V
Charge-Pump Frequency
fCP
CPOFF = 0
5.5
V
V
3.9
CPF[1:0] = 00
333
CPF[1:0] = 01
190
CPF[1:0] = 10
426
CPF[1:0] = 11
260
kHz
DIAGNOSTICS
Output Current Limit
Short to GND or battery
580
mA
230
mA
Q250
mV
Thermal Warning Threshold
135
NC
Thermal Shutdown Threshold
165
NC
Thermal Shutdown Hysteresis
15
NC
Current-Limit Warning Threshold
Open-Load Detection
Output Offset Detection
10
Valid when muted
kI
ESD PROTECTION
Air Gap IEC 61000-4-2
OUT_ pins
Q15
kV
Contact Discharge IEC 61000-4-2
OUT_ pins
Q8
kV
HBM
All pins
Q2
kV
4 Maxim Integrated
MAX13325/MAX13326
Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic
DIGITAL CHARACTERISTICS
(VDD = 14.4V, VL = 3.3V, TA = TJ = -40NC to +105NC, typical values are TA = +25NC, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INTERFACE
Input-Voltage High
VINH
VL = 2.7V to 5.5V
Input-Voltage Low
VINL
VL = 2.7V to 5.5V
0.75 x VL
V
0.25 x VL
Input-Voltage Hysteresis
50
Input Leakage Current
V
mV
Q100
FA
Output Low Voltage
FLAG, SDA, ISINK = 3mA
0.4
Output Leakage Current
FLAG, SDA = 5.5V
V
2
FA
Stand-Alone FLAG Pulse Width
ADD0, ADD1 = GND
100
ms
Stand-Alone Fault Retry Time
ADD0, ADD1 = GND
500
ms
I2C TIMING
Serial-Clock Frequency
fSCL
Bus Free Time
tBUF
Hold Time
400
kHz
1.3
Fs
Repeated START condition
0.6
Fs
SCL Low Time
tLOW
1.3
Fs
SCL High Time
tHIGH
0.6
Data Hold Time
tHD:DAT
0
Data Setup Time
tSU:DAT
100
Bus Capacitance
CB
Per bus line
400
pF
Receiving Rise Time
tR
SCL, SDA
20 + 0.1CB
300
ns
Receiving Fall Time
tF
SCL, SDA
20 + 0.1CB
300
ns
Transmitting Fall Time
tF
SDA, VL = 3.6V
20 + 0.05CB
250
ns
STOP Condition Setup Time
Pulse Width of Suppressed Spike
tHD:STA
0
Between START and STOP conditions
tSU:STO
0.6
tSP
0
Fs
900
ns
ns
Fs
50
ns
Note 2: All devices are 100% tested at TA = +25NC. Limits over temperature are guaranteed by design.


 (VOUT_ + ) − (VOUT_ − ) 
Note 3: Signal path gain is defined as: 20 × log 
.
 (VIN_ + ) − (VIN _ − ) 
Note 3: Signal Path Gain is defined as


Note 4: Measured in differential output mode, differential input voltage 4VP-P (for 0dB gain), 1VP-P (for 12dB gain) 1kHz.

Common-mode output balance is defined as: 20 × log 


.
) × 2

( | VOUT_ + ) − ( VOUT_ − )
 ( VOUT_ + ) + ( VOUT
_−

Common-Mode Output Balance is defined as
Note 5: 22Hz to 22kHz measurement bandwidth.
Note 6: KCP level is calculated as 20log[(peak voltage during mode transition, no input signal)/1VRMS]. Units are expressed in
dBV.
Maxim Integrated
5
MAX13325/MAX13326
Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic
Typical Operating Characteristics
(VDD = 14.4V, VL = 5V, RL = 1kI, gain = 12dB, TA = +25NC, unless otherwise noted.)
0.15
0.10
0.006
-60
0.004
-70
0.003
0.002
-90
0.001
0
-100
5
20 35 50 65 80 95
0
-10
MAX13325 toc04
0.008
0.006
-60
-70
-80
0.002
0
-120
0.004
1
2
3
4
5
6
7
8
9
500mVP-P RIPPLE
-40
-50
-90
-100
-110
100
10
10
MUTE ATTENUATION vs. FREQUENCY
-76
RIGHT CHANNEL
-80
100
1k
FREQUENCY (Hz)
10k
100k
100k
10k
MAX13325 toc03
100k
RIGHT TO LEFT
LEFT TO RIGHT
10
100
1k
10k
100k
FREQUENCY (Hz)
FFT vs. FREQUENCY
MAX13325 toc08
0
VOUT = 1VRMS
1kHz
-15
-30
-45
FFT (dBV)
LEFT CHANNEL
-72
OUTPUT-NOISE VOLTAGE (dBV)
-68
0
-10
-20
-30
-40
-50
-60
-70
-80
90
-100
-110
-120
-130
-140
-150
1k
1VRMS INPUT
20kHz AES17 FILTER
OUTPUT-NOISE VOLTAGE vs. FREQUENCY
MAX13325 toc07
2VRMS INPUT
A-WEIGHTED
10k
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
FREQUENCY (Hz)
OUTPUT VOLTAGE (VRMS)
-60
1k
100
CROSSTALK vs. FREQUENCY
CROSSTALK (dB)
0.010
RIGHT CHANNEL
10
FREQUENCY (Hz)
-20
-30
PSRR (dB)
0.012
10
100k
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
0.014
-64
10k
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. OUTPUT VOLTAGE
0.016
0
1k
FREQUENCY (Hz)
fIN = 1kHz
LEFT CHANNEL
0
100
10
TEMPERATURE (°C)
0.018
MUTE ATTENUATION (dB)
0.005
-80
0.020
THD+N (%)
0.007
-40
0.05
-40 -25 -10
6 0.008
-30
-50
1VRMS OUTPUT
0.009
THDN (%)
0.20
0.010
MAX13325 toc06
-20
CMRR (dB)
0.25
1VRMS INPUT
20kHz AES17 FILTER
-10
MAX13325 toc05
SHUTDOWN CURRENT (µA)
0.30
0
MAX13325 toc02
NO LOAD
INPUTS SHORTED
VSHDN = 0V
MAX13325 toc01
0.40
0.35
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
COMMON-MODE REJECTION RATIO
vs. FREQUENCY
MAX13325 toc09
SHUTDOWN CURRENT
vs. TEMPERATURE
-60
-75
-90
-105
-120
-135
-150
0
2
4
6
8
10 12 14 16 18 20
FREQUENCY (kHz)
10
100
1k
10k
100k
FREQUENCY (Hz)
Maxim Integrated
MAX13325/MAX13326
Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic
Typical Operating Characteristics (continued)
(VDD = 14.4V, VL = 5V, RL = 1kI, gain = 12dB, TA = +25NC, unless otherwise noted.)
OUTPUT VOLTAGE vs. CHARGE-PUMP
OVERDRIVE VOLTAGE
LEFT CHANNEL
-0.005
-0.010
8.5
THDN = 1%
fIN = 1kHz
VDD = 14.4
RL = 1kI
CPOFF = 1
8.0
7.5
-0.015
RIGHT CHANNEL
-0.020
-40 -25 -10
5
7.0
20 35 50 65 80 95
0
TEMPERATURE (°C)
0.15
MAX13326 (0dB)
VOUT = 1VRMS
LEFT CHANNEL
0.05
0
RIGHT CHANNEL
-0.10
-0.15
-0.20
2
4
Maxim Integrated
6 8 10 12 14 16 18 20
FREQUENCY (kHz)
-40 -25 -10 5 20 35 50 65 80
TEMPERATURE (°C)
MAX13325 toc12
1k
10k
100k
GAIN ERROR vs. FREQUENCY
0.10
-0.05
0
100
FREQUENCY (Hz)
GAIN vs. TEMPERATURE
GAIN (dB)
MAX13326 (0dB)
1VRMS OUTPUT
10
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0.20
MAX13325 toc13
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
0.050
0.045
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.005
0
-0.005
-0.010
-0.015
-0.020
-0.025
-0.030
-0.035
-0.040
-0.045
-0.050
(VCHOLD - VDD) (V)
OUTPUT-NOISE VOLTAGE vs. FREQUENCY
OUTPUT NOISE VOLTAGE (dBV)
MAX13325 toc12
9.0
95
GAIN ERROR (dB)
0
9.5
GAIN ERROR (dB)
0.005
GAIN ERROR vs. FREQUENCY
MAX13325 toc14
0.010
10.0
OUTPUT VOLTAGE (V)
0.015
GAIN ERROR (dB)
10.5
MAX13325 toc10
0.020
0.050
0.045
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.005
0
-0.005
-0.010
-0.015
-0.020
-0.025
-0.030
-0.035
-0.040
-0.045
-0.050
MAX13326 (0dB)
1VRMS OUTPUT
10
100
1k
10k
FREQUENCY (Hz)
MAX13325 toc15
GAIN ERROR vs. TEMPERATURE
100k
7
MAX13325/MAX13326
Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic
Pin Configuration
TOP VIEW
+
BIAS
1
VL
2
27 FLAG
I.C.
3
26 CM
I.C.
4
25 CP
INLP
5
INLM
6
VDD
7
22 CHOLD
INRM
8
21 PGND
INRP
28 CSS
24 OUTLP
MAX13325
MAX13326
23 OUTLM
9
20 OUTRP
I.C. 10
19 OUTRM
I.C. 11
18 GND
SHDN 12
17 ADD1
MUTE 13
16 SDA
ADD0 14
EP
15 SCL
TSSOP
CONNECT TO PGND.
Pin Description
PIN
NAME
1
BIAS
2
VL
Logic Supply Voltage. Connect VL to a 2.7V to 5V logic supply. Bypass VL to GND with a 0.1FF
capacitor.
3, 4, 10, 11
I.C.
Internally Connected. Leave unconnected.
5
INLP
Left Audio Positive Input. Either input of each pair can be used as a single-ended input, with the
complementary input bypassed to GND.
6
INLM
Left Audio Negative Input. Either input of each pair can be used as a single-ended input, with the
complementary input bypassed to GND.
7
VDD
Power-Supply Input. Connect VDD to the supply voltage. Bypass VDD to GND through a 1FF
capacitor.
8
INRM
Right Audio Negative Input. Either input of each pair can be used as a single-ended input, with the
complementary input bypassed to GND.
9
INRP
Right Audio Positive Input. Either input of each pair can be used as a single-ended input, with the
complementary input bypassed to GND.
12
SHDN
Shutdown Input. Drive SHDN low to power down the device.
13
MUTE
Mute Input. Drive MUTE low to mute the outputs. The outputs are low impedance in mute.
8 FUNCTION
Analog Bias Voltage. Bypass BIAS to GND with a 10FF capacitor.
Maxim Integrated
MAX13325/MAX13326
Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic
Pin Description (continued)
PIN
NAME
14
ADD0
FUNCTION
I2C
Address Inputs. Connect ADD0 and ADD1 to VL, GND, SCL, or SDA to select 7 I2C addresses.
Connect ADD0 and ADD1 to GND for stand-alone mode.
15
SCL
Serial Clock
16
SDA
Serial-Data IO
17
ADD1
I2C Address Inputs. Connect ADD0 and ADD1 to VL, GND, SCL, or SDA to select 7 I2C addresses.
Connect ADD0 and ADD1 to GND for stand-alone mode.
18
GND
Analog Ground. Ground connection for the input bias and gain circuits.
19
OUTRM
Right Audio Negative Output. Each output is current limited.
20
OUTRP
Right Audio Positive Output . Each output is current limited.
21
PGND
Power Ground. Ground connection for the output stage drivers.
22
CHOLD
Charge-Pump Output (When Charge Pump is On; CPOFF = 0). When the charge pump is off,
provide an external supply through a diode to the CHOLD input. Bypass CHOLD with 1µF to PGND.
23
OUTLM
Left Audio Negative Output. Each output is current limited.
24
OUTLP
Left Audio Positive Outputs. Each output is current limited.
25
CP
Charge-Pump Flying Capacitor, Positive Connection
26
CM
Charge-Pump Flying Capacitor, Negative Connection
27
FLAG
28
CSS
—
EP
Open-Drain Fault Flag Output. FLAG indicates a fault on any one channel. In stand-alone mode,
FLAG is stretched to a typical pulse width of 100ms.
Soft-Start Capacitor Connection. CSS is charged/discharged by < 100FA current to get soft mute/
play transition. Bypass to GND through a 220nF capacitor.
Exposed Pad. Connect to PGND.
Detailed Description
The MAX13325/MAX13326 audio line drivers are designed
to transmit audio data across noisy environments. The differential interface is highly resistant to noise injection from
external sources common to automotive applications.
The MAX13325/MAX13326 operate in stand-alone or
I2C-compatible mode with diagnostic outputs capable
of detecting short to GND or battery, overcurrent, overtemperature, or excessive offset. A short across another
audio output signal line is also protected.
Table 1. Register Address Map
ADDRESS
REGISTER TYPE
NAME
READ/WRITE
DEFAULT
0x00
Configuration
CONFIG
Read/Write
0x00
0x01
Command Byte
CMD
Read/Write
0x00
0x02
General Fault
GFAULT
Read
0x00
0x03
Left-Channel Fault
LFAULT
Cleared on Read
0x00
0x04
Right-Channel Fault
RFAULT
Cleared on Read
0x00
0x05
Flag
FLAG
Read
0x04 (12dB)
0x05 (0dB)
0x06
General Mask
GMASK
Read/Write
0x00
0x07
Left-Channel Mask
LMASK
Read/Write
0x00
0x08
Right-Channel Mask
RMASK
Read/Write
0x00
Maxim Integrated
9
MAX13325/MAX13326
Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic
Configuration Register
Table 2. Configuration Register Format
REGISTER DATA
FUNCTION
ADDRESS
CODE (HEX)
D7
D6
D5
D4
D3
D2
D1
D0
POR STATE
(HEX)
Configuration
Register
0x00
DIAG
ENABLE
MUTE
CPOFF
OLDL
OLDR
CPF1
CPF0
0x00
DIAG: Set DIAG to 1 to enable diagnostic mode. Write '0' to disable diagnostic mode.
ENABLE: Set ENABLE bit to 1 to enable the device. Write ‘0’ disables the device. Low on the SHDN pin overrides the
ENABLE bit.
MUTE: Set the MUTE bit to 1 to mute both the output channels. Output is low impedance when in mute. Low on the
MUTE pin input overrides the MUTE bit.
CPOFF: Set the CPOFF bit to 1 to turn off the charge pump. CHOLD pin must be externally supplied (see the VCPH
parameter in the Electrical Characteristics table). Charge pump is enabled when CPOFF = 0.
OLDL: Write 1 to the OLDL bit to initiate the open-load detection for the left channel. To run OLDL again, write ‘0’ and
‘1’ again.
OLDR: Write 1 to the OLDR bit to initiate the open-load detection for the right channel. To run OLDR again, write ‘0’
and ‘1’ again.
Table 2a. Charge-Pump Frequency Bits
CPF1
CPF0
FREQUENCY (kHz)
0
0
333
0
1
190
1
0
426
1
1
260
CPF[1:0]: Sets the frequency of the charge pump.
Command Byte Register
Table 3. Command Byte Register Format
REGISTER DATA
FUNCTION
ADDRESS
CODE (HEX)
D7
D6
D5
D4
D3
D2
D1
D0
POR STATE
(HEX)
Command Byte
Register
0x01
RETRYR
RETRYL
x
x
x
x
x
x
0x00
RETRYR: The right-channel power amplifier switches off after a fault condition. Write ‘1’ to turn it back on after the fault
condition.
RETRYL: The left-channel power amplifier switches off after a fault condition. Write ‘1’ to turn on the left-channel power
amplifier after the fault condition.
10 Maxim Integrated
MAX13325/MAX13326
Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic
General Faults
Table 4. General Fault Register Format
REGISTER DATA
FUNCTION
ADDRESS
CODE (HEX)
D7
D6
D5
D4
D3
D2
D1
D0
POR STATE
(HEX)
General Fault
Register
0x02
x
TWARN
TSHDN
DUMP
x
x
x
x
0x00
TWARN: The TWARN bit is set to ‘1’ when the temperature warning threshold is reached.
TSHDN: The TSHDN is set to ‘1’ when the temperature shutdown threshold is reached.
DUMP: The DUMP bit is set to ‘1’ when the VDD voltage exceeds the overvoltage threshold.
Set the appropriate mask bit in the GMASK register to detect the general faults. See Table 8.
Left-Channel Faults
Table 5. Left-Channel Fault Register Format
FUNCTION
ADDRESS
CODE
(HEX)
Left-Channel
Fault Register
0x03
REGISTER DATA
D7
D6
D5
D4
D3
D2
D1
D0
POR STATE
(HEX)
SVDDL
SGNDL
LIMITL
x
OFFSETL
OPENL
x
x
0x00
SVDDL: The SVDDL bit is set to ‘1’ when a short to VDD is detected on the left channel.
SGNDL: The SGNDL bit is set to ‘1’ when a short to GND is detected on the left channel.
LIMITL: The LIMITL bit is set to ‘1’ when the current-limit threshold is tripped for left output.
OFFSETL: The OFFSETL bit is set to ‘1’ when excessive offset is detected on the left-channel output.
OPENL: The OPENL bit is set to ‘1’ when an open load is detected on the left channel.
Set the appropriate mask bit in the LMASK register to detect the faults on the left channel. See Table 9.
When any bit of the LFAULT register is high, the FLAG output is low.
Right-Channel Faults
Table 6. Right-Channel Fault Register Format
FUNCTION
ADDRESS
CODE
(HEX)
Right-Channel
Fault Register
0x04
REGISTER DATA
D7
D6
D5
D4
D3
D2
D1
D0
POR STATE
(HEX)
SVDDR
SGNDR
LIMITR
x
OFFSETR
OPENR
x
x
0x00
SVDDR: The SVDDR bit is set to ‘1’ when a short to VDD is detected on the right channel.
SGNDR: The SGNDR bit is set to ‘1’ when a short to GND is detected on the right channel.
LIMITR: The LIMITR bit is set to ‘1’ when the current-limit threshold is tripped for right output.
OFFSETR: The OFFSETR bit is set to ‘1’ when excessive offset is detected on the right-channel output.
OPENR: The OPENR bit is set to ‘1’ when an open load is detected on the right channel.
Set the appropriate mask bit in the RMASK register to detect the faults on the right channel. See Table 10.
When any bit of the RFAULT register is high, the FLAG output is pulled low.
Maxim Integrated
11
MAX13325/MAX13326
Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic
FLAG Register
Table 7. Flag Register Format
FUNCTION
ADDRESS
CODE
(HEX)
FLAG
Register
0x05
REGISTER DATA
D7
D6
D5
D4
D3
D2
D1
D0
POR STATE
(HEX)
FLAG
LHIGHZ
RHIGHZ
OFFSETL
OFFSETR
ID2
ID1
ID0
0x04/0x05
FLAG: FLAG bit is set to ‘1’ when the FLAG output is logic-low. The FLAG bit allows to quickly access the status of the
device without using the FLAG output and without having to read all the fault registers.
LHIGHZ: The LHIGHZ bit is set to ‘1’ when the left-channel output is high impedance; for example due to a short circuit.
RHIGHZ: The RHIGHZ bit is set to ‘1’ when the right-channel output is high impedance; for example due to a short
circuit.
OFFSETL: The OFFSETL bit is set to ‘1’ when excessive offset is detected on the left-channel output.
OFFSETR: The OFFSETR bit is set to ‘1’ when excessive offset is detected on the right-channel output.
ID[2:0]: The ID[2:0] bits indicate the device type (12dB = 100 and 0dB = 101).
General Mask Register
Table 8. General Mask Register Format
FUNCTION
ADDRESS
CODE
(HEX)
General Mask
Register
0x06
REGISTER DATA
D7
D6
D5
D4
D3
D2
D1
D0
POR STATE
(HEX)
0
MTWARN
MTSHDN
MDUMP
x
x
x
x
0x00
MTWARN: Set MTWARN to ‘1’ to enable the TWARN fault detection. See Table 4.
MTSHDN: Set MTSHDN to ‘1’ to enable the TSHDN fault detection. See Table 4.
MDUMP: Set MDUMP to ‘1’ to enable the DUMP fault detection. See Table 4.
Left-Channel Mask Register
Table 9. Left-Channel Mask Register
FUNCTION
ADDRESS
CODE
(HEX)
Left-Channel
Mask Register
0x07
REGISTER DATA
D7
D6
D5
D4
D3
D2
D1
D0
MSVDDL
MSGNDL
MLIMITL
0
MOFFSETL
MOPENL
x
x
POR
STATE
(HEX)
0x00
MSVDDL: Set MSVDDL to 1 to enable the short to VDD detection on the left channel.
MSGNDL: Set MSGNDL to 1 to enable the short to GND detection on the left channel.
MLIMITL: Set MLIMITL to 1 to enable overcurrent detection on the left channel.
MOFFSETL: Set MOFFSETL to 1 to enable excessive-offset detection on the left-channel output.
MOPENL: Set MOPENL to 1 to enable open-load detection on the left channel.
12 Maxim Integrated
MAX13325/MAX13326
Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic
Right-Channel Mask Register
Table 10. Right-Channel Mask Register
FUNCTION
ADDRESS
CODE
(HEX)
Right-Channel
Mask Register
0x08
REGISTER DATA
D7
D6
D5
D4
D3
D2
D1
D0
MSVDDR
MSGNDR
MLIMITR
0
MOFFSETR
MOPENR
x
x
POR
STATE
(HEX)
0x00
MSVDDR: Set MSVDDR to 1 to enable the short to VDD detection on the right channel.
MSGNDR: Set MSGNDR to 1 to enable the short to GND detection on the right channel.
MLIMITR: Set MLIMITR to 1 to enable overcurrent detection on the right channel.
MOFFSETR: Set MOFFSETR to 1 to enable excessive-offset detection on the right channel.
MOPENR: Set MOPENR to 1 to enable open-load detection on the right channel.
I2C and Stand-Alone Diagnostics
When the DIAG bit and the appropriate mask bits are set
to 1, the MAX13325/MAX13326 enter diagnostic mode.
In this mode, the MAX13325/MAX13326 detect short
to GND, short to battery, overcurrent condition, overtemperature condition, excessive offset, and report the
diagnosis using the I2C serial interface, FLAG bit, and
the FLAG output.
For stand-alone mode, there exists a 500ms stand-alone
fault retry function (for autoretry) until the fault goes
away. The FLAG output is pulsed to indicate a fault.
Output Short to VDD
When in diagnostic mode, the MAX13325/MAX13326
detect if any of the differential outputs is shorted to VDD
or battery. Upon detection of the short to VDD or battery,
the faulted channel is switched off and its output goes
into a high-impedance state. The fault is reported using
the I2C interface and the FLAG output. See Table 11.
Table 11. Output Short to VDD­/Battery Diagnostic
FAULT CONDITION
STATUS REPORT
FLAG is asserted low.
FLAG bit set. See Table 7.
Left-Channel Output
Short to VDD
SVDDL bit is set in the LFAULT
register. See Table 5.
Left channel switches off and output
goes to high-impedance state.
FLAG is asserted low.
FLAG bit set. See Table 7.
Right-Channel
Output Short to VDD
Maxim Integrated
SVDDR bit is set in the RFAULT
register. See Table 6.
Right channel switches off and
output goes to high-impedance
state.
UNMASK
RECOVERY
In LMASK register, set
MSVDDL bit to 1.
See Table 9.
Cleared on reading the LFAULT
register. See Table 5.
Note: 500ms autoretry in standalone mode.
Cannot be masked.
Output is enabled by setting the
RETRYL bit to 1 in the Common
Byte register. See Table 3.
In RMASK register, set
MSVDDR bit to 1. See
Table 10.
Cleared on reading the RFAULT
register. See Table 6.
Note: 500ms autoretry in standalone mode.
Cannot be masked.
Output is enabled by setting the
RETRYR bit to 1 in the Command
Byte register. See Table 3.
13
MAX13325/MAX13326
Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic
Output Short to GND
When in diagnostic mode, the MAX13325/MAX13326
detect if any of the differential outputs is shorted to
ground. Upon detection of the short to ground, the
faulted channel is switched off and its output goes into a
high-impedance state. The fault is reported using the I2C
interface and the FLAG output. See Table 12.
Overtemperature
When in diagnostic mode, if the MAX13325/MAX13326
exceed the overtemperature warning or temperature shutdown thresholds the device reports the condition using
the I2C interface and the FLAG output. See Table 13.
Table 12. Output Short to GND Diagnostic
FAULT CONDITION
STATUS REPORT
FLAG is asserted low.
FLAG bit set. See Table 7.
Left-Channel Output
Short to GND
SGNDL bit is set in the LFAULT
register. See Table 5.
Left channel switches off and output
goes to high-impedance state.
FLAG is asserted low.
FLAG bit set. See Table 7.
Right-Channel Output
Short to GND
SGNDR bit is set in the RFAULT
register. See Table 6.
Right channel switches off and
output goes to high-impedance
state.
UNMASK
RECOVERY
In LMASK register, set
MSGNDL bit to 1. See
Table 9.
Cleared on reading the LFAULT
register. See Table 5.
Note: 500ms autoretry in standalone mode.
Cannot be masked.
Output is enabled by setting the
RETRYL bit to 1 in the Command
Byte register. See Table 3.
In RMASK register, set
MSGNDR bit to 1. See
Table 10.
Cleared on reading the RFAULT
register. See Table 6.
Note: 500ms autoretry in standalone mode.
Cannot be masked.
Output is enabled by setting the
RETRYR bit to 1 in the Command
Byte register. See Table 3.
Table 13. Overtemperature Diagnostic
FAULT CONDITION
Overtemperature
Warning
STATUS REPORT
FLAG is asserted low.
FLAG bit set. See Table 7.
TWARN bit is set in the GFAULT
register. See Table 4.
UNMASK
RECOVERY
In GMASK register, set
MTWARN bit to 1. See
Table 8.
Die temperature falls below warning
threshold.
Cleared on reading the GFAULT
register.
In GMASK register, set
MTSHDN bit to 1. See
Table 8.
Die temperature falls below
shutdown threshold.
Cleared on reading the GFAULT
register.
Note: 500ms autoretry in standalone mode.
Cannot be masked.
Left channel is enabled by setting
the RETRYL bit to 1 in the Command
Byte register.
Right channel is enabled by
setting the RETRYR bit to 1 in the
Command Byte register.
See Table 3.
FLAG is asserted low.
FLAG bit set. See Table 7.
TSHDN bit is set in the GFAULT
Register. See Table 4.
Overtemperature
Shutdown
Left and right channels switch
off and output goes to highimpedance state.
14 Maxim Integrated
MAX13325/MAX13326
Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic
Excessive Offset
When in diagnostic mode with mute enabled, if there
is excessive offset on any output, the MAX13325/
MAX13326 reports the condition through the I2C interface and the FLAG output. See Table 14.
Overcurrent
When in diagnostic mode, if any of the output pairs is
excessively loaded, the MAX13325/MAX13326 issue a
warning and report the condition through the I2C interface and the FLAG output. The faulted channel is not
switched off. See Table 15.
Open Load
When in diagnostic mode and the open-load detection is initiated, the selected channel is switched off for
1ms during which the diagnosis is taking place. Upon
detecting an open load on any channel, the MAX13325/
MAX13326 report the condition using the I2C interface
and the FLAG output. See Table 16.
Overvoltage
When in diagnostic mode, if the MAX13325/MAX13326
exceed the VDD overvoltage threshold (for example
during a load-dump condition), the device reports the
condition using the I2C interface and the FLAG output.
See Table 17.
Table 14. Excessive Offset Diagnostic
FAULT CONDITION
Excessive Output
Offset on Left
Channel
Excessive Output
Offset on Right
Channel
STATUS REPORT
FLAG is asserted low.
FLAG bit set. See Table 7.
OFFSETL bit is set in the LFAULT
register. See Table 5.
FLAG is asserted low.
FLAG bit set.
OFFSETR bit is set in the RFAULT
register. See Table 6.
UNMASK
RECOVERY
In the LMASK register, set
MOFFSETL bit to 1. See
Table 9.
Cleared on reading the LFAULT
register.
In the RMASK register, set
MOFFSETR bit to 1. See
Table 10.
Cleared on reading the RFAULT
register.
UNMASK
RECOVERY
In the LMASK register,
set MLIMITL bit to 1. See
Table 9.
Load current falls below the
current-limit threshold.
Cleared on reading the LFAULT
register.
In the RMASK register,
set MLIMITR bit to 1. See
Table 10.
Load current falls below the
current-limit threshold.
Cleared on reading the RFAULT
register.
UNMASK
RECOVERY
In the LMASK register,
set MOPENL bit to 1. See
Table 9.
Cleared on reading
the LFAULT register.
In the RMASK register,
set MOPENR bit to 1. See
Table 10.
Cleared on reading
the RFAULT register.
Table 15. Overcurrent Diagnostic
FAULT CONDITION
Overcurrent on Left
Channel
Overcurrent on Right
Channel
STATUS REPORT
FLAG is asserted low.
FLAG bit set. See Table 7.
LIMITL bit is set in the LFAULT
register. See Table 5.
FLAG is asserted low.
FLAG bit set. See Table 7.
LIMITR bit is set in the RFAULT
register. See Table 6.
Table 16. Open-Load Diagnostic
FAULT CONDITION
Left-Channel Open
Load
Right-Channel Open
Load
Maxim Integrated
STATUS REPORT
FLAG is asserted low.
FLAG bit set. See Table 7.
OPENL bit is set in the LFAULT
register. See Table 5.
FLAG is asserted low.
FLAG bit set. See Table 7.
OPENR bit is set in the RFAULT
register. See Table 6.
15
MAX13325/MAX13326
Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic
Table 17. Overvoltage Diagnostic
FAULT CONDITION
STATUS REPORT
FLAG is asserted low.
FLAG bit set. See Table 7.
DUMP bit is set in the GFAULT
register. See Table 4.
Overvoltage
Shutdown
Left and right channels switch
off and output goes to a
high-impedance state.
Applications Information
Serial Interface
Writing to the MAX13325/MAX13326 using I2C requires
that first the master sends a START (S) condition followed by the device’s I2C address. After the address,
the master sends the register address of the register
that is to be programmed. The master then ends communication by issuing a STOP (P) condition to relinquish
UNMASK
RECOVERY
In GMASK register, set
MDUMP bit to 1.
See Table 8.
VDD voltage falls below overvoltage
threshold. Cleared on reading the
GFAULT register. Note: 500ms
autoretry in stand-alone mode.
Cannot be masked.
Left channel is enabled by setting
the RETRYL bit to 1. Right channel
is enabled by setting the RETRYR
bit to 1. See Table 3.
control of the bus, or a Repeated START (Sr) condition to
communicate to another I2C slave (see Figure 1).
Bit Transfer
Each SCL rising edge transfers one data bit. The data
on SDA must remain stable during the high portion of the
SCL clock pulse (see Figure 2). Changes in SDA while
SCL is high are read as control signals (see the START
and STOP Conditions section). When the serial interface
is inactive, SDA and SCL idle high.
SDA
tF
tLOW
tLOW
tSU:DAT
tHD:STA
tF
tSP
tR
tBUF
SCL
tHD:STA
S
tHD:DAT
tHIGH
tSU:STA
tSU:STO
Sr
P
S
Figure 1. I2C Timing
SDA
SCL
DATA LINE
STABLE;
DATA VALID
CHANGE OF
DATA ALLOWED
Figure 2. Bit Transfer
16 Maxim Integrated
MAX13325/MAX13326
Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic
serial interface until the next START or Repeated START
condition, minimizing digital noise and feedthrough.
START and STOP Conditions
A master device initiates communication by issuing
a START condition, which is a high-to-low transition
on SDA with SCL high. A START condition from the
master signals the beginning of a transmission to the
MAX13325/MAX13326. The master terminates transmission by a STOP condition (see the Acknowledge Bit
section). A STOP condition is a low-to-high transition
on SDA while SCL is high (Figure 3). The STOP condition frees the bus. If a Repeated START condition is
generated instead of a STOP condition, the bus remains
active. When a STOP condition or incorrect slave ID is
detected, the device internally disconnects SCL from the
Acknowledge Bit
The acknowledge (ACK) bit is a clocked 9th bit that
the MAX13325/MAX13326 use to handshake receipt of
each byte of data when in write mode. The MAX13325/
MAX13326 pull down SDA during the entire mastergenerated 9th clock pulse if the previous byte is successfully received (see Figure 4). Monitoring ACK
allows for detection of unsuccessful data transfers. An
unsuccessful data transfer occurs if a receiving device
is busy or if a system fault has occurred. In the event
START
CONDITION
STOP
CONDITION
SDA
SCL
Figure 3. START/STOP Conditions
NOT ACKNOWLEDGE
S
SDA
ACKNOWLEDGE
1
SCL
8
9
Figure 4. Acknowledge and Not-Acknowledge Bits
Table 18. Slave Address
ADD1
ADD0
A6
A5
A4
A3
A2
A1
A0
R/W
SLAVE
ADDRESS
READ
(HEX)
SLAVE
ADDRESS
WRITE
(HEX)
MODE
GND
GND
—
—
—
—
—
—
—
—
—
—
Standalone
VL
GND
1
1
0
0
0
0
1
1/0
0xC3
0xC2
I2C
GND
VL
1
1
0
0
0
1
0
1/0
0xC5
0xC4
I2C
VL
VL
1
1
0
0
0
1
1
1/0
0xC7
0xC6
I2C
SCL
VL
1
1
0
0
1
0
0
1/0
0xC9
0xC8
I2C
SDA
VL
1
1
0
0
1
0
1
1/0
0xCB
0xCA
I2C
VL
SCL
1
1
0
0
1
1
0
1/0
0xCD
0xCC
I2C
VL
SDA
1
1
0
0
1
1
1
1/0
0xCF
0xCE
I2C
Maxim Integrated
17
MAX13325/MAX13326
Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic
Register Address Map
of an unsuccessful data transfer, the bus master may
retry communication. The master must pull down SDA
during the 9th clock cycle to acknowledge receipt of
data when the MAX13325/MAX13326 are in read mode.
An acknowledge must be sent by the master after each
read byte to allow data transfer to continue. A notacknowledge is sent when the master reads the final
byte of data from the MAX13325/MAX13326, followed by
a STOP condition.
Single-Byte Write Operation
For a single-byte write operation, send the slave address
as the first byte followed by the register address and
then a single data byte (see Figure 5).
Burst Write Operation
For a burst write operation, send the slave address as
the first byte followed by the register address and then
the data bytes (see Figure 6).
Slave Address
The MAX13325/MAX13326 are programmable to one of
seven I2C slave addresses. These slave addresses are
unique device IDs. Connect ADD_ to GND, VL, SCL, or
SDA to set the I2C slave address. The address is defined
as the seven most significant bits (MSBs) followed by
the read/write bit. Set the read/write bit to 1 to configure
the MAX13325/MAX13326 to read mode. Set the read/
write bit to 0 to configure the device to write mode. The
address is the first byte of information sent after the
START condition.
S
S7
S6
S5
S4
S3
S2
R/W
=0
S1
Single-Byte Read Operation
For a single-byte read operation, send the slave address
with the read bit set, as the first byte followed by the register address. Then send a Repeated START condition
followed by the slave address. After the slave sends the
data byte, send a not-acknowledge followed by a STOP
condition (see Figure 7).
Burst Read Operation
For a burst read operation, send the slave address with
a write as the first byte followed by the register address.
Then send a Repeated START condition followed by the
slave address. The slave sends data bytes until a notacknowledge condition is sent (see Figure 8).
ACK
C7
C6
C5
SLAVE ADDRESS
B7
B6
B5
B4
B3
C4
C3
C2
C1
C0
ACK
REGISTER ADDRESS
B2
B1
B0
ACK
P
DATA 1
Figure 5. A Single-Byte Write Operation
S
S7
S6
S5
S4
S3
S2
S1
R/W
=0
ACK
R7
R6
SLAVE ADDRESS
B7
B6
B5
B4
B3
R5
R4
R3
R2
R1
R0
ACK
B2
B1
B0
ACK
B2
B1
B0
ACK
REGISTER ADDRESS
B2
B1
B0
ACK
B7
B6
B5
DATA 1
B4
B3
DATA 2
ACK
B7
B6
B5
B4
B3
P
DATA N
Figure 6. A Burst Write Operation
18 Maxim Integrated
MAX13325/MAX13326
Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic
S
S7
S6
S5
S4
S3
S2
R/W
=0
S1
ACK
B7
B6
B5
SLAVE ADDRESS
Sr
S7
S6
S5
S4
B4
B3
B2
B1
B0
ACK
B1
B0
NACK
REGISTER ADDRESS
S3
S2
R/W
=1
S1
ACK
B7
B6
B5
B4
SLAVE ADDRESS
B3
B2
P
DATA
Figure 7. A Single-Byte Read Operation
S
S7
S6
S5
S4
S3
S2
S1
R/W
=0
ACK
B7
B6
B5
SLAVE ADDRESS
Sr
S7
S6
S5
S4
S3
B4
B3
B2
B1
B0
ACK
B2
B1
B0
ACK
B1
B0
NACK
P
REGISTER ADDRESS
S2
S1
R/W
=1
ACK
B7
B6
B5
B4
SLAVE ADDRESS
B3
DATA 1
ACK
B7
B6
B5
B4
B3
B2
DATA N
Figure 8. A Burst Read Operation
Charge Pump
The MAX13325/MAX13326 charge pump can be disabled depending on application requirements. When
charge pump is enabled [CPOFF = 0], please follow the
charge-pump capacitor selections. When the charge
pump is disabled [CPOFF = 1], the flying capacitor
(C1) is not needed. There are internal diodes between
VDD/OUT_ to CHOLD, so it is important that CHOLD
not be forced below VDD or any of the outputs. A series
diode needs to be placed between the external supply
(VSUP) and CHOLD. See D2 in the Typical Operating
Circuit.
Charge-Pump Capacitor Selection
Use ceramic capacitors with a low ESR for optimum performance. For optimal performance over the extended
temperature range, select capacitors with an X7R
dielectric. Table 19 lists suggested manufacturers.
Flying Capacitor (C1)
The value of the flying capacitor (see the Typical
Operating Circuit) affects the charge pump’s load regulation and output resistance. A C1 value that is too small
degrades the device’s ability to provide sufficient current
drive, which leads to a loss of output voltage. Increasing
the value of C1 improves load regulation and reduces
the charge-pump output resistance. For optimum performance, use a 470nF capacitor for C1. When the charge
pump is disabled [CPOFF = 1], the flying capacitor (C1)
is not needed.
Hold Capacitor (C2)
The hold capacitor value (see the Typical Operating
Circuit) and ESR directly affect the ripple at the internal
negative rail. Increasing the value of C2 reduces output
ripple. Likewise, decreasing the ESR of C2 reduces both
ripple and output resistance. Lower capacitance values
can be used in systems with low maximum output power
levels. For optimum performance, use a 1FF capacitor
for C2.
Table 19. Suggested Capacitor Vendors
PHONE
FAX
Murata Electronics North America, Inc.
SUPPLIER
770-436-1300
770-436-3030
www.murata-northamerica.com
Taiyo Yuden
800-348-2496
847-925-0899
www.t-yuden.com
TDK Corp.
847-803-6100
847-390-4405
www.component.tdk.com
Maxim Integrated
WEBSITE
19
MAX13325/MAX13326
Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic
Power-Supply Bypass Capacitor (C3)
The power-supply bypass capacitor (see the Typical
Operating Circuit) lowers the output impedance of the
power supply, and reduces the impact of the MAX13325/
MAX13326 charge-pump switching transients. Bypass
VDD with C3, the same value as C2, and place it physically close to the VDD and PGND pins.
Load-Dump Protection
With minimal external components, the MAX13325/
MAX13326 can be protected against automotive loaddump conditions. See the Typical Operating Circuit.
nMOSFET (Q1)
Q1 should be selected to withstand the full-voltage exposure (BVDSS > 45V). The gate-source turn-on voltage
should be chosen to be less than VCPS to ensure initial
startup. Using an external nMOS, RTR020N05, 300ms
duration component provides 50V load-dump protection.
Zener Diode (D1)
During short-to-battery condition, OUT_ lifts up CHOLD
using an internal diode. In order not to violate the maximum gate-source voltage of Q1, a zener diode of appropriate clamping voltage should be added between the
gate and source terminals.
Series Resistor (R1)
Normally, a series resistor for current limitation is needed
during short-to-battery condition. R1 should be chosen
according to (18V - VDD(min) - VZENER)/1mA so that no
excessive current is being drawn from CHOLD.
Layout and Grounding
Proper layout and grounding are essential for optimum
performance. Connect the EP and GND together at a
single point on the PCB. Ensure ground return resistance
is minimized for optimum crosstalk performance.
Chip Information
PROCESS: BCD
20 Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates RoHS
status only. Package drawings may show a different suffix
character, but the drawing pertains to the package regardless
of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND PATTERN
NO.
28 TSSOP-EP
U28E+5
21-0108
90-0147
Maxim Integrated
MAX13325/MAX13326
Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic
Revision History
REVISION
NUMBER
REVISION
DATE
0
1/10
Initial release
—
1
3/10
Updated the Typical Operating Circuit
1
2
4/10
3
6/10
4
9/12
DESCRIPTION
Added new register bits to Tables 1, 2, and 7. Revised FLAG Register
section and added Table 2a and Charge Pump section.
Introduced the MAX13326. Updated the Electrical Characteristics table
and added new Typical Operating Characteristics graphs.
Corrected slave addresses in Table 18
PAGES
CHANGED
1, 4, 7, 8–12, 19, 20
1, 4, 5, 7
17
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2012
Maxim Integrated
21
The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.