CY7C09169AVTITLE CY7C09159AV 3.3-V 8 K × 9 Synchronous Dual Port Static RAM Features ■ True dual-ported memory cells which allow simultaneous access of the same memory location ■ Flow-through/Pipelined device ❐ 8 K × 9 organization (CY7C09159AV) ■ Three Modes ❐ Flow-through ❐ Pipelined ❐ Burst ■ 3.3 V Low operating power ❐ Active = 135 mA (typical) ❐ Standby = 10 μA (typical) ■ Fully synchronous interface for easier operation ■ Burst counters increment addresses internally ❐ Shorten cycle times ❐ Minimize bus noise ❐ Supported in Flow-through and Pipelined modes ■ Dual chip enables for easy depth expansion ■ Pipelined output mode on both ports allows fast 67-MHz operation ■ Automatic power-down ■ Commercial temperature ranges ■ 0.35-micron complementary metal oxide semiconductor (CMOS) for optimum speed/power ■ Available in 100-pin thin quad plastic flatpack (TQFP) ■ High-speed clock to data access 9 ns (max.) ■ Pb-free packages available Logic Block Diagram R/WL R/WR OEL OER CE0L CE1L 1 0 0 0/1 1 0/1 FT/PipeL 0/1 0 0 0/1 FT/PipeR 9 I/O Control A0−A12L CLKL ADSL CNTENL CNTRSTL 1 9 I/O0L−I/O8L CE0R CE1R 1 I/O0R−I/O8R I/O Control 13 13 Counter/ Address Register Decode Cypress Semiconductor Corporation Document Number: 38-06053 Rev. *E Counter/ Address Register Decode True Dual-Ported RAM Array • 198 Champion Court • A0−A12R CLKR ADSR CNTENR CNTRSTR San Jose, CA 95134-1709 • 408-943-2600 Revised November 8, 2011 CY7C09159AV Functional Description The CY7C09159AV is a high-speed synchronous CMOS 8 K × 9 dual-port static RAM. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.[1] Registers on control, address, and data lines allow for minimal setup and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 9 ns (pipelined). Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode data will be available tCD1 = 20 ns after the address is clocked into the device. Pipelined output or flow-through mode is selected via the FT/Pipe pin. Each port contains a burst counter on the input address register. The internal write pulse width is independent of the LOW- to-HIGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times. A HIGH on CE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables allows easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE0 LOW and CE1 HIGH to reactivate the outputs. Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port’s burst counter is loaded with the port’s Address Strobe (ADS). When the port’s Count Enable (CNTEN) is asserted, the address counter will increment on each LOW-to-HIGH transition of that port’s clock signal. This will read/write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop back to the start. Counter Reset (CNTRST) is used to reset the burst counter. All parts are available in 100-pin thin quad plastic flatpack (TQFP) packages. Note 1. When simultaneously writing to the same location, final value cannot be guaranteed. Document Number: 38-06053 Rev. *E Page 2 of 19 CY7C09159AV Contents Pin Configuration ............................................................. 4 100-Pin TQFP (Top View) ................................................. 4 Selection Guide ................................................................ 4 Pin Definitions .................................................................. 5 Maximum Ratings ............................................................. 5 Operating Range ............................................................... 5 Electrical Characteristics Over the Operating Range ............................................... 6 Capacitance ...................................................................... 6 AC Test Loads .................................................................. 6 Switching Characteristics Over the Operating Range ............................................... 7 Document Number: 38-06053 Rev. *E Switching Waveforms ...................................................... 8 Ordering Information ...................................................... 16 Ordering Code Definitions ......................................... 16 Package Diagram ............................................................ 17 Acronyms ........................................................................ 17 Document Conventions ................................................. 17 Units of Measure ....................................................... 17 Document History Page ................................................. 18 Sales, Solutions, and Legal Information ...................... 19 Worldwide Sales and Design Support ....................... 19 Products .................................................................... 19 PSoC Solutions ......................................................... 19 Page 3 of 19 CY7C09159AV Pin Configuration NC A6R A5R A4R A3R A2R A1R A0R CNTENR CLKR ADSR GND GND ADSL CLKL CNTENL A0L A1L A2L A3L A4L A5L A6L NC NC 100-Pin TQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC 1 75 NC NC 2 74 NC A7L 3 73 A7R A8L 4 72 A8R A9L 5 71 A9R A10L 6 70 A10R A11L 7 69 A11R A12L 8 68 A12R NC 9 67 NC NC 10 66 NC NC 11 65 NC NC 12 64 NC VCC 13 63 GND NC 14 62 NC NC 15 61 NC NC 16 60 NC NC 17 59 NC CE0L 18 58 CE0R CE1L 19 57 CE1R CNTRSTL 20 56 CNTRSTR R/WL 21 55 R/WR CY7C09159AV (8 K × 9) OEL 22 54 OER FT/PIPEL 23 53 FT/PIPER NC 24 52 GND NC 25 51 NC NC NC I/O8R I/O7R I/O6R I/O5R I/O4R I/O3R VCC I/O2R I/01R I/O0R GND VCC I/O0L I/O1L GND I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L GND I/O8L 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Selection Guide fMAX2 (Pipelined) Max access time (clock to data, pipelined) CY7C09159AV –9 Unit 67 MHz 9 ns 135 mA Typical standby current for ISB1 (Both ports TTL level) 20 mA Typical standby current for ISB3 (Both ports CMOS level) 10 μA Typical operating current ICC Document Number: 38-06053 Rev. *E Page 4 of 19 CY7C09159AV Pin Definitions Left Port Right Port Description A0L–A12L A0R–A12R Address inputs (A0−A12 for 8 K devices). ADSL ADSR Address strobe input. Used as an address qualifier. This signal should be asserted LOW during normal read or write transactions. Asserting this signal LOW also loads the burst address counter with data present on the I/O pins. CE0L,CE1L CE0R,CE1R Chip enable input. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH). CLKL CLKR Clock signal. This input can be free-running or strobed. Maximum clock input rate is fMAX. CNTENL CNTENR Counter enable input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW. CNTRSTL CNTRSTR Counter reset input. Asserting this signal LOW resets the burst address counter of its respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN. I/O0L–I/O8L I/O0R–I/O8R Data bus input/output (I/O0–I/O8 for x9 devices). OEL OER Output enable input. This signal must be asserted LOW to enable the I/O data pins during read operations. R/WL R/WR Read/Write enable input. This signal is asserted LOW to write to the dual-port memory array. For read operations, assert this pin HIGH. FT/PIPEL FT/PIPER Flow-through/Pipelined select input. For flow-through mode operation, assert this pin LOW. For pipelined mode operation, assert this pin HIGH. GND Ground Input. NC No connect. VCC Power input. Maximum Ratings[2] Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Operating Range Storage temperature................................ –65 °C to +150 °C Range Ambient Temperature VCC Ambient temperature with power applied . –55 °C to +125 °C Commercial 0 °C to +70 °C 3.3 V ± 300 mV Supply voltage to ground potential ...............–0.5 V to +4.6 V DC voltage applied to outputs in High Z state........................... –0.5 V to VCC+0.5 V DC input voltage .................................... –0.5 V to VCC+0.5 V Output current into outputs (LOW) .............................. 20 mA Static discharge voltage............................................ >2001 V Latch-up current ...................................................... >200 mA Note 2. The voltage on any input or I/O pin can not exceed the power pin during power-up Document Number: 38-06053 Rev. *E Page 5 of 19 CY7C09159AV Electrical Characteristics Over the Operating Range CY7C09159AV Parameter Description –9 Min Typ Unit Max VOH Output HIGH voltage (VCC = Min., IOH = –4.0 mA) 2.4 – – V VOL Output LOW voltage (VCC = Min., IOH = +4.0 mA) – – 0.4 V VIH Input HIGH voltage 2.0 – – V VIL Input LOW voltage – – 0.8 V IOZ Output leakage current ICC Operating current (VCC = Max., IOUT = 0 mA) outputs disabled Commercial Standby current (Both ports TTL level) CEL & CER ≥ VIH, f = fMAX Commercial Standby current (One port TTL level) CEL | CER ≥ VIH, f = fMAX Commercial Standby current (Both ports CMOS level) CEL and CER ≥ VCC – 0.2 V, f = 0 Commercial ISB1 [3] ISB2[3] ISB3 [3] ISB4[3] –10 – 10 μA – 135 230 mA Industrial – mA – 20 75 mA – 95 155 mA Industrial mA Industrial – – 10 – 85 Industrial Standby current (One port CMOS level) CEL | CER ≥ VIH, f = fMAX mA 500 μA 115 mA μA – Commercial Industrial mA Capacitance Parameter Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = 3.3 V Max Unit 10 pF 10 pF AC Test Loads 3.3 V 3.3 V R1 = 590 Ω OUTPUT C = 30 pF R2 = 435 Ω OUTPUT RTH = 250 Ω R1 = OUTPUT C = 30 pF C = 5 pF VTH = 1.4 V (a) Normal Load (Load 1) (b) Thévenin Equivalent (Load 1) R2 = 435 Ω (c) Three-state Delay (Load 2) (Used for tCKLZ, tOLZ, & tOHZ including scope and jig) Note 3. CEL and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH). Document Number: 38-06053 Rev. *E Page 6 of 19 CY7C09159AV Switching Characteristics Over the Operating Range CY7C09159AV Parameter Description Unit –9 Min Max – 40 MHz fMAX1 fMax flow-through fMAX2 fMax pipelined – 67 MHz tCYC1 Clock cycle time – flow-through 25 – ns tCYC2 Clock cycle time – pipelined 15 – ns tCH1 Clock HIGH time – flow-through 12 – ns tCL1 Clock LOW time – flow-through 12 – ns tCH2 Clock HIGH time – pipelined 6 – ns tCL2 Clock LOW time – pipelined 6 – ns tR Clock rise time – 3 ns tF Clock fall time – 3 ns tSA Address setup time 4 – ns tHA Address hold time 1 – ns tSC Chip enable setup time 4 – ns tHC Chip enable hold time 1 – ns tSW R/W setup time 4 – ns tHW R/W hold time 1 – ns tSD Input data setup time 4 – ns tHD Input data hold time 1 – ns tSAD ADS setup time 4 – ns tHAD ADS hold time 1 – ns tSCN CNTEN setup time 4 – ns tHCN CNTEN hold time 1 – ns tSRST CNTRST setup time 4 – ns tHRST CNTRST hold time 1 – ns tOE Output enable to data valid – 10 ns tOLZ OE to Low Z 2 – ns tOHZ OE to High Z 1 7 ns tCD1 Clock to data valid - flow-through – 20 ns tCD2 Clock to data valid - pipelined – 9 ns tDC Data output hold after clock HIGH 2 – ns tCKHZ Clock HIGH to output high Z 2 9 ns tCKLZ Clock HIGH to output low Z 2 – ns Port to Port Delays tCWDD Write port clock high to read data delay – 40 ns tCCS Clock to clock setup time – 15 ns Document Number: 38-06053 Rev. *E Page 7 of 19 CY7C09159AV Switching Waveforms Figure 1. Read Cycle for Flow-Through Output (FT/PIPE = VIL)[4, 5, 6, 7] tCH1 tCYC1 tCL1 CLK CE0 tSC tHC tSW tSA tHW tHA tSC tHC CE1 R/W An ADDRESS An+1 An+2 An+3 tCKHZ tDC tCD1 DATAOUT Qn Qn+1 Qn+2 tDC tCKLZ tOHZ tOLZ OE tOE Figure 2. Read Cycle for Pipelined Operation (FT/PIPE = VIH)[4, 5, 6, 7] tCH2 tCYC2 tCL2 CLK CE0 tSC tHC tSW tSA tHW tHA tSC tHC CE1 R/W ADDRESS DATAOUT An An+1 1 Latency An+2 tDC tCD2 Qn tCKLZ An+3 Qn+1 tOHZ Qn+2 tOLZ OE tOE Notes 4. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 5. ADS = VIL, CNTEN and CNTRST = VIH 6. The output is disabled (high-impedance state) by CE0=VIH or CE1 = VIL following the next rising edge of the clock. 7. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. Document Number: 38-06053 Rev. *E Page 8 of 19 CY7C09159AV Switching Waveforms (continued) Figure 3. Bank Select Pipelined Read[8, 9] - tCH2 tCYC2 tCL2 CLKL tHA tSA ADDRESS(B1) A0 A1 A3 A2 A4 A5 tHC tSC CE0(B1) tCD2 tHC tSC tCD2 tHA tSA A0 ADDRESS(B2) tDC A1 tDC tSC tCKLZ A3 A2 tCKHZ D3 D1 D0 DATAOUT(B1) tCD2 tCKHZ A4 A5 tHC CE0(B2) tSC tCD2 tHC tCKHZ DATAOUT(B2) tCD2 D4 D2 tCKLZ Figure 4. Left Port Write to Flow-Through Right Port tCKLZ Read[10, 11, 12, 13] CLKL tSW tHW tSA tHA R/WL ADDRESSL NO MATCH MATCH tHD tSD DATAINL VALID tCCS CLKR R/WR ADDRESSR tCD1 tSW tSA tHW tHA NO MATCH MATCH tCWDD DATAOUTR tCD1 VALID tDC VALID tDC Notes 8. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this data sheet. ADDRESS(B1) = ADDRESS(B2). 9. OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH. 10. The same waveforms apply for a right port write to flow-through left port read. 11. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 12. OE = VIL for the right port, which is being read from. OE = VIH for the left port, which is being written to. 13. It tCCS ≤ maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS>maximum specified, then data is not valid until tCCS + tCD1. tCWDD does not apply in this case. Document Number: 38-06053 Rev. *E Page 9 of 19 CY7C09159AV Switching Waveforms (continued) Figure 5. Pipelined Read-to-Write-to-Read (OE = VIL)[14, 15, 16, 17] tCH2 tCYC2 tCL2 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An ADDRESS An+1 tSA An+2 An+2 An+3 An+4 tSD tHD tHA DATAIN tCD2 tCKHZ Dn+2 tCD2 tCKLZ Qn DATAOUT READ Qn+3 NO OPERATION WRITE READ Figure 6. Pipelined Read-to-Write-to-Read (OE Controlled)[14, 15, 16, 17] tCH2 tCYC2 tCL2 CLK CE0 tSC tHC CE1 R/W tSW tHW tSW tHW An An+1 An+2 An+3 An+4 An+5 ADDRESS tSA tHA tSD tHD Dn+2 DATAOUT Dn+3 tCD2 DATAIN tCKLZ tCD2 Qn Qn+4 tOHZ OE READ WRITE READ Notes 14. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only 15. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. 16. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 17. During “No operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. Document Number: 38-06053 Rev. *E Page 10 of 19 CY7C09159AV Switching Waveforms (continued) Figure 7. Flow-Through Read-to-Write-to-Read (OE = VIL)[18, 19, 20, 21, 22] tCH1 tCYC1 tCL1 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An ADDRESS An+1 tSA DATAIN An+2 An+2 tSD tHA An+3 tHD Dn+2 tCD1 tCD1 DATAOUT An+4 tCD1 Qn tCD1 Qn+1 tDC tCKHZ READ Qn+3 tCKLZ NO OPERATION WRITE tDC READ Figure 8. Flow-Through Read-to-Write-to-Read (OE Controlled)[18, 19, 20, 21, 22] tCH1 tCYC1 tCL1 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An An+1 An+2 An+3 An+4 An+5 ADDRESS tSA DATAIN tSD tHA tDC tCD1 DATAOUT tHD Dn+2 Dn+3 tOE tCD1 Qn tCD1 Qn+4 tOHZ tCKLZ tDC OE READ WRITE READ Notes 18. ADS = VIL, CNTEN and CNTRST = VIH 19. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only 20. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. 21. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 22. During “No operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. Document Number: 38-06053 Rev. *E Page 11 of 19 CY7C09159AV Switching Waveforms (continued) Figure 9. Pipelined Read with Address Counter Advance[23] tCH2 tCYC2 tCL2 CLK tSA tHA ADDRESS An tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tSCN DATAOUT tHCN Qx-1 tCD2 Qx READ EXTERNAL ADDRESS Qn Qn+1 tDC READ WITH COUNTER Qn+2 COUNTER HOLD Qn+3 READ WITH COUNTER Figure 10. Flow-Through Read with Address Counter Advance[23] tCH1 tCYC1 tCL1 CLK tSA tHA An ADDRESS tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tSCN DATAOUT tHCN tCD1 Qx Qn Qn+1 Qn+2 Qn+3 tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER Note 23. CE0 and OE = VIL; CE1, R/W and CNTRST = VIH. Document Number: 38-06053 Rev. *E Page 12 of 19 CY7C09159AV Switching Waveforms (continued) Figure 11. Write with Address Counter Advance (Flow-Through or Pipelined Outputs)[24, 25] tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL ADDRESS An tSAD tHAD tSCN tHCN An+1 An+2 An+3 An+4 ADS CNTEN Dn DATAIN tSD tHD WRITE EXTERNAL ADDRESS Dn+1 Dn+1 WRITE WITH COUNTER Dn+2 WRITE COUNTER HOLD Dn+3 Dn+4 WRITE WITH COUNTER Notes 24. CE0 and R/W = VIL; CE1 and CNTRST = VIH. 25. The “Internal Address” is equal to the “External Address” when ADS = VIL and equals the counter output when ADS = VIH. Document Number: 38-06053 Rev. *E Page 13 of 19 CY7C09159AV Switching Waveforms (continued) Figure 12. Counter Reset (Pipelined Outputs)[26, 27, 28, 29] tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL ADDRESS AX 0 tSW tHW tSD tHD 1 An+1 An An+1 R/W tSAD tHAD tSCN tHCN tSRST tHRST ADS CNTEN CNTRST DATAIN D0 DATAOUT Q0 COUNTER RESET WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 Q1 Qn READ ADDRESS n Notes 26. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only 27. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. 28. CE0 = VIL; CE1 = VIH. 29. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. Document Number: 38-06053 Rev. *E Page 14 of 19 CY7C09159AV Table 1. Read/Write and Enable Operation[30, 31, 32] Inputs OE CLK CE0 Outputs CE1 R/W I/O0–I/O9 Operation [33] X H X X High-Z Deselected X X L X High-Z Deselected[33] X L H L DIN L L H H DOUT Read[33] L H X High-Z Outputs disabled H X Table 2. Address Counter Control Operation Address Previous Address X X CLK Write [30, 34, 35, 36] ADS CNTEN CNTRST I/O Mode Operation X X L Dout(0) Reset Counter reset to address 0 An X L X H Dout(n) Load Address load into counter X An H H H Dout(n) Hold External address blocked—counter disabled X An H L H Dout(n+1) Increment Counter enabled—internal address generation Notes 30. “X” = “don’t care,” “H” = VIH, “L” = VIL. 31. ADS, CNTEN, CNTRST = “don’t care.” 32. OE is an asynchronous input signal. 33. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle. 34. CE0 and OE = VIL; CE1 and R/W = VIH. 35. Data shown for Flow-through mode; pipelined mode output will be delayed by one cycle. 36. Counter operation is independent of CE0 and CE1. Document Number: 38-06053 Rev. *E Page 15 of 19 CY7C09159AV Ordering Information Table 3. 8 K × 9 3.3-V Synchronous Dual-Port SRAM Speed (ns) 9 Package Name Ordering Code CY7C09159AV-9AXC A100 Package Type 100-Pin Pb-free Thin Quad Flat Pack Operating Range Commercial Ordering Code Definitions CY7C 09 XX9 AV X AX C Tem perature Grades C = Com m ercial Package Type AX: 100 pin Pb-free TQFP Speed: 9 ns 3.3 V Density: 159 = 8 K Synchronous Dual Port SRAM Com pany ID: CY = Cypress SRAM s Document Number: 38-06053 Rev. *E Page 16 of 19 CY7C09159AV Package Diagram Figure 13. 100-Pin TQFP (14 × 14 × 1.4 mm) 51-85048 *E Acronyms Document Conventions Acronym Description CMOS complementary metal oxide semiconductor TQFP thin quad plastic flatpack I/O input/output SRAM static random access memory Document Number: 38-06053 Rev. *E Units of Measure Symbol Unit of Measure °C degree Celsius MHz megahertz µA microampere mA milliampere mV millivolt ns nanosecond Ω ohm pF picofarad V volt W watt Page 17 of 19 CY7C09159AV Document History Page Document Title: CY7C09159AV 3.3-V 8 K × 9 Synchronous Dual Port Static RAM Document Number: 38-06053 Revision ECN Orig. of Change Submission Date Description of Change ** 110205 SZV 11/15/01 Change from Spec number: 38-00839 to 38-06053 *A 122303 RBI 12/27/02 Power up requirements added to Maximum Ratings Information *B 393581 YIM See ECN Added Pb-Free Logo Added Pb-Free parts to ordering information: CY7C09159AV-9AXC, CY7C09159AV-12AXC, CY7C09169AV-12AXC, CY7C09169AV-12AXI *C 2897159 RAME 03/22/10 Removed inactive parts from ordering information and updated package diagram. *D 3076884 ADMU 11/02/10 Updated as per latest template Added Acronyms and Units of Measure table Added Ordering Code Definitions. *E 3432711 ADMU 11/08/11 Updated template according to current CY standards. Removed information on CY7C09169AV. Removed speed bin –12. Updated package diagram. Document Number: 38-06053 Rev. *E Page 18 of 19 CY7C09159AV Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing cypress.com/go/memory cypress.com/go/image PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2010-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-06053 Rev. *E Revised November 8, 2011 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 19 of 19