FDMF6704A - XSTM DrMOS The Xtra Small, High Performance, High Frequency DrMOS Module Benefits tm General Description The XSTM DrMOS family is Fairchild’s next-generation fullyoptimized, ultra-compact, integrated MOSFET plus driver power stage solutions for high current, high frequency synchronous buck DC-DC applications. The FDMF6704A XSTM DrMOS integrates a driver IC, two power MOSFETs and a bootstrap Schottky diode into a thermally enhanced, ultra compact 6 mm x 6 mm MLP package. With an integrated approach, the complete switching power stage is optimized with regards to driver and MOSFET dynamic performance, system inductance and RDS(ON). This greatly reduces the package parasitics and layout challenges associated with conventional discrete solutions. XSTM DrMOS uses Fairchild's high performance PowerTrenchTM 5 MOSFET technology, which dramatically reduces ringing in synchronous buck converter applications. PowerTrenchTM 5 can eliminate the need for a snubber circuit in buck converter applications. The driver IC incorporates advanced features such as SMOD for improved light load efficiency. A 5 V gate drive and an improved PCB interface optimized for a maximum low side FET exposed pad area, ensure higher performance. This product is compatible with the new Intel 6 mm x 6 mm DrMOS specification. Ultra compact size - 6 mm x 6 mm MLP, 44 % space saving compared to conventional MLP 8 mm x 8 mm DrMOS packages. Fully optimized system efficiency. Clean voltage waveforms with reduced ringing. High frequency operation. Features Ultra- compact thermally enhanced 6 mm x 6 mm MLP package 84 % smaller than conventional discrete solutions. Synchronous driver plus FET multichip module. High current handling of 35 A. Over 93 % peak efficiency. Logic level PWM input. Fairchild's PowerTrench® 5 technology MOSFETs for clean voltage waveforms and reduced ringing. Optimized for high switching frequencies of up to 1 MHz. Skip mode SMOD [low side gate turn off] input. Fairchild SyncFETTM [integrated Schottky diode] technology in the low side MOSFET. Applications Integrated bootstrap Schottky diode. Compact blade servers V-core, non V-core and VTT DC-DC converters. Desktop computers V-core, non V-core and VTT DC-DC converters. Workstations V-core, non V-core and VTT DC-DC converters. Gaming Motherboards V-core, non V-core and VTT DC-DC converters. Gaming consoles. High-current DC-DC Point of Load (POL) converters. Networking and telecom microprocessor voltage regulators. Small form factor voltage regulator modules. Adaptive gate drive timing for shoot-through protection. Driver output disable function [DISB# pin]. Undervoltage lockout (UVLO). Fairchild Green Packaging and RoHS compliant. Low profile SMD package. Power Train Application Circuit 12 V 5V CVDRV CVIN VDRV VCIN DISB# PWM Input OFF ON DISB# VIN RBOOT BOOT PWM SMOD# CGND CBOOT PHASE VSWH LOUT OUTPUT COUT PGND Figure 1. Power Train Application Circuit Ordering Information Order Number FDMF6704A Marking FDMF6704A_1 ©2008 Fairchild Semiconductor Corporation FDMF6704A Rev. F Temperature Range -55 °C to 150 °C Device Package 40 Pin, 3 DAP, MLP 6x6 mm 1 Packing Method Tape and Reel Quantity 3000 www.fairchildsemi.com FDMF6704A The Xtra Small, High Performance, High Frequency DrMOS Module August 2009 VCIN BOOT VDRV VIN GH Q1 DISB# Overlap VSWH Control PWM VDRV SMOD# Q2 PGND GL CGND Figure 2. Functional Block Diagram 18 43 32 19 20 21 1 2 3 4 5 6 7 17 34 VSWH 18 33 43 19 32 31 20 PGND PGND PGND PGND PGND PGND PGND PGND VSWH VSWH 22 23 24 25 26 27 28 35 VSWH VSWH PGND PGND PGND PGND PGND PGND PGND PGND 29 31 36 16 PWM DISB# NC CGND GL VSWH VSWH VSWH VSWH VSWH 30 17 VSWH 33 38 15 29 34 40 39 37 28 16 41 42 13 14 27 15 CGND 26 36 35 VIN 12 25 14 11 8 VIN VIN NC PHASE GH CGND BOOT VDRV VCIN SMOD# 13 37 VIN VIN VIN VIN VSWH PGND PGND PGND PGND PGND 24 42 VIN VIN VIN VIN VSWH PGND PGND PGND PGND PGND 9 10 12 23 38 41 VIN 22 CGND 21 9 10 8 7 6 5 4 3 11 40 39 30 PWM DISB# NC CGND GL VSWH VSWH VSWH VSWH VSWH 2 1 SMOD# VCIN VDRV BOOT CGND GH PHASE NC VIN VIN Pin Configuration Bottom View Top View Figure 3. 6mm x 6mm, 40L MLP FDMF6704A Rev. F 2 www.fairchildsemi.com FDMF6704A The Xtra Small, High Performance, High Frequency DrMOS Module Functional Block Diagram Pin Name Function 1 SMOD# 2 VCIN IC bias supply. Minimum 1 F ceramic capacitor is recommended from this pin to CGND. 3 VDRV Power for low side driver. Minimum 1 F ceramic capacitor is recommended to be connected as close as possible from this pin to CGND. 4 BOOT Bootstrap supply input. Provides voltage supply to high-side MOSFET driver. Connect bootstrap capacitor from this pin to PHASE. 5, 37, 41 CGND 6 GH When SMOD# = HI, low side driver is inverse of PWM input. When SMOD# = Low, low side driver is disabled. This pin has no internal pullup or pulldown. It should not be left floating. Do not add noise filter cap. IC ground. Ground return for driver IC. For manufacturing test only. This pin must be floated. Must not be connected to any pin. 7 PHASE 8, 38 NC No connect. Switch node pin for easy bootstrap capacitor routing. Electrically shorted to VSWH pin. 9-14, 42 VIN Power input. Output stage supply voltage. 15, 29-35, 43 VSWH, PHASE 16-28 PGND 36 GL For manufacturing test only. This pin must be floated. Must not be connected to any pin. 39 DISB# Output disable. When low, this pin disable FET switching (GH and GL are held low). This pin has no internal pullup or pulldown. It should not be left floating. Do not add noise filter cap. 40 PWM PWM Signal Input. This pin accepts a logic-level PWM signal from the controller. This pin has no internal pullup or pulldown. It should not be left floating. Do not add noise filter cap. Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point for the adaptive shoot-thru protection. Power ground. Output stage ground. Source pin of low side MOSFET(s). Absolute Maximum Rating Parameter Min Max Units VCIN, VDRV, DISB#, PWM, SMOD#, GL to CGND 6 V VIN to PGND, CGND 27 V BOOT, GH to VSWH, PHASE 6 V BOOT, VSWH, PHASE, GH to GND 27 V BOOT to VDRV 22 V IO(AV)* VIN = 12 V, VO = 1.3 V fSW = 350 kHz 35 A fSW = 1 MHz 32 A IO(peak)* RθJPCB Junction to PCB Thermal Resistance Operating and Storage Junction Temperature Range -55 80 A 3.75 °C/W 150 °C * IO(AV) and IO(peak) are measured in FCS evaluation board. These ratings can be changed with different application setting. Recommended Operating Range Parameter VCIN VIN Control Circuit Supply Voltage Output Stage Supply Voltage Min Typ Max Units 4.5 5 5.5 V 12 14 V 3 * * May be operated at lower input voltage. See figure 10. FDMF6704A Rev. F 3 www.fairchildsemi.com FDMF6704A The Xtra Small, High Performance, High Frequency DrMOS Module Pin Description VIN = 12 V, TA = 25 °C unless otherwise noted. Parameter Operating Quiescent Current Symbol IQ Conditions Min Typ Max PWM = GND 2 PWM = VCIN 2 Units mA VCIN UVLO UVLO Threshold 3.0 UVLO COMP Hysteresis 3.2 3.4 0.2 V V PWM, DISB# and SMOD# Input High Level Input Voltage 2 V Low Level Input Voltage Input Bias Current -2 0.8 V 2 A PWM = GND, delay between SMOD# or DISB# from HI to LO to GL from HI to LO. 15 ns Rise Time 10 % to 90 % 25 ns Fall Time 90 % to 10 % 20 ns Propagation Delay Time High Side Driver Deadband Time tDTHH GL going LO to GH going HI, 10 % to 10 % 25 ns Propagation Delay tPDHL PMW going LO to GH going LO 10 ns Rise Time 10 % to 90 % 25 ns Fall Time 90 % to 10 % 20 ns Low Side Driver Deadband Time tDTLH VSWH going LO to GL going HI, 10 % to 10 % 20 ns Propagation Delay tPDLL PWM going HI to GL going LO 10 ns Delay between GH from HI to LO and GL from LO to HI. 250 ns 250 ns Time Out Circuit 250 ns Time Delay FDMF6704A Rev. F 4 www.fairchildsemi.com FDMF6704A The Xtra Small, High Performance, High Frequency DrMOS Module Electrical Characteristics Adaptive Gate Drive Circuit Circuit Description The driver IC embodies an advanced design that ensures minimum MOSFET dead-time while eliminating potential shoot-through (cross-conduction) currents. It senses the state of the MOSFETs and adjusts the gate drive, adaptively, to ensure they do not conduct simultaneously. Refer to Figure 4 for the relevant timing waveforms. The FDMF6704A is a driver plus FET module optimized for synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. Each part is capable of driving speeds up to 1 MHz. To prevent overlap during the low-to-high switching transition (Q2 OFF to Q1 ON), the adaptive circuitry monitors the voltage at the GL pin. When the PWM signal goes HIGH, Q2 will begin to turn OFF after some propagation delay (tPDLL). Once the GL pin is discharged below 1 V, Q1 begins to turn ON after adaptive delay tDTHH. Low-Side Driver The low-side driver (GL) is designed to drive a ground referenced low RDS(ON) N-channel MOSFET. The bias for GL is internally connected between VDRV and CGND. When the driver is enabled, the driver's output is 180° out of phase with the PWM input. When the driver is disabled (DISB = 0 V), GL is held low. To preclude overlap during the high-to-low transition (Q1 OFF to Q2 ON), the adaptive circuitry monitors the voltage at the VSWH pin. When the PWM signal goes LOW, Q1 will begin to turn OFF after some propagation delay (tPDHL). Once the VSWH pin falls below 1 V, Q2 begins to turn ON after adaptive delay tDTLH. High-Side Driver The high-side driver (GH) is designed to drive a floating N-channel MOSFET. The bias voltage for the high-side driver is developed by a bootstrap supply circuit, consisting of the internal diode and external bootstrap capacitor (CBOOT). During start-up, VSWH is held at PGND, allowing CBOOT to charge to VDRV through the internal diode. When the PWM input goes high, GH will begin to charge the high-side MOSFET's gate (Q1). During this transition, charge is removed from CBOOT and delivered to Q1's gate. As Q1 turns on, VSWH rises to VIN, forcing the BOOT pin to VIN +VC(BOOT), which provides sufficient VGS enhancement for Q1. To complete the switching cycle, Q1 is turned off by pulling GH to VSWH. CBOOT is then recharged to VDRV when VSWH falls to PGND. GH output is in phase with the PWM input. When the driver is disabled, the high-side gate is held low. Additionally, VGS of Q1 is monitored. When VGS(Q1) is discharged low, a secondary adaptive delay is initiated, which results in Q2 being driven ON after 250 ns, regardless of VSWH state. This function is implemented to ensure CBOOT is recharged each switching cycle, particularly for cases where the power convertor is sinking current and VSWH voltage does not fall below the 1 V adaptive threshold. The 250 ns secondary delay is longer than tDTLH. SMOD The SMOD (Skip Mode) function allows for higher converter efficiency under light load conditions. During SMOD, the LS FET is disabled and it prevents discharging of output caps. When the SMOD# pin is pulled high, the sync buck converter will work in synchronous mode. When the SMOD# pin is pulled low, the LS FET is turned off. The SMOD function does not have internal current sensing. This SMOD# pin is connected to a PWM controller which enables or disables the SMOD automatically when the controller detects light load condition. Normally this pin is Active Low. FDMF6704A Rev. F 5 www.fairchildsemi.com FDMF6704A The Xtra Small, High Performance, High Frequency DrMOS Module Description of Operation tPDHL Timeout PWM GL tPDLL tDTLH GH to VSWH tDTHH VSWH Figure 4. Timing Diagram Switch Node Ringing Suppression Fairchild's DrMOS products have proprietary feature* that minimizes the peak overshoot and ringing voltage on the switch node (VSWH) output, without the need of external snubbers. The following pictures show the waveforms of an FDMF6704 DrMOS part and a competitor's part tested without snubbing. The tests were done in the same test circuit, under the same operating conditions. Figure 5. FDMF6704 Figure 6. Competitor Part * Patent Pending FDMF6704A Rev. F 6 www.fairchildsemi.com FDMF6704A The Xtra Small, High Performance, High Frequency DrMOS Module Timing Diagrams VIN = 12V, VCIN = 5V, TA = 25°C unless otherwise noted. 35 12 30 10 8 PLOSS, W ILOAD, A 25 VIN = 12 V VOUT = 1.3 V L = 440 nH 20 15 fSW = 1 MHz 6 4 10 VIN = 12 V VOUT = 1.3 V fSW = 1 MHz L = 440 nH 5 fSW = 350 kHz 2 0 0 0 25 50 75 100 125 0 150 5 10 15 Figure 7. Safe Operating Area 1.40 PLOSS (NORMALIZED) PLOSS (NORMALIZED) 1.12 1.00 1.10 1.08 1.06 1.04 VOUT = 1.3 V IOUT = 30 A L = 440 nH fSW = 350 kHz 1.02 0.90 1.00 0.98 300 400 500 600 700 800 900 1000 6 8 10 fSW, kHz 1.07 1.30 1.04 PLOSS (NORMALIZED) PLOSS (NORMALIZED) 1.40 1.01 0.98 VIN = 12 V VOUT = 1.3 V IOUT = 30 A L = 440 nH fSW = 350 kHz 4.8 16 VIN = 12 V IOUT = 30 A L = 440 nH fSW = 350 kHz 1.20 1.10 1.00 0.90 5.1 5.4 5.7 0.80 0.8 6.0 Driver Supply Voltage, V 1.1 1.4 1.7 2.0 2.3 2.6 2.9 3.2 Output Voltage, V Figure 11. Power Loss vs. Driver Supply Voltage FDMF6704A Rev. F 14 Figure 10. Power Loss vs. Input Voltage 1.10 0.89 4.5 12 Input Voltage, V Figure 9. Power Loss vs. Switching Frequency 0.92 35 1.14 1.10 0.95 30 1.16 1.20 0.80 200 25 Figure 8. Module Power Loss vs. Output Current VIN = 12 V VOUT = 1.3 V IOUT = 30 A L = 440 nH 1.30 20 ILOAD, A o PCB Temperature, C Figure 12. Power Loss vs. Output Voltage 7 www.fairchildsemi.com FDMF6704A The Xtra Small, High Performance, High Frequency DrMOS Module Typical Characteristics VIN = 12V, VCIN = 5V, TA = 25°C unless otherwise noted. 1.045 45 1.040 40 Driver Supply Current, mA PLOSS (NORMALIZED) 1.035 1.030 1.025 1.020 1.015 1.010 VIN = 12 V VOUT = 1.3 V IOUT = 30 A fSW = 350 kHz 1.005 1.000 0.995 220 VCIN = 5 V 35 30 25 20 15 10 5 275 330 385 0 200 440 300 400 500 600 Figure 13. Power Loss vs. Output Inductance 800 900 1000 Figure 14. Driver Supply Current vs. Frequency 50 60 fSW = 1 MHz VCIN = 5 V fSW = 1 MHz 49 55 Driver Supply Current, mA Driver Supply Current, mA 700 fSW, kHz Output Inductance, nH 50 45 40 35 48 47 46 45 44 43 42 41 30 4.5 4.8 5.0 5.3 5.5 5.8 40 -50 6.0 -25 0 Driver Supply Voltage, V 2.0 PWM Threshold Voltage, V PWM Threshold Voltage, V 2.0 1.8 VIH 1.6 1.4 VIL 1.2 1.0 5.3 5.5 5.8 125 150 VCIN = 5 V 1.8 VIH 1.6 1.4 VIL 1.2 1.0 -50 6.0 Driver Supply Voltage, V -25 0 25 50 75 100 125 150 o Temperature, C Figure 17. PWM Threshold Voltage vs. Driver Supply Voltage FDMF6704A Rev. F 100 Figure 16. Driver Supply Current vs. Temperature 2.2 5.0 75 o 2.2 4.8 50 Temperature, C Figure 15. Driver Supply Current vs. Drive Supply Voltage 4.5 25 Figure 18. PWM Threshold Voltage vs. Temperature 8 www.fairchildsemi.com FDMF6704A The Xtra Small, High Performance, High Frequency DrMOS Module Typical Characteristics 2.2 2.2 2.0 2.0 SMOD# Threshold Voltage, V SMOD# Threshold Voltage, V VIN = 12V, VCIN = 5V, TA = 25°C unless otherwise noted. VIH 1.8 1.6 VIL 1.4 1.2 1.0 4.5 4.8 5.0 5.3 5.5 5.8 VCIN = 5 V VIH 1.8 1.6 VIL 1.4 1.2 1.0 -50 6.0 -25 0 Driver Supply Voltage, V 25 50 75 100 125 150 o Temperature, C Figure 19. SMOD# Threshold Voltage vs. Driver Supply Voltage Figure 20. SMOD# Threshold Voltage vs. Temperature 2.2 2.2 2.0 2.0 DISB# Threshold Voltage, V DISB# Threshold Voltage, V VCIN = 5 V VIH 1.8 1.6 VIL 1.4 1.2 1.0 4.5 4.8 5.0 5.3 5.5 5.8 1.6 VIL 1.4 1.2 1.0 -50 6.0 Driver Supply Voltage, V -25 0 25 50 75 100 125 150 o Temperature, C Figure 21. DISB# Threshold Voltage vs. Driver Supply Voltage FDMF6704A Rev. F VIH 1.8 Figure 22. DISB# Threshold Voltage vs. Temperature 9 www.fairchildsemi.com FDMF6704A The Xtra Small, High Performance, High Frequency DrMOS Module Typical Characteristics Supply Capacitor Selection VCIN Filter For the supply input (VCIN) of the FDMF6704A, a local ceramic bypass capacitor is recommended to reduce the noise and to supply the peak current. Use at least a 1 F, X7R or X5R capacitor. Keep this capacitor close to the FDMF6704A VCIN and PGND pins. The VDRV pin provides power to the gate drive of the high side and low side power FET. In most cases, it can be connected directly to VCIN, the pin that provides power to the logic section of the driver. For additional noise immunity, an RC filter can be inserted between VDRV and VCIN. Recommended values would be 10 Ohms and 1 F. Bootstrap Circuit The bootstrap circuit uses a charge storage capacitor (CBOOT), as shown in Figure 23. A bootstrap capacitance of 100nF, X7R or X5R capacitor is adequate. A series bootstrap resistor would be needed for specific application in order to improve switching noise immunity. Typical Application VIN 12V V5V 5V VDRV PWM DISB# SMOD# VIN CGND VCIN BOOT PHASE VSWH PGND RBOOT CBOOT LOUT FDMF6704A VCC EN SMOD# PWM1 PWM Controller PWM2 VDRV PWM DISB# SMOD# VIN CGND VCIN BOOT PHASE VSWH PGND RBOOT CBOOT LOUT FDMF6704A VOUT PWM3 PWM4 CGND Signal GND Power GND VDRV PWM DISB# SMOD# VIN CGND VCIN BOOT PHASE VSWH PGND RBOOT CBOOT LOUT FDMF6704A VDRV PWM DISB# SMOD# VIN CGND VCIN BOOT PHASE VSWH PGND RBOOT CBOOT LOUT FDMF6704A Figure 23. Typical Application FDMF6704A Rev. F 10 www.fairchildsemi.com FDMF6704A The Xtra Small, High Performance, High Frequency DrMOS Module Application Information the FDMF6704A. The resistor and capacitor need to be of proper size for the power dissipation. 5. Place ceramic bypass capacitor and BOOT capacitor as close as possible to the VCIN and BOOT pins of the FDMF6704A to ensure clean and stable power. Routing width and length should be considered as well. Refer to Figure 24 for power loss testing method. Power loss calculation are as follows: (a) (b) (c) (d) (e) (f) (g) PIN PSW POUT PLOSS_MODULE PLOSS_BOARD EFFMODULE EFFBOARD = (VIN x IIN) + (V5V x I5V) = VSW x IOUT = VOUT x IOUT = PIN - PSW = PIN - POUT = 100 x PSW/PIN = 100 x POUT/PIN (W) (W) (W) (W) (W) (%) (%) 6. Include a trace from PHASE to VSWH in order to improve noise margin. Keep the trace as short as possible. 7. The layout should include the option to insert a small value series boot resistor between boot cap and BOOT pin. The boot loop size, including Rboot and Cboot, should be as small as possible. The boot resistor is normally not required, but is effective at improving noise operating margin in multi phase designs that may have noise issues due to ground bounce and high negative VSWH ringing. The VIN and PGND pins handle large current transients with frequency components above 100 MHz. If possible, these package pins should be connected directly to the VIN and board GND planes. The use of thermal relief traces in series with these pins is discouraged since this will add inductance to the power path. This added inductance in series with the PGND pin will degrade system noise immunity by increasing negative VSWH ringing. PCB Layout Guideline Figure 25 shows a proper layout example of FDMF6704A and critical parts. All of high current flow path, such as VIN, VSWH, VOUT and GND copper, should be short and wide for better and stable current flow, heat radiation and system performance. Following is a guideline which the PCB designer should consider: 1. Input ceramic bypass capacitors must be close to VIN and PGND pin of FDMF6704A to help reduce the input current ripple component induced by switching operation. 8. CGND pad and PGND pins should be connected by plane GND copper with multiple vias for stable grounding. Poor grounding can create a noise transient offset voltage level between CGND and PGND. This could lead to fault operation of gate driver and MOSFET. 2. The VSWH copper trace serves two purposes. In addition to being the high frequency current path from the DrMOS package to the output inductor, it also serves as heatsink for the lower FET in the DrMOS package. The trace should be short and wide enough to present a low impedance path for the high frequency, high current flow between the DrMOS and inductor in order to minimize losses and temperature rise. Please note that the VSWH node is a high voltage and high frequency switching node with high noise potential. Care should be taken to minimize coupling to adjacent traces. Additionally, since this copper trace also acts as heatsink for the lower FET, tradeoff must be made to use the largest area possible to improve DrMOS cooling while maintaining acceptable noise emission. 9. Ringing at the BOOT pin is most effectively controlled by close placement of the boot capacitor. Do not add an additional BOOT to PGND capacitor. This may lead to excess current flow through the BOOT diode. 10. SMOD#, DISB# and PWM pins don’t have internal pull up or pull down resistors. They should not be left floating. These pins should not have any noise filter caps. 11. Use multiple vias on each copper area to interconnect top, inner and bottom layers to help smooth current flow and heat conduction. Vias should be relatively large and of reasonable inductance. Critical high frequency components such as Rboot, Cboot, the RC snubber and bypass caps should be located close to the DrMOS module and on the same side of the PCB as the module. If not feasible, they should be connected from the backside via a network of low inductance vias. 3. Output inductor location should be as close as possible to the FDMF6704A for lower power loss due to copper trace. Care should be taken so that inductor dissipation does not heat the DrMOS. 4. The PowerTrench® 5 MOSFETs used in the output stage are very effective at minimizing ringing. In most cases, no snubber will be required. If a snubber is used, it should be placed near V5V A I5V IIN A CVDRV VIN CVIN VDRV VCIN DISB# PWM Input SMOD# DISB# VIN RBOOT BOOT PWM CBOOT PHASE VSWH SMOD# CGND PGND LOUT V VSW IOUT A VOUT COUT Figure 24. Power Loss Measurement Block Diagram FDMF6704A Rev. F 11 www.fairchildsemi.com FDMF6704A The Xtra Small, High Performance, High Frequency DrMOS Module Power Loss and Efficiency Measurement and Calculation FDMF6704A The Xtra Small, High Performance, High Frequency DrMOS Module TOP VIEW BOTTOM VIEW Figure 25. Typical PCB Layout Example FDMF6704A Rev. F 12 www.fairchildsemi.com FDMF6704A The Xtra Small, High Performance, High Frequency DrMOS Module Dimensional Outline and Pad layout FDMF6704A Rev. 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Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I40 FDMF6704A Rev. F 14 www.fairchildsemi.com FDMF6704A The Xtra, Small High Performance, High Frequency DrMOS Module TRADEMARKS