FDMF6730 Driver plus FET Multi-chip Module Features General Description Over 95% efficiency The FDMF6730 is a high efficiency Driver plus MOSFET power stage solution optimized for Ultra Mobile PC (UMPC) system power voltage supplies. It is fully compliant with the Intel UltraMobile Driver MOS (uDrMOS) Specification. The MOSFETs and driver have been optimized to perform with high efficiency at light and medium loads, ideal for compact PC devices. Internal 5V regulator for gate drive 6V-16V input range 1MHz max operating frequency SMOD operation capability for light load efficiency 5A current capability (10A with PASS FET) The internal driver IC integrates two highly efficient LDOs for internal gate-drive and external circuitry. The bootstrap diode is also integrated within the IC. When operating with a single low side MOSFET the uDrMOS module is capable of delivering up to 5A of continuous current. The PASS transistor may be easily routed in parallel with the low side MOSFET to provide up to 10A. The module also incorporates an over current protection flag from an RDSON current sense architecture. Current limit set by RDSON sensing to minimize power losses Integrated bootstrap diode Applications Ultra Mobile PC The device comes in a 6X6 Power QFN package for improved thermal performance. Notebook Computers Typical Application VIN VCC VIN LDO 5V OUT LDO 5V BOOT LDO ENABLE LDO EN VSW H LDO OUT VOUT PGND LDO OUT FDMF6730 LDRV PWM CONTROLLER LDO ADJ DRIVE HS G_PASS DRIVE LS PW M OUT CS_O UT CGND D_PASS CS_PROG S_PASS Figure 1. Power Train Application Circuit Ordering Information Part Current Rating Max [A] Input Voltage Typical [V] Frequency Max [KHz] Device Marking FDMF6730 10 6-16 1000 FDMF6730 ©2008 Fairchild Semiconductor Corporation FDMF6730 Rev. D2 1 www.fairchildsemi.com FDMF6730 Driver plus FET Multi-chip Module August 2008 FDMF6730 Driver plus FET Multi- chip Module Functional Block Diagram VC C BO O T PH A SE HD R V V IN LDO _5V 5V Reg V SW H LDO _EN LD O Adjust LD O_O U T P GN D LD R V O CP C urren t T rim m ing LDO_A DJ G _PASS D _PAS S D RIVE_HS D RIVE_LS C G ND CS _OUT C S_P RO G S_PASS Figure 2. Functional Block Diagram 1 VIN VIN VIN VIN VIN VSWH VSWH VSWH VSWH PGND Pin Configuration 10 PGND 40 11 PGND VIN VIN B (VIN) A (VSWH) PGND HDRV LDRV VIN VSWH CGND D_PASS PHASE G_PASS D (D_PASS) S_PASS BOOT C (CGND) LDO_5V S_PASS LDO_OUT S_PASS 31 20 LDO_EN DRIVE_LS DRIVE_HS CGND VCC CS_OUT CS_PROG NC 21 D_PASS S_PASS 30 LDO_ADJ Figure 3. 6mm X 6mm, 40L MLP Bottom View FDMF6730 Rev. D2 2 www.fairchildsemi.com Pin Name Function 1, 38 - 40 PGND Low Side FET Source Pin. Connect to GND 2 - 5, 36, A VSWH Switch Node Pin. Low Side FET Drain pin. Electrically shorted to PHASE pin 6 - 12,14,B VIN 13 HDRV Input Voltage Pin. Input voltage for buck converter HDRV pin. High Side driver output. Connected to High Side FET gate pin. 15, 24, C CGND IC Ground. Ground return for driver IC. 16 PHASE Switch Node Pin for easy bootstrap capacitor routing. Electrically shorted to VSWH pin. 17 BOOT Bootstrap Supply Input Pin. Provides voltage supply to high-side MOSFET driver. Connect bootstrap capacitor. 18 LDO_5V 5V Internal LDO Output. 19 LDO_OUT Adjustable LDO Output. 20 LDO_ADJ LDO Adjust Input. Connect to external voltage divider to adjust LDO output. 21 LDO_EN Adjustable LDO Enable Pin. 1 = Enable, 0 = Disable 22 DRIVE_LS Low Side PWM Input. Connect to PWM controller. 23 DRIVE_HS High Side PWM Input. Connect to PWM controller. 25 VCC 26 CS_OUT 27 CS_PROG 28, 35, D D_PASS 29 NC 30-33 S_PASS 34 G_PASS 37 LDRV Driver VCC. Connect to 5V. Current Sense Output. 1 = Over-current Fault, 0 = No Fault. Current Sense Program. Pass FET Drain Pin. Connect to VSWH pad for higher output current. No Connect. This pin must be floated. Must not be connected to any pin. Pass FET Source Pin. Connect to PGND pad for higher output current. Pass FET Gate Pin. Connect to LDRV pin for higher output current. LDRV pin. Low Side driver output. Connect to G_PASS pin for higher output current. Absolute Maximum Rating Stresses exceeding the absolute maximum rating may damage the device. The device may not function or be operable above the recommended operating conditions and stressing these parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect the device reliability. The absolute maximum rating are stress ratings only. Parameter Min. Max. Units VCC, Drive_LS, Drive_HS, LDO_EN, CS_Prog, CS_Out to GND -0.3 6 V VIN to PGND -0.3 20 V BOOT to VSWH -0.3 6 V VSWH to PGND -1.0 27 V -0.3 27 V 10 A BOOT to PGND IO(AV) VIN = 8.4V, VO = 3.3V, fSW = 1MHz, TPCB = 130°C IO(PK) VIN = 8.4V, tPULSE = 10 s 35 A RθJPCB Junction to PCB Thermal Resistance note 1. TPCB =130°C 5.5 °C/W PT Operating and Storage Junction Temperature Range -55 3.3 W 150 °C Note 1: Package power dissipation based on 4 layer, 2 square inch, 2 oz. copper pad. RθJPCB is the steady state junction to PCB thermal resistance with PCB temperature referenced at VSWH pin. FDMF6730 Rev. D2 3 www.fairchildsemi.com FDMF6730 Driver plus FET Multi- chip Module Pin Description The recommended operating conditions table defines the conditions for actual device operation. These conditions are specified to ensure optimal performance to the datasheet specification. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Parameter Min. Typ. Max. Units VCC Control Circuit Supply Voltage 4.5 5 5.5 V VIN Output Stage Supply Voltage 6 8.4 16 V VOUT Output Voltage 1.5 3.3 5 V Electrical Characteristics VIN = 8.4V, VCC = 5V, TA = 25°C unless otherwise noted. Parameter Input Voltage Range Symbol Conditions VIN Min. Typ. 6 Operating Quiescent Current Max. Units 16 V 2 mA Drive_HS, Drive_LS, LDO_EN Logic Inputs High Level Input VIH Low Level Input VIL 2.4 Input Current V -2 0.4 V 2 A 5V LDO Output Voltage 4.7 Line Regulation 6V < VIN < 16V Load Regulation 5mA < ILOAD < 100mA Short Circuit Current Limit 5 5.3 5 V mV 75 mV 100 180 mA 0.58 0.6 Adjustable LDO Adjust Voltage VADJ 0.62 V Line Regulation 6V < VIN < 16V 3 mV Load Regulation 5mA < ILOAD < 100mA 11 mV Short Circuit Current Limit 100 180 Adjust Input Bias Current mA 0.2 A 50 A Over Current Protection CS_Prog Current 30 40 Thermal Shutdown Threshold Hysteresis 150 o 19 o C C Propagation Delay 250ns Timeout FDMF6730 Rev. D2 tTIMEOUT VSWH = 2V, HDRV from HI to LO and LDRV from LO to HI 250 ns tDTHH LDRV going LO to VSWH going HI 30 ns tPDHL Drive_LS going HI to HDRV going LO 10 ns tDTLH VSWH going LO to LDRV going HI 20 ns tPDLL Drive_LS going LO to LDRV going LO 10 ns 4 www.fairchildsemi.com FDMF6730 Driver plus FET Multi- chip Module Recommended Operating Range Applications Section The PWM input is composed of a high side drive and a low side drive input which control the high side and low side FETs respectively. They can also be setup to provide asynchronous rectification (low FET off) and phase shutoff (both FETs off). A High frequency 4.7ceramic X5R must be connected directly from VIN to GND 2-Bit PWM Input Input Capacitor Bootstrap Circuit The bootstrap circuit uses a charge storage capacitor and an external diode. A minimum of 0.1 F high frequency capacitor must be connected between the BOOT and PHASE pin. The PHASE pin is already internally connected to the switch-node. Truth Table DRIVE_LS DRIVE_HS Low Side MOSFET High Side MOSFET 0 0 OFF OFF 0 1 OFF ON 1 0 ON OFF 1 1 OFF OFF 5V LDO A minimum of 4.7 F ceramic X5R type must be connected from LDO_5V pin to GND to ensure stable operation and to provide high frequency bypassing for low side driver. This LDO can provide power to the internal logic circuitry and gate drivers via a 10Ohm resistor. A high frequency 1 F ceramic capacitor must be placed from VCC to GND. PASS FET One of the most unique features of the uDrMOS is the integrated Pass FET. The pass FET can be easily routed in parallel with the low side FET in order to provide up to 10A of current. When not used as part of the DC-DC controller, it can be used in other applications such as load switching, etc. Adjustable LDO A minimum of 10 F ceramic X5R type must be connected close from this pin to GND to insure stable operation for a range of 2.5V to 5V outputs. For output voltages of 0.6V to 2.5V the minimum capacitance must be 22 F ceramic type. A minimum of 1mA load current must be connected from this pin to GND. LDO_ADJ voltage 0.6V typical. LDO_EN: Adjustable LDO enable pin (1= Enable, 0= Disable) 5V LDO The uDrMOS conveniently incorporates a 5V LDO regulator to drive the internal logic of the IC and gates of the internal MOSFETs. Over Current Protection Adjustable LDO A resistor connected from the VSWH pin and this pin programs the over current threshold point. CS_OUT is the output of an internal current sense comparator which switches high when the current in low side MOSFET exceeds a pre program level set by the CS_PROG pin. This pin is low during normal operation. Another feature of the part is the adjustable 100mA LDO. The LDO output voltage is easily configured with a resistor divider. Current Limit The part also has current limit flag which is set by an internal OCP topology. FDMF6730 Rev. D2 5 www.fairchildsemi.com FDMF6730 Driver plus FET Multi-chip Module Description of Operation 16 3.5 14 12 2.5 PLOSS, W 10 ILOAD, A VIN = 8.4V VOUT = 3.3V L = 2.2uH 3.0 8 6 2 FSW = 1MHz 1.5 FSW = 300KHz 1.0 VIN = 8.4V VOUT = 3.3V L = 2.2uH FSW = 1MHz 4 2.0 0.5 0 0.0 0 25 50 75 100 125 150 0 2 4 o PCB Temperature, C Figure 4. Safe Operating Area 1.02 1.06 0.96 0.94 0.92 0.90 1.04 1.02 1.00 VOUT = 3.3V ILOAD = 10A L = 2.2uH FSW = 1MHz 0.98 0.88 0.86 300 0.96 400 500 600 700 800 900 1000 6 8 Switching Frequency, KHz 1.10 12 14 16 Figure 7. Power Loss vs. Input Voltage 1.20 VIN = 8.4V ILOAD = 10A L = 2.2uH FSW = 1MHz VIN = 8.4V VOUT = 3.3V ILOAD = 10A FSW = 1MHz 1.15 PLOSS (NORMALIZED) PLOSS (NORMALIZED) 1.15 10 Input Voltage, V Figure 6. Power Loss vs. Switching Frequency 1.20 10 1.08 PLOSS (NORMALIZED) PLOSS (NORMALIZED) 0.98 8 Figure 5. Power Loss vs. Output Current VIN = 8.4V VOUT = 3.3V ILOAD = 10A L = 2.2uH 1.00 6 ILOAD, A 1.05 1.00 0.95 0.90 1.10 1.05 1.00 0.95 0.90 0.85 0.80 1.5 0.85 2 2.5 3 3.5 4 4.5 5 1 Output Voltage, V 2 2.5 3 3.5 Output Inductance, uH Figure 8. Power Loss vs. Output Voltage FDMF6730 Rev. D2 1.5 Figure 9. Power Loss vs. Output Inductance 6 www.fairchildsemi.com FDMF6730 Driver plus FET Multi-chip Module Typical Characteristics 3.00 0.64 2.75 0.62 Supply Current, mA Supply Current, mA 0.66 0.60 0.58 0.56 0.54 2.50 2.25 2.00 1.75 1.50 1.25 0.52 4 4.5 5 5.5 1.00 300 6 400 500 Driver Supply Voltage, V 700 800 900 1000 Figure 11. Supply Current vs. Frequency 0.66 1.40 0.64 1.38 LDO_EN Threshold Voltage, V Supply Current, mA Figure 10. Supply Current vs. Driver Supply 0.62 0.60 0.58 0.56 0.54 0.52 1.35 1.33 1.30 1.28 1.25 1.23 1.20 -50 -10 30 70 110 150 -50 -10 Temperature, oC 30 70 110 150 Temperature, oC Figure 12. Supply Current vs. Temperature Figure 13. LDO_EN Threshold Voltage vs. Temperature 1.9 1.9 1.8 1.8 Drive_HS Threshold Voltage, V Drive_LS Threshold Voltage, V 600 Frequency, kHz 1.7 1.6 1.5 1.4 1.3 1.2 1.7 1.6 1.5 1.4 1.3 1.2 -50 -10 30 70 110 150 -50 Temperature, oC 30 70 110 150 Temperature, oC Figure 14. Driver_LS Threshold Voltage vs. Temperature FDMF6730 Rev. D2 -10 Figure 15. Driver_HS Threshold Voltage vs. Temperature 7 www.fairchildsemi.com FDMF6730 Driver plus FET Multi-chip Module Typical Characteristics FDMF6730 Driver plus FET Multi-chip Module Typical Characteristics 41.0 CS_Prog Current, uA 40.5 40.0 39.5 39.0 38.5 38.0 37.5 -50 -10 30 70 110 150 Temperature, oC Figure 16. CS_Prog Current vs. Temperature FDMF6730 Rev. D2 8 www.fairchildsemi.com Dimensional Outline and Pad layout 0.10 C 6.00 2X 5.80 4.50 B A 21 31 2.10 0.30 6.00 2.10 11 0.10 C 2X TOP VIEW PIN #1 IDENT 0.60 1 0.30 0.50 TYP 2.10 0.80 MAX 0.10 C 0.35 2.10 RECOMMENDED LAND PATTERN (0.20) 0.08 C C SIDE VIEW 0.05 0.00 SEATING PLANE (0.20) 0.50 40X 0.30 2.00? .10 (2X) 1 PIN #1 IDENT 11 2.00? .10 (2X) (0.20) 4.40? .10 (0.20) 31 0.50 40X (2.20) 4.40? .10 BOTTOM VIEW 0.20~0.30 0.10 0.05 C A B C A. DOES NOT FULLY CONFORM TO JEDEC REGISTRATION, MO-220. DATED MAY/2005. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. DRAWING FILE NAME: MLP40XREV1 40LD,MLP,QUAD, NON-JEDEC, 6X6 MM, Four DAP 1 FDMF6730 Rev. D2 9 www.fairchildsemi.com FDMF6730 Driver plus FET Multi-chip Module THIS DRAWING IS THE PROPERTY OF FAIRCHILD SEMICONDUCTOR CORPORATION. NO USE THEREOF SHALL BE MADE OTHER THAN AS A REFERENCE FOR PROPOSALS AS SUBMITTED TO FAIRCHILD SEMICONDUCTOR CORPORATION FOR JOBS TO BE EXECUTED IN CONFORMITY WITH SUCH PROPOSALS UNLESS THE CONSENT OF SAID FAIRCHILD SEMICONDUCTOR CORPORATION HAS PREVIOUSLY BEEN OBTAINED. NO PART OF THIS DRAWING SHALL BE COPIED OR DUPLICATED OR ITS CONTENTS DISCLOSED. THE INFORMATION CONTAINED ON THIS DRAWING IS CONFIDENTIAL AND PROPRIETARY. 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Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I35 FDMF6730 Rev. D2 10 www.fairchildsemi.com FDMF6730 Driver plus FET Multi-chip Module TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidianries, and is not intended to be an exhaustive list of all such trademarks.