GC5325 www.ti.com .............................................................................................................................................................................................. SLWS215 – JANUARY 2009 GC5325 Wideband Digital Predistortion Transmit Processor • FEATURES 1 • Integrated CFR and DPD Functions • Up to 20-MHz Combined Signal Bandwidth • CFR: Typically Meets 3GPP TS 25.141 <6.5 dB PAR, <8 dB PAR for 802.16e Signals • DPD: Memory Compensation, Typical ACLR Improvement of 20 dB to 30 dB or More • Transmit- and Feedback-Channel Equalizers • 352-Ball S-PBGA Package, 27 mm × 27 mm • 1.2-V Core, 3.3-V I/O • Typical Power Consumption = 1.9 W 23 • Flexible DSP Algorithm Supports Existing and Emerging Wireless Standards Supports Direct Interface to TI High-Speed Data Converters APPLICATIONS • • • • 3GPP (W-CDMA, TD-SCDMA) Base Stations 3GPP2 (CDMA2000) Base Stations WiMAX and WiBRO (OFDMA) Base Stations Multicarrier Power Amplifiers (MCPAs) SYSTEM BLOCK DIAGRAM DAC5682Z GC5325 Baseband Input DAC I/Q DAC TRF3703 I/Q Modulator HPA LPA CFR–DPD TRF3761 LO CDCM7005 ADC 'C6727 ADS6149 THS9001 Mixer DSP B0278-02 DESCRIPTION The GC5325 is a wideband digital predistortion transmit processor that includes a crest factor reduction (CFR) block and a digital predistortion (DPD) block with its associated feedback chain and capture buffers. The GC5325 processes composite input bandwidths of up to 20 MHz and processes DPD sample rates of up to 140 MHz. The GC5325 accepts a composite signal over an interleaved parallel interface at a data rate of up to 140 MSPS. The GC5325 CFR block reduces the peak-to-average ratio (PAR) of wideband digital signals provided in quadrature (I/Q) format, such as those used in third-generation (3G) code division multiple access (CDMA) wireless and orthogonal frequency division multiple access (OFDMA) applications. The GC5325 DPD block reduces adjacent-channel leakage ratio (ACLR), or out-of-band energy, by 20 dB to 30 dB or more. The efficiency of follow-on power amplifiers (PAs) is substantially improved by reducing the PAR and ACLR of digital signals. The digital-to-RF conversion can be further simplified by the fractional interpolator between the CFR and the DPD blocks, and a bulk upconverter (BUC) in the final stage of the GC5325. This feature typically eliminates the need for superheterodyne (dual-stage) upconversion architectures. Transmit and feedback NCO/mixers provide additional flexibility in the system frequency planning. 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS320C64x, C55x, C64x are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated GC5325 SLWS215 – JANUARY 2009 .............................................................................................................................................................................................. www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTIONS PACKAGED DEVICE (1) TC 352-ball S-PBGA package, 27 mm × 27 mm –40°C to 85°C (1) GC5325IZND For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. GC5325 FUNCTIONAL BLOCK DIAGRAM RESETB SYNC SYNC INT UPDATA UPADDR OEB RDB WRB CEB OUT 3 16 10 GC5325 MPU Interface TCK TRSTB TDI TMS TDO 4 JTAG BBin 16 BBFR Input Interface CFR Fractional Farrow Resampler Circular Limiter MFIO[19:18] 2 (Optional; additional 2 LSBs) FB (LVDS) 18 Pairs ADC Interface Real to Complex (or Bypass) Feedback Equalizer BB PLL BBCLK DPD PLL DPDCLK (LVDS) Feedback NL Correction SYNCD TX (Diff.) 19 Pairs DAC Interface Bulk Interpolation + Mixer Transmit Equalizer (LVDS) DPD Capture Buffers BB Clock Domain DPD Clock Domain B0279-02 2 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5325 GC5325 www.ti.com .............................................................................................................................................................................................. SLWS215 – JANUARY 2009 DETAILED DESCRIPTION GC5325 Introduction The GC5325 is a flexible transmit sector processor that includes a crest factor reduction (CFR) block and a digital predistortion (DPD) block and its associated feedback chain. The GC5325 processes composite input bandwidths of up to 40 MHz and processes DPD expansion bandwidths of up to 140 MHz (actual performance may vary for signal bandwidths exceeding 23 MHz). By reducing both the peak-to-average ratio (PAR) of the input signals using the CFR block and linearizing the power amplifier (PA) using the DPD block, the GC5325 reduces the costs of multicarrier PAs (MCPA) for wireless infrastructure applications. The GC5325 applies CFR and DPD while a separate microprocessor (a Texas Instruments TMS320C6727 DSP) is used to optimize performance levels and maintain target PA performance levels. By including the GC5325 in their system architecture, manufacturers of BTS equipment can realize significant savings on power amplifier bill of materials (BOM) and overall operational costs due to the PA efficiency improvement. The GC5325 meets multicarrier 3G performance standards (PCDE, composite EVM, and ACLR) at PAR levels down to 6.5 dB and improves the ACLR, at the PA output, by 20 dB to 30 dB or more. The GC5325 integrates easily into the transmit signal chain between baseband processors such as the Texas Instruments TMS320C64x™ DSP family and their high-performance data converters. A • • • • • • • typical GC5325 system application would include the following transmit-chain components: TMS320C6727 digital signal processor (DSP) DAC5682 16-bit, 1-GSPS DAC (transmit path) CDCM7005 clock generator TRF3761 integrated VCO/PLL synthesizer TRF3703 quadrature modulator ADS5517 11-bit 200-MSPS or ADS6149 14-bit, 250-MSPS ADC (feedback path) AMC7823 analog monitoring and control circuit with GPIO and SPI Baseband Interface The GC5325 BB interface block accepts baseband signals over an interleaved parallel interface at a data rate of up to 140 MHz. The input interface supports up to 12 separate baseband carriers. The GC5325 input interface can be programmed in a wideband mode in which users are required to channelize the data using an external processor. Gain/Pilot Insertion/AntCal Insertion/Power Meter Baseband gain can be applied on a per-carrier basis to accurately control the individual channel power through the system. Also present is the functionality for adding pilot codes to the data stream for antenna calibration applications. Independent programmable RMS power meters for up to 12 channels are also included in this block of the device. Crest Factor Reduction (CFR) The GC5325 CFR block selectively reduces the peak-to-average ratio (PAR) of wideband digital signals provided in quadrature (I and Q) format, such as those used in third-generation (3G) code division multiple access (CDMA) wireless applications. The CFR block can reduce the PAR of W-CDMA Test Model 1 and Test Model 3 signals down to 6.5 dB output PAR while still meeting all 3GPP requirements for ACLR, composite EVM, and peak code domain error (PCDE). The CFR block accepts input sampling rates up to 140 MSPS complex from the input interface. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5325 3 GC5325 SLWS215 – JANUARY 2009 .............................................................................................................................................................................................. www.ti.com Fractional Farrow Resampler (FR) The CFR block output signal bandwidth is up to 40 MHz wide, sampled at up to 70 MSPS. However; the DPD block provides PA compensation over an expansion bandwidth of up to 140 MHz, using a complex sampling rate of up to 140 MSPS. To provide the requisite sampling rate of up to 140 MSPS at the input to DPD, the output of the CFR block must be resampled. The GC5325 performs this (nominally 2×) upsampling function using a Farrow filter resampler. The user-programmable Farrow resampler supports upsampling rates from 1× to 64×, with 16-bit precision on the interpolation ratio. It marks the transition of the input clock domain (driven by the input interface clock) to the transmit domain (driven by the DAC sampling clock). Digital Predistortion (DPD) The DPD block provides predistortion for up to Nth-order nonlinearities, and can correct multiple orders and lengths of PA memory effects. The predistortion correction terms are computed by an external processor (for example, TI TMS320C6727 DSP) based on PA feedback data captured in the GC5325. The external processor reads the captured data buffers from the GC5325 and writes back the newly computed DPD correction terms on a continuous basis. TI provides a base delivery of 'C6727 software to GC5325 customers that achieves a typical ACLR improvement of 20 dB to 30 dB or more when compared to a PA without DPD. The standard EMIF bus allows the user to provide an alternate DPD adaptation algorithm and DSP embodiment, if desired. Bulk Upconverter (BUC) The bulk upconverter block can interpolate the DPD block output by 1.5×, 2×, 3× with a complex output, or 6× with a real output. The complex-to-real converter block optionally modifies the DPD complex output stream into a real output stream. The bulk upconverter has flexible mixing options between its various interpolation stages. When used in combination, the bulk upconverter and the complex-to-real functions allow the GC5325 to output a 16-bit real signal at up to 840 MSPS, or a complex signal at up to 420 MSPS. Next-generation data converters can accept sampling rates as high as 1 GSPS and sample widths of 16 bits. In a typical application, the bulk upconverter outputs a 737.28-MSPS real sampling rate (16 bits/sample) directly to the DAC on a modified center frequency of 184.32 MHz (1/4 of the 737.28-MSPS sampling rate). The bulk upconverter has multiple high-speed, low-voltage, single-ended/differential output interfaces to existing and future TI DACs. Feedback Path (FB) The feedback block accepts an external A/D converter input that represents the PA output signal. This feedback signal is processed by a feedback path that adjusts for gain, frequency, and phase anomalies in the RF-to-IF downconversion chain. The feedback path includes an 8-tap complex receive equalizer and lookup tables that can compensate for the nonlinearities in the RF-to-IF part of the feedback chain. The block also includes a real-to-complex conversion to facilitate signal processing. The GC5325 connects directly to the ADS5444, ADS5545, ADS5546, and ADS5517 among others, without requiring external components. The GC5325 simplifies timing by providing a FIFO for each ADC port, sampling the input data using the ADC data-ready signal. Microprocessor Interface (MPU) The MPU interface is designed to interface with external memory interface (EMIF) ports on TI DSPs operating in asynchronous mode. It consists of a 16-bit bidirectional data bus, a 10-bit address bus, and RDB, WRB, OEB, and CEB control signals. The interface fully supports TI C55x™, C64x™ DSPs and, with minimal effort, supports the low-cost 'C6727 floating-point DSP. Smart Capture Buffers (SCB) The GC5325 has two capture buffers, each 4096 complex words deep, which are periodically read by the external coefficient update controller (DSP) in order to optimize the DPD coefficients. The first capture buffer can be used to capture: • The output of the Farrow resampler; this is also called the reference signal. • The feedback output; this represents the waveform as seen by the PA. • The error output • Testbus(31:16) The second capture buffer can be used to provide: 4 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5325 GC5325 www.ti.com .............................................................................................................................................................................................. SLWS215 – JANUARY 2009 • • • • The output of the Farrow resampler; this is also called the reference signal. The feedback output; this represents the waveform as seen by the PA. The error output Testbus(15:0) The reference and feedback buffers are time-aligned by the GC5325, because there may be a delay of tens or even hundreds of samples between the transmitted signal and the feedback signal from the PA output. The capture controller can trigger a capture on several different metrics, including an above-threshold peak count or an average signal power value. Input and Output Syncs The GC5325 features multiple-user programmable input syncs. These are typically used as trigger mechanisms to activate features within the device. These triggers can be provided internally or through externally provided inputs. The input syncs can be used to trigger: • Power measurements • Initializing/loading the feedback, equalizer, LUTs, etc. • Flush out data within the processing blocks of the device • Feedback path tuner alignment • Capturing and sourcing of data through SCBs Programmable Power Meters There are three power meter locations/functions within the GC5325. The first is a channel RMS power meter. The second power meter is located at the output of the CFR block, and the final power detector is similar to the CFR output power detector and is located at the Farrow resampler output. This power meter can measure RMS power integrated up to a million samples at the DPD sample rate. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5325 5 GC5325 SLWS215 – JANUARY 2009 .............................................................................................................................................................................................. www.ti.com Pin Assignment and Descriptions GND Package (Bottom View) 26 A 25 24 23 22 VSS1 VSS1 VSS1 VSS1 FB1 19 18 16 FB9 VDD FB31 FB35 VSSA2 SYNCC BB15 BB11 BB7 SHV BB3 BB0 VSS1 VSS1 VSS1 BB4 BB1 VSS1 VSS1 VDD1 BB5 BB2 VSS1 VDD1 VSS1 FB11 FB15 FB17 FB21 FB25 FB27 12 11 9 8 7 6 3 FB5 14 10 5 20 17 15 13 21 4 2 1 B VDD1 VSS1 VSS1 VSS1 FB0 FB4 VDD FB30 FB34 VDDA2 SYNCB BBFR BB12 BB8 FB8 FB10 FB14 FB16 FB20 FB24 FB26 SHV C VSS1 VDD1 VSS1 VSS1 NC FB3 FB7 VDD1 FB13 VDD ADC FB29 FB33 VDD1 SYNCA BBCLK BB13 BB9 FB19 FB23 VDD1 SHV IREF D VSS1 VSS1 VDD1 VSS1 NC FB2 FB6 VDD1 FB12 VDD SYNC ADC FB28 FB32 VSS1 FB18 FB22 VDD1 VDD1 BB14 BB10 BB6 VSS1 VDD1 VSS1 VSS1 SHV OUT VREF E VSS1 VSS1 VSS1 VDD1 VDD1 VSS1 VSS1 VSS1 F VSS1 VSS1 VSS1 VDD1 VDD1 VDD1 VSS1 VSS1 G VSS1 VSS1 VSS1 VDD SHV VDD VSS1 VSS1 VSS1 SHV VDD1 UP UP UP ADDR2 ADDR1 ADDR0 VDD1 VDD1 UP UP UP ADDR5 ADDR4 ADDR3 VDD VDD1 SHV VDD1 UP UP UP ADDR8 ADDR7 ADDR6 VDD1 VDD1 UP VDD WRB SHV ADDR9 VDD1 VDD1 OEB H NC NC J VPP1 NC K NC NC L NC NC NC M NC NC NC N NC NC VDD VDD1 SHV VDD1 UP UP UP DATA2 DATA1 DATA0 P NC NC MFIO18 VDD1 VDD1 VDD VSS1 VSS1 SHV R VPP1 VDD1 NC CEB RDB MFIO19 NC NC VDD1 VDD1 UP UP UP DATA5 DATA4 DATA3 NC VDD1 VDD1 UP VDD VPP2 SHV DATA6 VDD VDD1 SHV VDD1 UP UP VPP2 DATA8 DATA7 T NC NC U NC NC V NC NC NC VDD1 VDD1 UP UP UP DATA11 DATA10 DATA9 W NC NC NC VDD1 VDD1 UP UP UP DATA14 DATA13 DATA12 Y NC VSS1 VSS1 VDD1 UP VDD VSS1 VSS1 SHV DATA15 AA VSS1 VSS1 VSS1 VDD1 VDD1 VSS1 VSS1 VSS1 AB VSS1 VSS1 VSS1 VDD1 VDD1 VDD1 VSS1 VSS1 AC VSS1 VSS1 VDD1 AD VSS1 VDD1 VSS1 VSS1 DPD DPD VSS1 VDDA1 TX3 IREF CLKC AE VDD1 VSS1 VSS1 VSS1 DPD VDD SYNCD SHV VREF AF VSS1 VSS1 VSS1 VSS1 VSS1 RESET VDD SHV B DPD VSS1 VDD1 TX2 CLK TX6 TX10 TX14 VDDS VSS1 DAC TX25 TX29 TX33 TX37 VSS1 VDD1 VDD2 VSS1 VDD1 VSS1 VSS1 REFP TX7 TX11 TX15 VDDS VSS1 VDD DAC VDD1 VSS2 VSS1 VSS1 VDD1 VSS1 TX24 TX28 TX32 TX36 SHV REFN TX12 TX16 VDDS TX19 TX21 TX23 TX27 TX31 TX35 TRSTB TDI TX0 TX4 TX8 SYNC VSSA1 TX1 DC TX5 TX9 TX13 TX17 VSS1 TX18 TX20 TX22 TX26 TX30 TX34 TMS TCK INTERVSS1 VSS1 VSS1 VDD1 RUPT TDO = Baseband Input = Transmit Ouput = Feedback Input = Microprocessor Interface = Miscellaneous = Multi-Function Input/Output = Power and Biasing = JTAG Interface = NC TEST VSS1 VSS1 VSS1 MODE P0077-01 6 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5325 GC5325 www.ti.com .............................................................................................................................................................................................. SLWS215 – JANUARY 2009 Table 1. TERMINAL FUNCTIONS TERMINAL NAME I/O NO. DESCRIPTION MICROPROCESSOR INTERFACE OEB M3 I Output enable CEB M2 I Chip enable RDB M1 I Read WRB L2 I Write UPADDR[9:0] L1, K3, K2, K1, J3, J2, J1, H3, H2, H1 I Microprocessor address UPDATA[15:0] Y1, W3, W2, W1, V3, V2, V1, U3, U2, T1, R3, R2, R1, N3, N2, N1 I/O Microprocessor data INTERRUPT AE5 O Microprocessor interrupt POWER AND BIASING VDD1 B1, B26, C2, C10, C14, C19, C25, D3, D8, D14, D19, D24, E4, E23, F3, F4, F23, H4, H23, J4, J23, K4, K23, L4, L23, M4, M23, N4, N23, P4, P23, R4, R23, T4, T23, U4, U23, V4, V23, W4, W23, Y23, AA4, AA23, AB3, AB4, AB23, AC3, AC6, AC19, AC24, AD2, AD6, AD25, AE1, AE26 PWR 1.2-V supply VSS1 A1, A2, A3, A23, A24, A25, A26, B2, B3, B23, B24, B25, C1, C3, C23, C24, C26, D1, D2, D4, D10, D23, D25, D26, E1, E2, E3, E24, E25, E26, F1, F2, F24, F25, F26, G1, G2, G3, G24, G25, G26, P1, P2, Y2, Y3, Y24, Y25, AA1, AA2, AA3, AA24, AA25, AA26, AB1, AB2, AB24, AB25, AB26, AC1, AC2, AC4, AC7, AC13, AC20, AC25, AC26, AD1, AD3, AD4, AD13, AD20, AD23, AD24, AD26, AE2, AE3, AE4, AE23, AE24, AE25, AF1, AF2, AF3, AF14, AF22, AF23, AF24, AF25, AF26 PWR Ground VDD2 AC5 NC Do not connect VSS2 AD5 NC Do not connect VDDS AC14, AD14, AE14 PWR 1.8-V supply VDDSHV A13, B13, C13, D13, G4, G23, K24, L3, N24, P3, T3, U24, Y4, AC22, AD7, AE20 PWR 3.3-V supply VDDA1 AD19 PWR 1.2-V supply (requires filtering) VSSA1 AF20 PWR Ground (requires filtering) VDDA2 B10 PWR 1.2-V supply (requires filtering) VSSA2 A10 PWR Ground (requires filtering) VPP1 H24, J26 PWR 1.2-V supply VPP2 T2, U1 PWR 1.2-V supply DPDIREF AD22 PWR DPD bias 1 kΩ to VSS DPDVREF AE22 PWR DPD bias to VDD DACREFP AC12 PWR DAC bias 50-Ω to VSS DACREFN AD12 PWR DAC bias 50-Ω to VDDS ADCIREF C17 PWR ADC bias 1 kΩ to VSS ADCVREF D17 PWR ADC bias to VDD BASEBAND INPUT BB[15:0] A8, D7, C7, B7, A7, D6, C6, B6, A6, D5, C5, B5, A5, C4, B4, A4 I Baseband input signal BBCLK C8 I Baseband input clock BBFR B8 I Baseband frame for sample and channel timing MFIO[19:18] R26, P24 I LSBs for 18-bit baseband input signal [-2, -1] I Chip reset (active-low .Required.) MISCELLANEOUS RESETB AC23 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5325 7 GC5325 SLWS215 – JANUARY 2009 .............................................................................................................................................................................................. www.ti.com Table 1. TERMINAL FUNCTIONS (continued) TERMINAL NAME I/O NO. DESCRIPTION SYNCA C9 I Programmable general-purpose sync SYNCB B9 I Programmable general-purpose sync SYNCC A9 I Programmable general-purpose sync SYNCD AE21 I Programmable general-purpose sync SYNCDC AF21 I Complementary of SYNCD SYNCOUT D9 O Programmable general-purpose sync output DPDCLK AC21 I Clock to DPD DPDCLKC AD21 I Complementary clock to DPD TESTMODE AF4 I Tie to ground JTAG INTERFACE TCK AF6 I JTAG clock TDI AE6 I JTAG data in TDO AF5 O JTAG data out TRSTB AE7 I JTAG reset (active-low); pull down if JTAG is not used. TMS AF7 I JTAG mode select TX[37:0] AC8, AD8, AE8, AF8, AC9, AD9, AE9, AF9, AC10, AD10, AE10, AF10, AC11, AD11, AE11, AF11, AE12, AF12, AE13, AF13, AF15, AE15, AD15, AC15, AF16, AE16, AD16, AC16, AF17, AE17, AD17, AC17, AF18, AE18, AD18, AC18, AF19, AE19 O Transmit to DAC(s) FB[35:0] A11, A15, A18, A21, I Feedback from ADC(s) NC Y26, W24, W25, W26, V24, V25, V26, U25, U26, T24, T25, T26, R24, R25, P25, P26, N25, N26, M24, M25, M26, L24, L25, L26, K25, K26, J24, J25, H25, H26, D22, C22 – No connect SIGNALS (See mode selection guide for pin assignment) B11, C11, B15, C15, B18, C18, B21, C21, D11, A12, B12, C12, D12, A14, B14, D15, A16, B16, C16, D16, A17, B17, D18, A19, B19, A20, B20, C20, D20, D21, A22, B22 10 W VDD1 VDDA1 or VDDA2 0.01 mF 1 mF 10 W VSS1 VSSA1 or VSSA2 S0315-01 Figure 1. GC5325 PLL Power Supply Filter The two PLLs require an analog supply. These can be generated by filtering the core digital supply (Vdd). A representative filter is shown in Figure 1. The two PLLs should have separate filters and be located as close as reasonable to their respective pins (especially the bypass capacitors). The ferrite beads should be series 50R (similar to Murata P/N: BLM31P500SPT Description: IND FB BLM31P500SPT 50R 1206). In particular, supply VDDA1 must be less than or equal to VDD1 when VDD1 is at the low end of the required range. The series resistor assures this condition is met. 8 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5325 GC5325 www.ti.com .............................................................................................................................................................................................. SLWS215 – JANUARY 2009 Table 2. GC5325 TX Interface Options PIN FUNCTION PIN NAME I/O DESCRIPTION DAC[15:0]P TX10, TX6, TX2, TX0, TX4, TX8, TX12, TX16, TX23, TX27, TX31, TX35, TX32, TX36, TX29, TX25 O DAC positive output DAC[15:0]N TX11, TX7, TX3, TX1, TX5, TX9, TX13, TX17, TX22, TX26, TX30, TX34, TX33, TX37, TX28, TX24 O DAC negative output DACCLK TX21 O Clock to DAC DACCLKC TX20 O Complementary clock to DAC DACSYNCP TX14 O Positive output data sync DACSYNCN TX15 O Negative output data sync TX (Single-Channel HSTL) Table 3. GC5325 FB Interface Options PIN FUNCTION PIN NAME I/O DESCRIPTION Feedback (Single-Channel SDR LVDS or DDR LVDS) ADC[15:0]P FB2, FB4, FB6, FB8, FB10, FB12, FB14, FB16, FB20, FB22, FB24, FB26, FB28, FB30, FB32, FB34 I ADC positive feedback from PA output ADC[15:0]N FB3, FB5, FB7, FB9, FB11, FB13, FB15, FB17, FB21, FB23, FB25, FB27, FB29, FB31, FB33, FB35 I ADC negative feedback from PA output ADCCLK FB0 I Clock from ADC ADCLKC FB1 I Complementary clock from ADC Feedback (Single- or Dual-Channel DDR LVDS) ADCA[7:0]P FB2, FB4, FB6, FB8, FB10, FB12, FB14, FB16 I ADC-A positive feedback from PA output ADCA[7:0]N FB3, FB5, FB7, FB9, FB11, FB13, FB15, FB17 I ADC-A negative feedback from PA output ADCACLK FB0 I Clock from ADC-A ADCACLKC FB1 I Complementary clock from ADC-A ADCB[7:0]P FB20, FB22, FB24, FB26, FB28, FB30, FB32, FB34 I ADC-B positive feedback from PA output ADCB[7:0]N FB21, FB23, FB25, FB27, FB29, FB31, FB33, FB35 I ADC-B negative feedback from PA output ADCBCLK FB18 I Clock from ADC-B ADCBCLKC FB19 I Complementary clock from ADC-B MPU Interface Guidelines The following section describes the hardware interface between the recommended microprocessor, external memory, and the GC5325. Users may select a microprocessor that meets their specific system requirements. Although the hardware can support multiple options, the recommended TMS320C6727 DSP is also fully supported with host control and adaptation software. Figure 2 illustrates the hardware interface between the DSP to GC5325 and SDRAM. The external memory is required to accommodate the computational efforts of the adaptation algorithm. Although the system evaluation kit suggests dual parallel 64-Mb/PC133 (128-Mb) memory modules provided by Samsung (K4S641632H-TC(L)75), other memory alternatives are available. The processing speed or convergence time of the adaptation algorithm is not strictly limited by the external memory speed rating. The use of an external inverter, with minimal propagation delay, is required for OEB of the GC5325; this device is necessary when using a TMS320C6727 DSP. Additional documentation for the hardware interface is available in the Hardware Designer’s Resource Guide application report (SPRAA87) and TMS320C672x DSP External Memory Interface (EMIF) user's guide (SPRU711). Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5325 9 GC5325 SLWS215 – JANUARY 2009 .............................................................................................................................................................................................. www.ti.com C6727 DSP Asynchronous Mode EM_D[31:0] UPDATA[15:0] EM_A[12:0] UPADDR[9:1] EM_BA[1:0] UPADDR[0] EM_CS[2]B CEB EM_RWB OEB EM_WEB WRB EM_OEB RDB AXRO[7] INTERRUPT GC5325 EM_CS[0]B EM_WE_DQM[3:0]B 1 DQ[31:16] / DQ[15:0] EM_CLK A[11:0] EM_CKE CSB EM_RASB DQM[3:0] EM_CASB BA[1:0] CLK SDRAM 1M ´ 16 ´ 4 (64Mb) ´ 2 CKE RASB CASB WEB B0280-02 NOTE: Dual SDRAM modules are used, upper and lower EMIF data lines are split to access each respective memory module. Figure 2. DSP to GC5325/SDRAM Interface Specifications In a typical implementation, the system configuration software resides locally (in nonvolatile memory) to ensure proper operation at power up. The adaptation algorithm should also reside in the same location; at power up, the host should transfer/load the software from the nonvolatile memory (FLASH) to the 'C6727 DSP. The size of the software required to support the GC5325 and 'C6727 should be no more than 128 Mb (16 MB); however, this allocation is subject to change pending algorithm improvements. The suggested host-to-DSP interface is through the UHPI port. See Chapter 0. The port can be configured into multiple modes of data transfer; the Multiplexed Host Address/Data Dual Halfword Mode is suggested for this application. Additional specifications and documents for the TMS320C6727 DSP are available from Texas Instruments at: http://focus.ti.com/docs/prod/folders/print/tms320c6727b.html. Typical Baseband Interface The GC5325 baseband interface receives time-interleaved I and Q data for each channel over the 16- or 18-bit input bus. The BB[15..0] bus is the 16-bit interface or the top 16 bits of the 18-bit interface. The frame strobe BBFS signal is used to identify the first channel I data. The data is input in channel order, I then Q. The baseband clock is used to register the interleaved IQ data and frame strobe. The hardware sync signals SyncA, SyncB, and SyncC are used to time-align internal GC5325 operations. A 0-to-1 transition clocked by BBClock is an active sync signal. 10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5325 GC5325 www.ti.com .............................................................................................................................................................................................. SLWS215 – JANUARY 2009 Customer Baseband-Data Processor GC5325 FRAME STROBE BBFR BASEBAND DATA[15..0] BASEBAND DATA[–1..–2] BB[15..0] MFIO[19..18] SYNC-HW1 SYNC A SYNC-HW2 SYNC B SYNC-HW3 SYNC C BASEBAND CLOCK BB CLK B0292-02 Figure 3. Typical Baseband Interface GENERAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS VDD, VDDA Core supply voltage VDDS Digital supply voltage for TX VDDSHV Digital supply voltage VIN Input voltage (under/overshoot) Tstg VALUE UNIT –0.3 to 1.32 V –0.3 to 2 V –0.3 to 3.6 V –0.5 to VDDSHV + 0.5 V Clamp current for an input/output –20 to 20 mA Storage temperature –65 to 150 °C 300 °C 260 ＝C Lead soldering temperature, 10 seconds ESD Classification Class 2 (Required 2-kV HBM, 500-V CDM) (Passed 2.5-kV HBM, 500-V CDM, 200-V MM) Moisture sensitivity Class 3 (1 week floor life at 30°C/60% H) Reflow conditions JEDEC standard Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5325 11 GC5325 SLWS215 – JANUARY 2009 .............................................................................................................................................................................................. www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) VDD, VDDA2, VPP Core supply voltages. Note VDDA2 ≤ VDD See (1) MIN TYP MAX UNIT 1.14 1.2 1.26 V VDDA1 Analog supply for DPD PLL 1 1.1 VDD V VDDS Digital supply voltage for TX 1.71 1.8 1.89 V VDDSHV Digital supply voltage 3.15 3.3 3.45 V 3 A 0.25 A 0.3 A 85 °C 105 °C IDD, IDDA1, IDDA2, Combined supply current for Vdd, Vdda1, IPP Vdda2, and VPP IDDS Digital supply current for TX IDDSHV Digital supply current TC Case temperature See (2) TJ Junction temperature See (3) (1) (2) (3) -40 30 VDDA1 must be less than VDD1 when VDD1 is low. See recommended filtering circuit in Figure 1. Maximum observed current on VDDA1 is 8 mA. Chip specifications in are production tested to 90°C case temperature. QA tests are performed at 85°C. Thermal management may be required for full-rate operation. Sustained operation at elevated temperatures reduces long-term reliability. Lifetime calculations based on maximum junction temperature of 105°C. THERMAL CHARACTERISTICS PARAMETER 352 BGA at 4 W UNITS 15 °C/W Theta junction to ambient (1 m/s) 11.8 °C/W RθJC Thermal resistance, junction-to-case 0.92 °C/W RθJB Thermal resistance, junction-to-board 5.3 °C/W RθJA Thermal resistance, junction-to-ambient (still air) RθJMA1 12 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5325 GC5325 www.ti.com .............................................................................................................................................................................................. SLWS215 – JANUARY 2009 GENERAL ELECTRICAL CHARACTERISTICS Describes the electrical characteristics for the baseband interface, multifunction I/O (MFIO), DPD clock and fast sync, MPU and JTAG interfaces over recommended operating conditions. Device is production tested at 90＝C for the given specification and characterized at –40＝C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CMOS INTERFACE VIL CMOS voltage input, low VIH CMOS voltage input, high 0.8 V 2 VDDSHV V VOL CMOS voltage output, low IOL = 2 mA VOH CMOS voltage output, high 0.5 V IOH = –2 mA 2.4 VDDSHV |IPU| V Pullup current VIN = 0 V 40 200 µA |IIN| Leakage current VIN = 0 or VIN = VDDSHV 5 µA 100 DAC INTERFACE (DAC P/N[15:0]) VO(diff) Output differential swing, | VO(diff) | = | VOH – VOL | (1) 250 mV V(COMM) Common mode voltage, (VOH + VOL)/2 (1) 1000 mV LVDS INTERFACE (FB[35:0], DPDCLK/C, SYNCD/C) Vi Input voltage range Vi(diff) Input differential voltage, |Vpos – Vneg| RIN Input differential impedance 0 0 < Vi < 2000 mV 1000 mV < Vi < 1400 mV, FB[35:0] only 2000 250 mV 90 80 mV 120 Ω 2.2 A POWER SUPPLY Idyn (1) (2) Core current See (2) HSTL output levels are measured at 675 Mb/s delay and with 100-Ω load from P to N. Drive strength set to 0x360. Contact TI for operations above 675 Mb/s. Operating at 280 MHz core, 840 TX port, maximum filtering, nominal supplies Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5325 13 GC5325 SLWS215 – JANUARY 2009 .............................................................................................................................................................................................. www.ti.com GENERAL SWITCHING CHARACTERISTICS Describes the electrical characteristics for the baseband interface, MFIO, Fast Sync, and MPU interfaces over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT 25 140 MHz BASEBAND INTERFACE fCLK(BB) Baseband input clock frequency tsu(BB) Input data setup time before BBCLK↑ BB[15:0], BBFR, SYNCA, SYNCB, and SYNCC; MFIO18/19 th(BB) Input data hold time after BBCLK↑ BB[15:0], BBFR, SYNCA, SYNCB, and SYNCC; MFIO18/19 th(SYNCA, -B, -C) Input data hold time after BBCLK↑ Valid for SYNCA, SYNCB, and SYNCC DutyCLK(BB) Duty cycle tjCLK(BB) Baseband input clock cycle-to-cycle jitter (1) (1) 1.3 ns 1.5 ns 2 ns 30% 70% –2.5% 2.5% Percent of baseband PLL clock period. The baseband PLL clock is typically 2×–4× the baseband clock frequency. 1/fCLK(BB) BBCLK I(ch = 1, t = 1) BB[15:0] tsu(BB) Q(ch = 1, t = 1) Q(ch = N, t = 1) I(ch = 1, t = 2) th(BB) BBFR T0284-01 Figure 4. Baseband Timing Specifications (ex. Four Interleaved I/Q Channels) 14 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5325 GC5325 www.ti.com .............................................................................................................................................................................................. SLWS215 – JANUARY 2009 Table 12. DPD CLOCK AND FAST SYNC SWITCHING CHARACTERISTICS PARAMETER TEST CONDITIONS MIN MAX UNIT MHz fCLK(DPD) DPD input clock frequency 100 280 DutyCLK(DPD) DPD input clock duty cycle 30% 70% th(SYNCD) Input hold time after DPDCLK↑ tsu(SYNCD) Input setup time after DPDCLK↑ th(SYNCA, -B, -C) Input hold time after DPDCLK↑ tsu(SYNCA, -B, -C) Input setup time after DPDCLK↑ tjCLK(DPD) DPD clock cycle-to-cycle jitter (1) See (1) 0.2 ns (1) 0.4 ns 2 ns 0.4 ns See –2.5% 2.5% SYNCD is the preferred sync for DPD clock and clock domain. DPDCLK DPDCLKC SYNCDC SYNCD tsu(SYNCD) th(SYNCD) SYNCA SYNCB SYNCC tsu(SYNCA, -B, -C) th(SYNCA, -B, -C) T0286-01 Figure 5. DPD Clock and Fast Sync Timing Specifications Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5325 15 GC5325 SLWS215 – JANUARY 2009 .............................................................................................................................................................................................. www.ti.com MPU SWITCHING CHARACTERISTICS (READ) PARAMETER TEST CONDITIONS MIN MAX UNIT tsu(AD) ADDR setup time to RDB↓ WRB is HIGH. 5 ns tsu(CEB) CEB setup time to RDB↓ WRB is HIGH. 7 ns tsu(OEB) OEB setup time to RDB↓ WRB is HIGH. 2 ns td(RD) DATA valid time after RDB↓ WRB is HIGH. th(RD) ADDR hold time to RDB↑ WRB is HIGH. 14 2 OEB, CEB hold time to RDB↑ ns 0 OEB hold time to RDB↑ 2 tHIGH(RD) Time RDB must remain HIGH between READs. WRB is HIGH (1). tZ(RD) DATA goes high-impedance after OEB↑ or RDB↑. WRB is HIGH (1). (1) ns 7 ns 7 ns Controlled by design and process and not directly tested RDB tHIGH(RD) WRB th(OEB) tsu(OEB) OEB tsu(CEB) CEB tsu(AD) ADDR DATA 3-State td(RD) tZ(RD) th(RD) T0287-01 Figure 6. MPU READ Timing Specifications 16 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5325 GC5325 www.ti.com .............................................................................................................................................................................................. SLWS215 – JANUARY 2009 MPU SWITCHING CHARACTERISTICS (WRITE) PARAMETER TEST CONDITIONS DATA and ADDR setup time to WRB↓ tsu(WR) MAX UNIT 5 CEB setup time to WRB↓ OEB and RDB are HIGH. OEB setup time to WRB↓ th(WR) MIN 7 ns 2 DATA and ADDR hold time after WRB↑ OEB and RDB are HIGH. OEB and CEB hold time after WRB↑ 2 ns 0 tlow(WR) Time WRB and CEB must remain simultaneously LOW OEB and RDB are HIGH. 15 ns thigh(WR) Time CEB or WRB must remain HIGH between WRITEs. OEB and RDB are HIGH. 10 ns RDB tlow(WR) thigh(WR) WRB OEB th(WR) tsu(WR) CEB ADDR DATA T0288-01 Figure 7. MPU WRITE Timing Specifications Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5325 17 GC5325 SLWS215 – JANUARY 2009 .............................................................................................................................................................................................. www.ti.com JTAG SWITCHING CHARACTERISTICS PARAMETER TEST CONDITIONS MIN MAX UNIT 50 MHz fTCK JTAG clock frequency tp(TCKL) JTAG clock low period 10 ns tp(TCKH) JTAG clock high period 10 ns tsu(TDI) Input data setup time before TCK↑ Valid for TDI and TMS 1 ns th(TDI) Input data hold time after TCK↑ Valid for TDI and TMS 6 td(TDO) Output data delay from TCK↓ ns 8 ns 1/fTCK TCK tp(TCKH) tp(TCKL) TDI tsu(TDI) th(TDI) TDO td(TDO) T0289-01 Figure 8. JTAG Timing Specifications ELECTRICAL CHARACTERISTICS TX SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER HSTL MODE – DDR fCLK(DAC) (1) TEST CONDITIONS MIN TYP MAX UNIT 420 MHz ex. DAC5682 DAC output clock frequency RL = 100 Ω (1) Because the output clock is DDR, this represents 840 MSPS real or 420 MSPS complex. 1/fCLK(DAC) DACCLKC DACCLK DAC[15:0]P I Q I DAC[15:0]N T0290-02 Figure 9. TX Timing Specifications (HSTL – DDR) 18 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5325 GC5325 www.ti.com .............................................................................................................................................................................................. SLWS215 – JANUARY 2009 LVDS SWITCHING CHARACTERISTICS Over recommended operating conditions (unless otherwise noted). The following table uses a shorthand nomenclature, NxM. N means the number of differential pairs used to transmit data from one ADC and M means the number of bits sent serially down each LVDS pair. Thus, 8x2 means 8 LVDS pairs each containing 2 bits of information sent serially. PARAMETER 16x1 SDR LVDS MODE fCLK(ADC) tsu(ADC[#]P) th(ADC[#]P) TEST CONDITIONS TYP MAX UNIT 280 MHz ex. ADS5444 ADC interface clock frequency Input data setup time before CLK↑ Input data hold time after CLK↑ 16x1 DDR LVDS MODE MIN See (1) See (1) (2) 300 ps See (1) (2) 600 ps ex. ADS5463 fCLK(ADC) ADC interface clock frequency See (1) tsu(ADC[#]P) Input data setup time before CLK↑↓ See (1) (2) 100 ps See (1) (2) 1200 ps See (1) 430 260 th(ADC[#]P) Input data hold time after CLK↑↓ 8x2 DDR LVDS MODE fCLK(ADCA) 140 MHz ex. ADS5545 ADCA interface clock frequency 280 MHz tsu(ADCA[#/2]P) Input data setup time before CLK↑↓ See (1) (3) th(ADCA[#/2]P) Input data hold time after CLK↑↓ See (1) (3) fCLK(ADCB) ADCB interface clock frequency See (1) tsu(ADCB[#/2]P) Input data setup time before CLK↑↓ See (1) (4) 800 ps th(ADCB[#/2]P) Input data hold time after CLK↑↓ See (1) (4) 400 ps (1) (2) (3) (4) . For port A . For port A ps ps 280 . For port B . For port B MHz Specifications are limited by GC5325 performance and may exceed the example ADC capabilities for the given interface. Setup and hold measured for ADC[15:0]P, ADC[15:0]N valid for (VOD > 250 mV) to/from ADCCLK and ADCCLKC clock crossing (VOD = 0). Setup and hold measured for ADCA[7:0]P, ADCA[7:0]N valid for (VOD > 250 mV) to/from ADCACLK and ADCACLKC clock crossing (VOD = 0). Setup and hold measured for ADCB[7:0]P, ADCB[7:0]N valid for (VOD > 250 mV) to/from ADCBCLK and ADCBCLKC clock crossing (VOD = 0). 1/fCLK(ADC) CLK CLKC ADC[15:0]P ADC[15:0]N tsu(ADC[#]P) th(ADC[#]P) T0286-02 Figure 10. LVDS Timing Specifications (16 × 1 SDR LVDS) 1/fCLK(ADC) CLK CLKC tsu(ADC[#]P) ADC[15:0]P ADC[15:0]N th(ADC[#]P) T0292-01 Figure 11. LVDS Timing Specifications (16 × 1 DDR LVDS) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5325 19 GC5325 SLWS215 – JANUARY 2009 .............................................................................................................................................................................................. www.ti.com 1/fCLK(ADCx) CLK CLKC ADC[# bits/2]P Even Bits Odd Bits Even Bits Odd Bits ADC[# bits/2]N tsu(ADCx[#/2]P) th(ADCx[#/2]P) t=N t=N+1 T0293-01 Figure 12. LVDS Timing Specifications (8 × 2 DDR LVDS) APPENDIX A See the TMS320C672x DSP Universal Host Port Interface (UHPI) reference guide (SPRU719). ADDR/DATA BUS (16-Bit) UHPI_HD[15:0] DATA READY UHPI_HRDYB HALFWORD STROBE UHPI_HD[16]/HHWIL CHIP SELECT Host Processor BYTE ENABLE CONTROL INPUT UHPI_HCS (1) UHPI_HBE[1:0]B (2) UHPI_HCNTL[1:0] FUNDAMENTAL STROBE C6727 DSP Asynchronous Mode UHPI_HCSB/UHPI_HDS[2:1]B READ/WRITE CONTROL UHPI_HRWB DSP INTERRUPT AMUTE2/HINTB HOST INTERRUPT AFSR2 B0281-01 (1) Byte enables are aplicable to single HPID accesses. All byte enables must be active during HPID with post-increment (burst) UHPI accesses. (2) Control inputs selecting between HPIA, HPIC, HPID, and HPID with post-increment accesses. Figure 13. Host-to-DSP Interface (Multiplexed Host Address/Data Dual Halfword) GLOSSARY OF TERMS 3G Third generation (refers to next-generation wideband cellular systems that use CDMA) 3GPP Third generation partnership project (W-CDMA specification, www.3gpp.org) 3GPP2 Third generation partnership project 2 (cdma2000 specification, www.3gpp2.org) ACLR Adjacent channel leakage ratio (measure of out-of-band energy from one CDMA carrier) ACPR Adjacent channel power ratio ADC Analog-to-digital converter BW Bandwidth 20 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5325 GC5325 www.ti.com .............................................................................................................................................................................................. SLWS215 – JANUARY 2009 CCDF Complementary cumulative distribution function CDMA Code division multiple access (spread spectrum) CEVM Composite error vector magnitude CFR Crest factor reduction CMOS Complementary metal oxide semiconductor DAC Digital-to-analog converter dB Decibels dBm Decibels relative to 1 mW (30 dBm = 1 W) DDR Dual data rate (ADC output format) DSP Digital signal processing or digital signal processor EVM Error vector magnitude FIR Finite impulse response (type of digital filter) I/Q In-phase and quadrature (signal representation) IF Intermediate frequency IIR Infinite impulse response (type of digital filter) JTAG Joint Test Action Group (chip debug and test standard 1149.1) LO Local oscillator LSB Least-significant bit Mb Megabits (divide by 8 for megabytes MB) MSB Most-significant bit MSPS Megasamples per second (1×106 samples/s) PA Power amplifier PAR Peak-to-average ratio PCDE Peak code domain error PDC Peak detection and cancellation (stage) PDF Probability density function RF Radio frequency RMS Root mean square (method to quantify error) SDR Single data rate (ADC output format) SEM Spectrum emission mask SNR Signal-to-noise ratio (usually measured in dB or dBm) UMTS Universal mobile telephone service W-CDMA Wideband code division multiple access (synonymous with 3GPP) WiBRO Wireless broadband (Korean initiative IEEE 802.16e) WiMAX Worldwide Interoperability of Microwave Access (IEEE 802.16e) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): GC5325 21 PACKAGE OPTION ADDENDUM www.ti.com 3-Feb-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing GC5325IZND ACTIVE BGA ZND Pins Package Eco Plan (2) Qty 352 40 Pb-Free (RoHS) Lead/Ball Finish SNAGCU MSL Peak Temp (3) Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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