2.3 GHz to 2.4 GHz WiMAX Power Amplifier ADL5570 Preliminary Technical Data FUNCTIONAL BLOCK DIAGRAM FEATURES Fixed gain of 29 dB Operation from 2.3 GHz to 2.4 GHz EVM ≤3% with 16 QAM OFDMA @ POUT = 25 dBm [3.5V] and @ POUT = 27.5 dBm [5V] Input internally matched to 50 Ω Power supply: 3.2 V to 5.5 V Quiescent current 130 mA in high power mode 70 mA in low power mode PAE: >20% Multiple operating modes to reduce battery drain Low power mode: 100 mA (Operating) Standby mode: 10 mA Sleep mode: < 1 μA APPLICATIONS VCC VCC1 RFIN STBY IM1 1st stage Bias_1 IM2 2nd stage Bias_2 VCC VCC2 IM3 3rd stage RFOUT OM Bias_3 VREG CFLT MODE Figure 1.AD5570 Block Diagram WiMAX/WiBro Mobile Terminals and CPEs Good performance from 2.5Ghz to 2.7Ghz - See Page 7 GENERAL DESCRIPTION The ADL5570 is a high linearity 2.3 GHz to 2.4 GHz power amplifier designed for WiMAX terminals and CPEs using TDD operation at a duty cycle of 50% or lower. With a gain of 29 dB and an output compression point of 31 dBm , it can operate at an output power level up to 26 dBm while maintaining an EVM of ≤3% with a supply voltage of 3.5V. PAE is greater than 20% at POUT = 25 dBm with a 3.5V supply voltage. The ADL5570 RF input is matched on chip and provides an input return loss of less than −10 dB. The open-collector output is externally matched with strip-line and external shunt capacitance. The ADL5570 operates over a supply voltage range from 3.2 V to 5.5 V with a supply current of 400mA Burst RMS when delivering 25 dBm (3.5 V supply). A low power mode is also available for operation at power levels ≤10 dBm with optimized operating and quiescent currents of 100 and 70 mA, respectively. A Standby mode is available which reduces the quiescent current to 10 mA: useful when a TDD terminal is receiving data. The ADL5570 is fabricated in a GaAs HBT process and is packaged in a 4mm x 4mm 16-Lead Pb-free RoHS compliant LFCSP that uses an exposed paddle for excellent thermal impedance. It operates from −40°C to +85°C. Rev. PrG Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. ADL5570 Preliminary Technical Data TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions..............................5 Applications....................................................................................... 1 Typical Performance Characteristics ..............................................6 Functional Block Diagram .............................................................. 1 APPLICATIONS ...............................................................................7 General Description ......................................................................... 1 2.5 GHz to 2.7 Ghz Peformance ..................................................7 Revision History ............................................................................... 2 Evaluation Board ...............................................................................8 Target Specifications - VCC = 3.5 V .............................................. 3 Outline Dimensions ....................................................................... 10 Target Specifications - Vcc = 5 V.................................................... 4 REVISION HISTORY 3/07—Rev. PrF: Preliminary Version Rev. PrG| Page 2 of 10 Preliminary Technical Data ADL5570 TARGET SPECIFICATIONS - VCC = 3.5 V T = 25°C, 1024 FFT, 16 QAM OFDMA modulated carrier, 10 MHz Channel BW, ZL = 50 Ω, MODE = 0 V, STBY = 0 V, VREG = 2.85 V, 33% duty cycle, unless otherwise noted. Table 1. Parameter Frequency Range Linear Output Power Gain vs. Frequency vs. Temp vs. Supply OP1dB EVM Input Return Loss Spectral Mask @ 25dBm Output Power Harmonic Distortion Power Supply Interface Supply Current PAE Standby Mode Sleep Mode Turn On/Off Time VSWR Survivability Conditions See table 5 for tuning details Min 2.3 MODE = 0 V, EVM ≤ 3% MODE = 2.5 V, EVM ≤ 3% ±5 MHz −40°C ≤ TA ≤ +85°C 3.2 V to 4.2 V Unmodulated input POUT = 25 dBm ±5 MHz carrier offset ±6 MHz carrier offset ±10.5 MHz carrier offset ±20 MHz carrier offset VCC = 3.5 V POUT = 25 dBm, MODE= 0 V. POUT = 12 dBm, MODE= 2.5 V. POUT = 25 dBm, MODE= 0 V VREG = 2.85 V, STBY = 2.5 V VREG = 0 V 10:1 Rev. PrG | Page 3 of 10 Typ Max 2.4 25 10 29 ±0.3 ±0.5 ±1 31 3 10 Unit GHz dBm dBm dB dB dB dB dBm % rms dB 35 37 41 51 36 dBc dBc dBc dBc dBc 250 100 >20 10 10 1 mA mA % mA μA μs ADL5570 Preliminary Technical Data TARGET SPECIFICATIONS - VCC = 5 V T = 25°C, 1024 FFT, 16 QAM OFDMA modulated carrier, 10 MHz Channel BW, ZL = 50 Ω, MODE = 0 V, STBY = 0 V, VREG = 2.85 V, 33% duty cycle, unless otherwise noted. Table 2. Parameter Frequency Range Linear Output Power Gain vs. Frequency vs. Temp vs. Supply OP1dB EVM Input Return Loss Spectral Mask @ 25dBm Output Power Harmonic Distortion Power Supply Interface Supply Current PAE Standby Mode Sleep Mode Turn On/Off Time VSWR Survivability Conditions See table 5 for tuning details Min 2.3 ±5MHz carrier offset 27.5 10 28 ±0.3 ±0.5 ±1 32 3 10 38 Unit GHz dBm dBm dB dB dB dB dBm % rms dB dBc ±6 MHz carrier offset ±10.5 MHz carrier offset ±20 MHz carrier offset 39 43 49 dBc dBc dBc 36 dBc 300 115 16 10 10 1 mA mA % mA μA μs MODE = 0 V, EVM ≤ 3% MODE = 2.5 V, EVM ≤ 3 % ±5 MHz −40°C ≤ TA ≤ +85°C 4.5 V to 5.5 V Unmodulated input POUT = 27.5 dBm VCC = 5 V POUT = 27.5 dBm, MODE = 0 V POUT = 13 dBm, MODE = 2.5 V POUT = 27.5 dBm, MODE = 0 V VREG = 2.85 V, STBY = 2.5 V VREG = 0 V 10:1 Rev. PrG| Page 4 of 10 Typ Max 2.4 Preliminary Technical Data ADL5570 2 VCC2 1 NC 15 RFOUT 14 RFOUT 13 NC xxxx-xx CFLT 9 VREG 8 TOP VIEW (Not to Scale) 16 NC NC 12 GND 7 ADL5570 NC 11 RFIN 6 PIN 1 INDICATOR MODE 10 VCC1 5 3 GND 4 STBY PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. ADL5570 Pin Configuration Table 3. Pin Function Descriptions Pin No. 5 6 8 Mnemonic VCC1 RFIN VREG 9 CFLT 10 MODE 14, 15 RFOUT 2 4 VCC2 STBY 1, 11 to 13, 16 7 N/C GND Exposed Paddle Description Connect to Power Supply. Matched RF Input. When VREG is low, the device goes into sleep mode, reducing supply current to 1 uA. When VREG is high (2.85 V), the device operates in its normal transmit mode. When high, VREG draws a bias current of approximately 10 mA. A Ground Referenced Capacitor. It should be connected to this node to reduce bias line noise (see figure 8). Switches Between High Power and Low Power Modes. When MODE is low (0 V), the device operates in high power mode. When MODE is high (2.5 V), the device operates in low power mode. Unmatched RF Output. These parallel outputs can be matched to 50 Ω using strip-line and shunt capacitance. The power supply voltage should be connected to these pins through a choke inductor. This power supply pin should be connected to the supply via a choke circuit (see Figure 8). When STBY is low (0 V), the device operates in transmit mode. When the radio is receiving data, STBY can be taken high (2.5 V), reducing supply current to 10 mA. No Connect. Do not connect these pins. Connected to Ground. The exposed paddle should be soldered down to a low impedance ground plane (use multiple vias (at least 9) to stitch together the ground planes) for optimum electrical and thermal performance. Table 4. Operating Modes 1 Mnemonic VREG MODE STBY 1 Normal Operation High Low Low Low Power Mode, POUT ≤ 10dBm High High Low X = don’t care. Rev. PrG | Page 5 of 10 Standby Mode High X High Sleep Mode Low X X ADL5570 Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, 1024 FFT, 16 QAM OFDMA modulated carrier, 10 MHz Channel BW, ZL = 50 Ω, MODE = 0 V, STBY = 0 V, VREG = 2.85 V, 33% duty cycle, unless otherwise noted. 0.8 31 0.7 30 0.6 29 0.5 28 GAIN (dB) BURST RM S CURRENT (A) Vcc=3.5V 0.4 0.3 Vcc=5V 27 26 25 0.2 24 0.1 23 2280 0 0 5 10 15 20 25 2300 2320 2340 30 2360 2380 2400 2420 FREQUENCY (Mhz) OUTPUT POWER (dBm) Figure 6. Gain vs. Frequency at PIN= −2 dBm Figure 3.Burst RMS Current vs. POUT, at 2.35 GHz, Vcc=3.5V 10 9 31 8 7 29 6 28 5 27 4 GAIN (dB) EVM (%) Vcc =3.5V 30 Vcc =3.5V 3 Vcc = 5V 2 Vcc =5V 26 25 24 23 1 22 0 0 5 10 15 20 25 21 30 0 OUTPUT POWER (dBm) 5 10 15 20 25 30 OUTPUT POWER (dBm) Figure 4. EVM vs. POUT at 2.35 GHz. Figure 7. Gain vs Output Power at 2.35 GHz 13 12 11 EVM (%) 2 VCC2 8 16 NC 15 RFOUT 14 RFOUT 13 NC 7 6 5 2400 Mhz 4 xxxx-xx CFLT 9 1 NC 4 STBY TOP VIEW (Not to Scale) 9 VREG 8 ADL5571 NC 12 GND 7 PIN 1 INDICATOR NC 11 RFIN 6 MODE 10 05352-002 IFOP VCC1 5 3 GND 10 TOP VIEW (Not to Scale) 2350 Mhz 3 2300 Mhz 2 1 0 0 5 10 15 20 25 OUTPUT POWER (dBm) Figure 5. WiMax Spectrum with FCC Spectral Mask limits applied at 2.35Ghz, Vcc=3.5V, Pout=25dBm. Rev. PrG | Page 6 of 10 Figure 8.EVM vs. Output Power at Vcc=3.5V 30 35 Preliminary Technical Data ADL5570 APPLICATIONS 2.5 GHZ TO 2.7 GHZ PEFORMANCE 10 30 9 29 8 28 7 27 G AIN (dB) E V M (% ) The ADL5570 is optimized for superior performance within the 2.3 GHz to 2.4 GHz frequency band. With a change in the external matching capacitor, C3, to 2.4pF, the ADL5570 shows good performance in the 2.5 GHz to 2.7 GHz frequency band. The EVM, Gain and RMS current performance data are shown in Figure 9 and Figure 10. 6 5 2700Mhz 4 24 22 2500Mhz 2 25 23 2600Mhz 3 26 21 1 20 2450 0 0 5 10 15 20 25 30 2500 2550 2600 2650 2700 2750 FREQUENCY (Mhz) OUTPUT POWER (dBm) Figure 9. EVM vs Output power Perfomance at Vcc=3.5V and 16QAM OFDMA Signal Rev. PrG | Page 7 of 10 Figure 10. Gain vs Frequency Performance at Vcc=3.5V and 16QAM OFDMA Signal ADL5570 Preliminary Technical Data EVALUATION BOARD Figure 11. Evaluation Board Layout The ADL5570 perfomance data were taken on a FR4 board layout. Care should be taken to ensure 50Ω impedance for all RF traces. For optimal performance in linearity, gain and efficiency, the output matching capacitor, C3, should be placed 30 mils from the edge of the package. Rev. PrG | Page 8 of 10 Preliminary Technical Data ADL5570 Table 5. Evaluation Board Configuration Options Component Vpos, Vpos1, GND TP1(STBY) TP2 (VREG) TP5(MODE) L3, C3, C4, Function Supply and Ground Connections Transmit/Standby Mode: When STBY is low (0 V), the device operates in transmit mode. When the radio is receiving data, STBY can be taken high (2.5 V), reducing supply current to 10 mA. Normal/Sleep Mode: When VREG is low, the device goes into sleep mode, reducing supply current to 10 uA. When VREG is high (2.85 V), the device operates in its normal transmit mode. When high, VREG draws a bias current of approximately 10 mA High/Low Power Mode: Switches between High Power and Low Power Modes. When Mode is low (0V), the device operates in High Power Mode. When Mode is high (MODE = 2.5 V), the device operates in Low Power Mode. Input Interface: (L3) matches the input to 50 ohms. Default Value W1 = Installed Not Applicable Output Interface: C4 provides dc blocking. C3 matches the output to 50 ohms. C4 = 39pF (Size 0402) C3 = 3.3pF (Size 0402) Not Applicable Not Applicable L3 = 2.2nH (Size 0402) (C3 value for 2.3 Ghz to 2.4Ghz operation) C2 C7, C8, C9, C10, C11, C12 L1, L2, C6, C5 Filter Interface: A ground referenced capacitor should be connected to this node to reduce bias line noise Power Supply Decoupling: The capacitors, C7, thru C12, are used for power supply decoupling. They should be placed as close as possible to the DUT. RF Trap: L1, C6 and L2, C5 form tank circuits and prevent RF from propagating on the dc supply lines Figure 12. Application Schematic Rev. PrG | Page 9 of 10 C2 = 2.2pF (Size 0402) C7 = 0.01μ F (Size 0402) C8 = 0.01μ F (Size 0402) C9 = 0.01μ F (Size 0402) C10 = 0.01μ F (Size 0402) C11 = 1μ F (Size 0402) C12 = 1μ F (Size 0402) L1 = 1nH (Size 0402) C6 = 3.6pF (Size 0402) L1 = 11nH (Size 0402) C5 = OPEN ADL5570 Preliminary Technical Data OUTLINE DIMENSIONS 4.00 BSC SQ PIN 1 INDICATOR 0.65 BSC TOP VIEW 12° MAX 3.75 BSC SQ 0.75 0.60 0.50 (BOTTOM VIEW) 13 12 9 8 16 PIN 1 INDICATOR 1 2.25 2.10 SQ 1.95 5 4 0.25 MIN 1.95 BSC 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 0.35 0.30 0.25 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VGGC Figure 13. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-16-4) Dimensions shown in millimeters ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06729-0-4/07(PrG) Rev. PrG | Page 10 of 10 021207-A 1.00 0.85 0.80 0.60 MAX 0.60 MAX