MAXIM MAX807M

19-0433; Rev 2; 1/02
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
____________________________Features
♦ Precision 4.675V (MAX807L) or 4.425V
(MAX807M), or 4.575V (MAX807N) Voltage
Monitoring
• Manual-reset input.
• Two-stage power-fail warning. A separate low-line
comparator compares VCC to a threshold 52mV above
the reset threshold. This low-line comparator is more
accurate than those in previous µP supervisors.
• Backup-battery switchover for CMOS RAM, real-time
clocks, µPs, or other low-power logic.
• Write protection of CMOS RAM or EEPROM.
• 2.275V threshold detector provides for power-fail
warning and low-battery detection, or monitors a
power supply other than +5V.
♦ MaxCap® and SuperCap® Compatible
♦ 200ms Power OK/Reset Time Delay
♦ RESET and RESET Outputs
♦ Independent Watchdog Timer
♦ 1µA Standby Current
♦ Power Switching
250mA in VCC Mode
20mA in Battery-Backup Mode
♦ On-Board Gating of Chip-Enable Signals;
2ns CE Gate Propagation Delay
♦ Voltage Monitor for Power Fail
♦ Backup-Battery Monitor
♦ Guaranteed RESET Valid to VCC = 1V
♦ ±1.5% Low-line Threshold Accuracy 52mV above
Reset Threshold
Pin Configuration
• BATT OK status flag indicates that the backup-battery
voltage is above +2.275V.
• Watchdog-fault output—asserted if the watchdog input
has not been toggled within a preset timeout period.
TOP VIEW
PFI 1
Applications
16 OUT
15 BATT OK
PFO 2
Computers
VCC 3
Controllers
WDI
Intelligent Instruments
14 BATT
MAX807
GND 5
Critical µP Power Monitoring
Portable/Battery-Powered Equipment
4
13 BATT ON
12 CE IN
MR
6
11 CE OUT
LOW LINE
7
10 WDO
RESET
8
9
RESET
DIP/SO/TSSOP
Ordering Information and Typical Operating Circuit appear at end of data sheet.
SuperCap is a registered trademark of Baknor Industries. MaxCap is a registered trademark of Cesiwid, Inc.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX807L/M/N
General Description
The MAX807 microprocessor (µP) supervisory circuit
reduces the complexity and number of components
needed to monitor power-supply and battery-control functions in µP systems. A 70µA supply current makes the
MAX807 ideal for use in portable equipment, while a 2ns
chip-enable propagation delay and 250mA output current
capability (20mA in battery-backup mode) make it suitable for larger, higher-performance equipment.
The MAX807 comes in 16-pin DIP, SO, and TSSOP packages, and provides the following functions:
• µP reset. The active-low RESET output is asserted during power-up, power-down, and brownout conditions,
and is guaranteed to be in the correct state for VCC
down to 1V.
• Active-high RESET output.
MAX807L/M/N
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
ABSOLUTE MAXIMUM RATINGS
Input Voltages (with respect to GND)
VCC ..........................................................................-0.3V to 6V
VBATT .......................................................................-0.3V to 6V
All Other Inputs......................................-0.3V to (VOUT + 0.3V)
Input Current
VCC Peak ...........................................................................1.0A
VCC Continuous .............................................................500mA
IBATT Peak......................................................................250mA
IBATT Continuous .............................................................50mA
GND .................................................................................50mA
All Other Inputs ................................................................50mA
Continuous Power Dissipation (TA = +70°C)
Plastic DIP (derate 10.53mW/°C above +70°C) ..........842mW
Wide SO (derate 9.52mW/°C above +70°C)................762mW
CERDIP (derate 10.00mW/°C above +70°C) ...............800mW
TSSOP (derate 6.70 mW/°C above +70°C) .................533mW
Operating Temperature Ranges
MAX807_C_E ......................................................0°C to +70°C
MAX807_E_E ...................................................-40°C to +85°C
MAX807_MJE ................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V CC = 4.60V to 5.5V for the MAX807L, V CC = 4.50V to 5.5V for the MAX807N, V CC = 4.35V to 5.5V for the MAX807M,
VBATT = 2.8V, VPFI = 0, TA = TMIN to TMAX. Typical values are tested with VCC = 5V and TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
Operating Voltage Range
VBATT, VCC (Note 1)
0
IOUT = 25mA
VOUT in Normal Operating
Mode
VCC to OUT On-Resistance
VOUT in Battery-Backup Mode
BATT to OUT On-Resistance
VCC = 4.5V
MAX
UNITS
5.5
V
VCC - 0.02
IOUT = 250mA,
VCC - 0.35 VCC - 0.22
MAX807C/E
V
IOUT = 250mA,
VCC - 0.45
MAX807M
VCC = 3V, VBATT = 2.8V, IOUT = 100mA
MAX807C/E
VCC = 4.5V,
IOUT = 250mA
MAX807M
VCC = 3V, IOUT = 100mA
VBATT = 4.5V, IOUT = 20mA, VCC = 0
VBATT = 2.8V, IOUT = 10mA, VCC = 0
VBATT = 2.0V, IOUT = 5mA, VCC = 0
VBATT = 4.5V, IOUT = 20mA
VBATT = 2.8V, IOUT = 10mA
VBATT = 2.0V, IOUT = 5mA
VCC - 0.25 VCC - 0.12
1.0
1.2
VBATT - 0.17
VBATT - 0.25 VBATT - 0.12
VBATT - 0.20 VBATT - 0.08
8.5
12
16
Supply Current in Normal
Operating Mode (excludes IOUT)
Supply Current in BatteryBackup Mode (excludes IOUT)
(Note 2)
VCC = 0, VBATT = 2.8V
BATT Standby Current (Note 3)
VBATT + 0.2V ≤ VCC
TA = +25°C
MAX807C/E
MAX807M
1.4
1.8
2.5
25
40
Ω
70
110
µA
0.4
1
5
50
µA
-0.1
0.1
TA = TMIN to
TMAX
-1.0
1.0
µA
Power up
Power down
VBATT = 2.8V
Battery-Switchover Hysteresis
BATT ON Output, Low Voltage
BATT ON Output, High Voltage
VRST (max), ISINK = 3.2mA
VCC = 0, ISOURCE = 0.1mA, VBATT = 2.8V
Ω
V
TA = +25°C
Battery-Switchover Threshold
2
TYP
2
VBATT + 0.05
VBATT
50
0.1
2.7
_______________________________________________________________________________________
V
0.4
mV
V
V
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
(V CC = 4.60V to 5.5V for the MAX807L, V CC = 4.50V to 5.5V for the MAX807N, V CC = 4.35V to 5.5V for the MAX807M,
VBATT = 2.8V, VPFI = 0, TA = TMIN to TMAX. Typical values are tested with VCC = 5V and TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
Sink current
Source current, VCC = 0, VBATT = 2.8V
RESET, LOW LINE, AND WATCHDOG TIMER
MAX807L
MAX807N
Reset Threshold
VRST
VCC rising and falling
MAX807M
Reset Threshold Hysteresis
LOW LINE to RESET
Threshold Voltage
VLR
VCC falling
LOW LINE Threshold,
VCC Rising
VLL
MAX807L
MAX807N
MAX807M
VCC to RESET Delay
tRP
Watchdog-Timeout Period
tWD
Minimum Watchdog Input
Pulse Width
ISC
RESET Output Voltage
ISC
LOW LINE Output Voltage
LOW LINE Output
Short-Circuit Current
ISC
WDO Output Voltage
WDO Output
Short-Circuit Current
WDI Threshold Voltage
(Note 4)
WDI Input Current
ISC
VIH
VIL
VIH
4.675
4.575
4.425
13
4.750
4.650
4.500
52
70
mV
4.73
4.63
4.48
4.81
4.71
4.56
V
µs
µs
140
200
280
ms
1.12
1.6
2.24
s
ns
VCC = 1V,
MAX807_C
0.3
VCC = 1.2V,
MAX807_E/M
0.3
VCC - 1.5
0.1
VCC - 0.1
60
1.6
mA
0.4
VCC - 1.5
60
15
0.4
28
20
V
mA
0.4
VCC - 1.5
35
20
V
mA
0.8
-10
16
V
mA
VCC - 1.5
-50
V
0.4
0.75 x VCC
Reset deasserted, WDI = 0
Reset deasserted, WDI = VCC
V
mV
100
ISINK = 3.2mA, VCC = 4.25V
ISOURCE = 0.1mA
Output sink current, VCC = 4.25V
Output source current
ISINK = 3.2mA
ISOURCE = 5mA
Output sink current
Output source current, VCC = 4.25V
ISINK = 3.2mA, VCC = 4.25V
ISOURCE = 5mA
Output sink current, VCC = 4.25V
Output source current
ISINK = 3.2mA
ISOURCE = 5mA
Output sink current
Output source current
UNITS
mA
24
VCC rising
ISINK = 50µA,
VBATT = 0, VCC falling
MAX
26
VIL = 0.8V, VIH = 0.75 x VCC
RESET Output Voltage
RESET Output
Short-Circuit Current
30
VCC falling at 1mV/µs
RESET Active-Timeout Period
RESET Output
Short-Circuit Current
4.600
4.500
4.350
VCC falling at 1mV/µs
VCC to LOW LINE Delay
TYP
70
5
BATT ON Output
Short-Circuit Current
50
V
µA
_______________________________________________________________________________________
3
MAX807L/M/N
ELECTRICAL CHARACTERISTICS (continued)
MAX807L/M/N
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
ELECTRICAL CHARACTERISTICS (continued)
(V CC = 4.60V to 5.5V for the MAX807L, V CC = 4.50V to 5.5V for the MAX807N, V CC = 4.35V to 5.5V for the MAX807M,
VBATT = 2.8V, VPFI = 0, TA = TMIN to TMAX. Typical values are tested with VCC = 5V and TA = +25°C, unless otherwise noted.)
PARAMETER
PFI Input Threshold
SYMBOL
VPFT
CONDITIONS
VPFI falling
VPFI rising
MIN
TYP
MAX
UNITS
2.20
2.22
2.265
2.285
20
±0.005
2.33
2.35
V
PFI Hysteresis
PFI Leakage Current
PFI to PFO Delay (Note 5)
±40
mV
nA
VOD = 30mV, VPFI falling
14
µs
CE IN Leakage Current
Disabled mode, MR = 0
±0.00002
±1
µA
CE IN to CE OUT Resistance
(Note 6)
Enabled mode, VCC = VRST (max)
75
150
Ω
CE OUT Short-Circuit Current
(RESET active)
VCC = 5V, disabled mode,
CE OUT = 0, MR = 0
17
CE IN to CE OUT
Propagation Delay (Note 7)
VCC = 5V, CLOAD = 50pF,
50Ω source impedance driver
2
CHIP-ENABLE GATING
CE OUT Output Voltage High
(RESET active)
Disabled mode, MR = 0
RESET to CE OUT Delay
VCC falling
VCC = 5V,
IOUT = 2mA
VCC = 0,
IOUT = 10µA
mA
8
ns
3.5
V
VBATT - 0.1
VBATT
28
µs
MANUAL RESET INPUT
MR Minimum Pulse Input
1
MR-to-RESET Propagation
Delay
MR Threshold
170
VIH
VIL
MR Pull-Up Current
BATT OK COMPARATOR
BATT OK Threshold
BATT OK Hysteresis
LOGIC OUTPUTS
µs
2.4
0.8
MR = 0
VBOK
Output Voltage
(PFO, BATT OK)
VOL
VOH
Output Short-Circuit Current
ISC
ns
ISINK = 3.2mA
ISOURCE = 5mA
Output sink current
Output source current
V
50
100
200
µA
2.200
2.265
20
2.350
V
mV
0.4
VCC - 1.5
35
20
V
mA
Note 1: Either VCC or VBATT can go to 0 if the other is greater than 2.0V.
Note 2: The supply current drawn by the MAX807 from the battery (excluding IOUT) typically goes to 15µA when (VBATT - 0.1V)
< VCC < VBATT. In most applications, this is a brief period as VCC falls through this region (see Typical Operating Characteristics).
Note 3: “+”= battery discharging current, “-”= battery charging current.
Note 4: WDI is internally connected to a voltage-divider between VCC and GND. If unconnected, WDI is driven to 1.8V (typical),
disabling the watchdog function.
Note 5: Overdrive (VOD) is measured from center of hysteresis band.
Note 6: The chip-enable resistance is tested with V CE IN = VCC/2, and I CE IN = 1mA.
Note 7: The chip-enable propagation delay is measured from the 50% point at CE IN to the 50% point at CE OUT.
4
_______________________________________________________________________________________
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
BATTERY SUPPLY CURRENT vs.
TEMPERATURE (BATTERY-BACKUP MODE)
76
74
72
70
68
66
64
MAX807-02
6
2.5
5
PROPAGATION DELAY (ns)
BATTERY SUPPLY CURRENT (µA)
78
VCC SUPPLY CURRENT (µA)
3.0
MAX807-01
80
CHIP-ENABLE PROPAGATION DELAY
vs. TEMPERATURE
MAX807-03
VCC SUPPLY CURRENT vs. TEMPERATURE
(NORMAL OPERATING MODE)
2.0
1.5
1.0
0.5
4
3
2
1
62
0
60
-60 -40 -20 0
-60 -40 -20 0
20 40 60 80 100 120 140
TEMPERATURE (°C)
TEMPERATURE (°C)
BATT-TO-OUT ON-RESISTANCE
vs. TEMPERATURE
VCC-TO-OUT ON-RESISTANCE
vs. TEMPERATURE
PFI THRESHOLD
vs. TEMPERATURE (VPFI FALLING)
25
VBATT = 2.0V
20
15
VBATT = 2.8V
10
VBATT = 4.5V
IOUT = 250mA
2.340
2.320
1.4
1.3
1.2
1.1
1.0
2.280
2.260
2.240
2.220
2.200
0.7
-60 -40 -20 0
2.300
0.9
0.8
5
MAX807-06
1.5
PFI THRESHOLD (V)
VCC-TO-OUT ON-RESISTANCE (Ω)
VCC = 0
IOUT = 10mA
MAX807-05
1.6
MAX807-04
-60 -40 -20 0
20 40 60 80 100 120 140
20 40 60 80 100 120 140
-60 -40 -20 0
20 40 60 80 100 120 140
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
RESET THRESHOLD
vs. TEMPERATURE
RESET TIMEOUT PERIOD
vs. TEMPERATURE (VCC RISING)
LOW LINE -TO-RESET THRESHOLD
vs. TEMPERATURE (VCC FALLING)
MAX807L
4.60
MAX807N
4.55
4.50
4.45
240
220
200
180
160
MAX807M
4.40
-60 -40 -20 0
20 40 60 80 100 120 140
TEMPERATURE (°C)
140
MAX807-09
260
RESET TIMEOUT PERIOD (ms)
4.65
80
LOW LINE-TO-RESET THRESHOLD (mV)
280
MAX807-07
4.70
MAX807-08
BATT-TO-OUT ON-RESISTANCE (Ω)
20 40 60 80 100 120 140
TEMPERATURE (°C)
30
RESET THRESHOLD (V)
0
-60 -40 -20 0
20 40 60 80 100 120 140
70
60
50
40
30
20
10
0
-60 -40 -20 0
20 40 60 80 100 120 140
TEMPERATURE (°C)
-60 -40 -20 0
20 40 60 80 100 120 140
TEMPERATURE (°C)
_______________________________________________________________________________________
5
MAX807L/M/N
__________________________________________Typical Operating Characteristics
(VCC = 5V, VBATT = 2.8V, PFI = 0, no load, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (contiued)
(VCC = 5V, VBATT = 2.8V, PFI = 0, no load, TA = +25°C, unless otherwise noted.)
4.70
N VERSION
4.65
4.60
4.55
M VERSION
4.50
4.45
VCC FALLING AT 1mV/µs
30
25
20
15
10
5
40
35
-60 -40 -20 0
25
20
15
10
5
0
-60 -40 -20 0
20 40 60 80 100 120 140
VCC FALLING AT 1mV/µs
30
0
4.40
20 40 60 80 100 120 140
-60 -40 -20 0
20 40 60 80 100 120 140
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
BATTERY CURRENT
vs. INPUT SUPPLY VOLTAGE
CHIP-ENABLE PROPAGATION DELAY
vs. CE OUT LOAD CAPACITANCE
BATT-TO-OUT vs.
OUTPUT CURRENT
PROPAGATION DELAY (ns)
12
10
8
6
4
6
4
MAX807-15
VCC = 0
SLOPE = 12Ω
BATT-TO-OUT (mV)
14
1000
MAX807-14
8
MAX807-13
16
100
2
2
50Ω DRIVER
0
0
2.5
2.6
2.7
2.8
2.9
10
0
3.0
50
10
MAXIMUM TRANSIENT DURATION vs.
RESET COMPARATOR OVERDRIVE
100
10
1000
MAX807-17
SLOPE = 1.0Ω
MAXIMUM TRANSIENT DURATION (µs)
MAX807-16
1000
100
IOUT (mA)
VCC-TO-OUT vs.
OUTPUT CURRENT
VCC-VOUT (mV)
1
100
CLOAD (pF)
VCC (V)
RESET OCCURS
100
10
1
1
1
10
100
IOUT (mA)
6
RESET COMPARATOR PROPAGATION
DELAY vs. TEMPERATURE (VCC FALLING)
MAX807-12
35
MAX807-11
40
LOW LINE COMPARATOR PROP DELAY (µs)
L VERSION
4.75
LOW LINE THRESHOLD (V)
MAX807-10
4.80
LOW LINE COMPARATOR PROPAGATION
DELAY vs. TEMPERATURE (VCC FALLING)
RESET COMPARATOR PROP DELAY (µs)
LOW LINE THRESHOLD
vs. TEMPERATURE (VCC RISING)
BATTERY CURRENT (µA)
MAX807L/M/N
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
1000
1
10
100
RESET COMPARATOR OVERDRIVE (mV)
_______________________________________________________________________________________
1000
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
PIN
NAME
FUNCTION
1
PFI
Power-Fail Input. When PFI is less than VPFT (2.265V), PFO goes low. Connect to ground when unused.
2
PFO
Power-Fail Output. This CMOS-logic output goes low when PFI is less than VPFT (2.265V). Valid for
VCC ≥ 4V. PFO swings between VCC and GND.
3
VCC
Input Supply Voltage, nominally +5V. Bypass with a 0.1µF capacitor to GND.
4
WDI
Watchdog Input. If WDI remains high or low longer than the watchdog-timeout period (1.6s typical), WDO
goes low. Leave unconnected to disable the watchdog function.
5
GND
Ground
6
MR
Manual-Reset Input. A logic low on MR asserts reset. Reset remains asserted as long as MR remains low
and for 200ms after MR returns high. MR is an active-low input with an internal pull-up to VCC. It can be
driven using TTL or CMOS logic, or shorted to ground with a switch. Connect to VCC, or leave unconnected if not used.
7
LOW LINE
Low-Line Comparator Output. This CMOS-logic output goes low when VCC falls to 52mV above the reset
threshold. Use this output to generate an NMI to initiate an orderly shutdown routine when VCC is falling.
LOW LINE swings between VCC and GND.
8
RESET
Active-High Reset Output. RESET is the inverse of RESET. It is a CMOS output that sources and sinks
current. RESET swings between VCC and GND.
RESET
Active-Low Reset Output. RESET is triggered and stays low when VCC is below the reset threshold or
when MR is low. It remains low 200ms after VCC rises above the reset threshold or MR returns high.
RESET has a strong pull-down but a relatively weak pull-up, and can be wire-OR connected to logic
gates. Valid for VCC ≥ 1V. RESET swings between VCC and GND.
9
10
WDO
Watchdog Output. This CMOS-logic output goes low if WDI remains high or low longer than the watchdog-timeout period (tWD), and remains low until the next transition of WDI. WDO remains high if WDI is
unconnected. WDO is high during reset. WDO swings between VCC and GND. Connect WDO to MR to
generate resets during watchdog faults.
11
CE OUT
Chip-Enable Output. Output to the chip-enable gating circuit. CE OUT is pulled up to the higher of VCC
or VBATT, when the chip-enable gate is disabled.
12
CE IN
Chip-Enable Input
13
BATT ON
Battery On Output. CMOS-logic output/external bypass switch driver. High when OUT is connected to
BATT and low when OUT is connected to VCC. Connect the base of a PNP transistor or gate of a PMOS
transistor to BATT ON for IOUT requirements exceeding 250mA. BATT ON swings between the higher of
VCC and VBATT and GND.
14
BATT
Backup-Battery Input. When VCC falls below the reset threshold and VBATT, OUT switches from VCC to
BATT. VBATT may exceed VCC. The battery can be removed while the MAX807 is powered-up, provided
BATT is bypassed with a 0.1µF capacitor to GND. If no battery is used, connect BATT to ground, and
connect VCC and OUT together.
15
BATT OK
Battery OK Signal Output. High in normal operating mode when VBATT exceeds VBOK (2.265V). Valid for
VCC ≥ 4V.
16
OUT
Output Supply Voltage to CMOS RAM. When VCC exceeds the reset threshold or VCC > VBATT, OUT is
connected to VCC. When VCC falls below the reset threshold and VBATT, OUT connects to BATT. Bypass
OUT with a 0.1µF capacitor to GND.
_______________________________________________________________________________________
7
MAX807L/M/N
Pin Description
MAX807L/M/N
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
Detailed Description
The MAX807 µP supervisory circuit provides powersupply monitoring, backup-battery switchover, and program execution watchdog functions in µP systems
(Figure 1). Use of BiCMOS technology results in an
improved 1.5% reset-threshold precision, while keeping
supply currents typically below 70µA. The MAX807 is
intended for battery-powered applications that require
high reset-threshold precision, allowing a wide powersupply operating range while preventing the system
from operating below its specified voltage range.
RESET and RESET Outputs
The MAX807’s RESET output ensures that the µP powers up in a known state, and prevents code execution
errors during power-down and brownout conditions. It
accomplishes this by resetting the µP, terminating program execution when VCC dips below the reset threshold or MR is pulled low. Each time RESET is asserted it
stays low for the 200ms reset timeout period, which is
set by an internal timer to ensure the µP has adequate
time to return to an initial state. Any time VCC goes
below the reset threshold before the reset-timeout period is completed, the internal timer restarts. The watchdog timer can also initiate a reset if WDO is connected
to MR. See the Watchdog Input section.
VCC
OUT
BATT
BATTERY-BACKUP
COMPARATOR
P
BATT ON
N
RESET
COMPARATOR
LOW LINE
LOW-LINE
COMPARATOR
BATT OK
PFO
WATCHDOG
TRANSITION
DETECTOR
BATTERY-OK
COMPARATOR
50kΩ
GND
PFI
WDI
VCC
POWER-FAIL
COMPARATOR
MR
RESET
STATE
MACHINE
RESET
WDO
OSCILLATOR
2.275V
THE HIGHER
OF VCC OR VBATT
P
MAX807
P
CE IN
CE OUT
N
Figure 1. Block Diagram
8
_______________________________________________________________________________________
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
VCC
VCC
VLOW LINE
VLOW LINE
VRESET
tRP
VRESET
(MAX801)
VRESET
tRP
VRESET
(MAX808)
VCE OUT
MAX807L/M/N
VRST + VLR VRST
VRST VLL
VBATT
VCE OUT
VBATT
SHOWN FOR VCC = 5V to 0, VBATT = 2.8V, CE IN = GND
SHOWN FOR VCC = 0 to 5V, VBATT = 2.8V, CE IN = GND
Figure 2a. Timing Diagram, VCC Rising
The RESET output is active low and implemented with a
strong pull-down/relatively weak pull-up structure. It is
guaranteed to be a logic low for 0 < VCC < VRST, provided VBATT is greater than 2V. Without a backup battery, RESET is guaranteed valid for VCC ≥ 1. It typically
sinks 3.2mA at 0.1V saturation voltage in its active state.
The RESET output is the inverse of the RESET output; it
both sources and sinks current and cannot be wire-OR
connected. Figure 2a shows a timing diagram with VCC
rising and Figure 2b shows VCC falling.
Figure 2b. Timing Diagram, VCC Falling
MANUAL RESET
MR
*
OTHER
RESET
SOURCES
MAX807
*
Manual Reset Input
Many µP-based products require manual-reset capability to allow an operator or test technician to initiate a
reset. The Manual Reset (MR) input permits the generation of a reset in response to a logic low from a switch,
WDO, or external circuitry. Reset remains asserted
while MR is low, and for 200ms after MR returns high.
MR has an internal 50µA to 200µA pull-up current, so it
can be left open if it is not used. MR can be driven with
TTL or CMOS-logic levels, or with open-drain/collector
outputs. Connect a normally open momentary switch
from MR to GND to create a manual-reset function;
external debounce circuitry is not required. If MR is driven from long cables or if the device is used in a noisy
environment, connect a 0.1µF capacitor from MR to
ground to provide additional noise immunity. As shown
in Figure 3, diode-ORed connections can be used to
allow manual resets from multiple sources. Figure 4
shows the reset timing.
* DIODES NOT REQUIRED ON OPEN-DRAIN OUTPUTS
Figure 3. Diode “OR” Connections Allow Multiple Reset
Sources to Connect to MR
Watchdog Timer
Watchdog Input
The watchdog circuit monitors the µP’s activity. If the
µP does not toggle the watchdog input (WDI) within
1.6s, WDO goes low. The internal 1.6s timer is cleared
and WDO returns high when reset is asserted or when
a transition (low-to-high or high-to-low) occurs at WDI
while RESET is high. As long as reset is asserted, the
timer remains cleared and does not count. As soon as
reset is released, the timer starts counting (Figure 5).
Supply current is typically reduced by 10µA when WDI
is at a valid logic level.
_______________________________________________________________________________________
9
MAX807L/M/N
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
Chip-Enable Signal Gating
1µs MIN
The MAX807 provides internal gating of chip-enable
(CE) signals to prevent erroneous data from corrupting
the CMOS RAM in the event of a power failure. During
normal operation, the CE gate is enabled and passes
all CE transitions. When reset is asserted, this path
becomes disabled, preventing erroneous data from
corrupting the CMOS RAM. The MAX807 uses a series
transmission gate from the Chip-Enable Input (CE IN) to
the Chip-Enable Output (CE OUT) (Figure 1).
MR
170ns
RESET
CE IN
0V
CE OUT
28µs TYP
Figure 4. Manual-Reset Timing Diagram
Watchdog Output
WDO remains high if there is a transition or pulse at
WDI during the watchdog-timeout period. WDO goes
low if no transition occurs at WDI during the watchdogtimeout period. The watchdog function is disabled and
WDO is a logic high when V CC is below the reset
threshold or WDI is an open circuit. To generate a system reset on every watchdog fault, diode-OR connect
WDO to MR (Figure 6). When a watchdog fault occurs
in this mode, WDO goes low, which pulls MR low, causing a reset pulse to be issued. As soon as reset is
asserted, the watchdog timer clears and WDO returns
high. With WDO connected to MR, a continuous high or
low on WDI will cause 200ms reset pulses to be issued
every 1.6s.
The 8ns max chip-enable propagation from CE IN to CE
OUT enables the MAX807 to be used with most µPs.
Chip-Enable Input
CE IN is high impedance (disabled mode) while RESET
is asserted. During a power-down sequence when VCC
passes the reset threshold, the CE transmission gate
disables and CE IN becomes high impedance 28µs
after reset is asserted (Figure 7). During a power-up
sequence, CE IN remains high impedance (regardless
of CE IN activity) until reset is deasserted following the
reset-timeout period.
In the high-impedance mode, the leakage currents into
this input are ±1µA max over temperature. In the lowimpedance mode, the impedance of CE IN appears as
a 75Ω resistor in series with the load at CE OUT.
The propagation delay through the CE transmission
gate depends on both the source impedance of the
drive to CE IN and the capacitive loading on CE OUT
VRST
VCC
4.7k
VCC
MAX807
WDO
RESET
tRP
RESET
MR
WDO
VCC
tWD
∼50µs
WDO
WDI
RESET
tRP
tWD
tRP
WDI
WDO CONNECTED TO µP INTERRUPT
Figure 5. Watchdog Timing Relationship
10
Figure 6. Generating a Reset on Each Watchdog Fault
______________________________________________________________________________________
TO µP
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
MAX807L/M/N
VRST MAX
VCC
RESET
THRESHOLD
VCC
CE IN
MAX807
CE OUT
28µs
26µs
CE IN
CE OUT
26µs
50pF
CLOAD
50Ω DRIVER
RESET
GND
RESET
Figure 7. Reset and Chip-Enable Timing
(see the Chip-Enable Propagation Delay vs. CE OUT
Load Capacitance graph in the Typical Operating
Characteristics). The CE propagation delay is production tested from the 50% point on CE IN to the 50%
point on CE OUT using a 50Ω driver and 50pF of load
capacitance (Figure 8). For minimum propagation
delay, minimize the capacitive load at CE OUT and use
a low output-impedance driver.
Chip-Enable Output
In the enabled mode, the impedance of CE OUT is equivalent to 75Ω in series with the source driving CE IN. In the
disabled mode, the 75Ω transmission gate is off and CE
OUT is actively pulled to the higher of VCC or VBATT. This
source turns off when the transmission gate is enabled.
Figure 8. CE Propagation Delay Test Circuit
4.5V to 5.5V
REGULATOR
VCC
LOW LINE
TO µP NMI
CHOLD
MAX807
CHOLD > ILOAD x tSHDN
VLR
GND
Low-Line Comparator
The low-line comparator monitors VCC with a threshold
voltage typically 52mV above the reset threshold, with
13mV of hysteresis. Use LOW LINE to provide a nonmaskable interrupt (NMI) to the µP when power begins
to fall to initiate an orderly software shutdown routine.
In most battery-operated portable systems, reserve
energy in the battery provides ample time to complete
the shutdown routine once the low-line warning is
encountered, and before reset asserts. If the system
must contend with a more rapid VCC fall time—such as
when the main battery is disconnected, a DC-DC converter shuts down, or a high-side switch is opened during normal operation—use capacitance on the VCC line
to provide time to execute the shutdown routine (Figure
9). First calculate the worst-case time required for the
system to perform its shutdown routine. Then, with the
Figure 9. Using LOW LINE to Provide a Power-Fail Warning to
the µP
worst-case shutdown time, the worst-case load current,
and the minimum low-line to reset threshold (VLR(min)),
calculate the amount of capacitance required to allow the
shutdown routine to complete before reset is asserted:
CHOLD = (ILOAD x tSHDN) / VLR (min)
where tSHDN is the time required for the system to complete the shutdown routine, and includes the VCC to
low-line propagation delay; and where ILOAD is the current being drained from the capacitor, VLR is the lowline to reset threshold.
______________________________________________________________________________________
11
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
MAX807L/M/N
VIN
VCC
R1
MAX807
PFI
VCC
R1
PFO
PFI
R2
MAX807
PFO
R2
MR
GND
GND
VCC
VIN
VCC
PFO
PFO
VL
VTRIP = R2 (VPFT + VPFH)
(
VL = R2 (VPFT)
1
1
VTRIP
( R1 + R2 ) –
1
1
+
R1 R2
)
VCC
R1
VCC
–
R1
VIN
0V
VTRIP = VPFT
WHERE VPFT = 2.265V
VPFH = 20mV
NOTE: VTRIP, VL ARE NEGATIVE.
a)
VTRIP
(
R1 + R2
R2
VH = (VPFT + VPFH)
b)
(
VH
VIN
)
R1 + R2
R2
)
Figure 10. Using the Power-Fail Comparator to Monitor an Additional Power Supply: a) VIN is Negative, b) VIN is Positive
FROM
REGULATED
SUPPLY
Power-Fail Comparator
VCC
OUT
0.1µF
0.1µF
PFI is the noninverting input to an uncommitted comparator. If PFI is less than VPFT (2.265V), PFO goes low.
The power-fail comparator is intended to monitor the
preregulated input of the power supply, providing an
early power-fail warning so software can conduct an
orderly shutdown. It can also be used to monitor supplies other than 5V. Set the power-fail threshold with a
resistor-divider, as shown in Figure 10.
µP POWER
POWER TO
CMOS RAM
MAX807
BATT
µP
2.8V
a)
RESET
NMI
I/O LINE
RESET
LOW LINE
WDI
GND
VCC
OUT
0.1µF
0.1µF
VOLTAGE
REGULATOR
Power-Fail Input
PFI is the input to the power-fail comparator. The typical
comparator delay is 14µs from VIL to VOL (power failing),
and 32µs from VIH to VOH (power being restored). If
unused, connect this input to ground.
µP POWER
POWER TO
CMOS RAM
MAX807
BATT
2.8V
RESET
PFO
WDI
PFI
µP
RESET
NMI
I/O LINE
GND
Power-Fail Output
The Power-Fail Output (PFO) goes low when PFI goes
below VPFT. It typically sinks 3.2mA with a saturation
voltage of 0.1V. With PFI above VPFT, PFO is actively
pulled to V CC . Connecting PFI through a voltagedivider to a preregulated supply allows PFO to generate an NMI as the preregulated power begins to fall
(Figure 11b). If the preregulated supply is inaccessible,
use LOW LINE to generate the NMI (Figure 11a). The
LOW LINE threshold is typically 52mV above the reset
threshold (see Low-Line Comparator section).
b)
Figure 11. a) If the preregulated supply is inaccessible, LOW
LINE generates the NMI for the µP. b) Use PFO to generate the
µP NMI if the preregulated supply is accessible.
12
______________________________________________________________________________________
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
PIN
NAME
FUNCTION
1
PFI
The power-fail comparator remains active in battery-backup mode for VCC ≥ 4V.
2
PFO
The power-fail comparator remains active in battery-backup mode for VCC ≥ 4V. Below 4V, PFO is forced low.
3
VCC
Battery switchover comparator monitors VCC for active switchover.
4
WDI
WDI is ignored and goes high impedance.
5
GND
Ground—0V reference for all signals.
6
MR
7
LOW LINE
8
RESET
Logic high; the open-circuit output voltage is equal to VCC.
9
RESET
Logic low
10
WDO
11
CE OUT
MR is ignored.
Logic low
Logic high. The open-circuit output voltage is equal to VCC.
12
CE IN
13
BATT ON
14
BATT
15
BATT OK
16
OUT
Logic high. The open-circuit output voltage is equal to VBATT.
High impedance.
Logic high. The open-circuit output voltage is equal to VBATT.
Supply current is 1µA maximum for VBATT ≤ 2.8V.
Logic high when VBATT exceeds 2.285V. Valid for VCC ≥ 4V. Below 4V, BATT OK is forced low.
OUT is connected to BATT through two internal PMOS switches in series.
MAX807
P
VCC
CONTROL
CIRCUITRY
OUT
0.1µF
BATT
P
P
Backup-Battery Input
The BATT input is similar to VCC, except the PMOS
switch is much smaller. This input is designed to conduct up to 20mA to OUT during battery backup. The
on-resistance of the PMOS switch is approximately
13Ω. Figure 12 shows the two series pass elements
between the BATT input and OUT that facilitate UL
approval. VBATT can exceed VCC during normal operation without causing a reset.
Output Supply Voltage
The output supply (OUT) transfers power from VCC or
BATT to the µP, RAM, and other external circuitry. At
the maximum source current of 250mA, VOUT will typically be 260mV below VCC. Decouple this terminal with
a 0.1µF capacitor.
BATT ON Output
Figure 12. VCC and BATT-to-OUT Switch
Battery-Backup Mode
Battery backup preserves the contents of RAM in the
event of a brownout or power failure. With a backup
battery installed at BATT, the MAX807 automatically
switches RAM to backup power when VCC falls. Two
conditions are required for switchover to battery-backup mode: 1) VCC must be below the reset threshold; 2)
VCC must be below VBATT. Table 1 lists the status of
inputs and outputs during battery-backup mode.
The battery on (BATT ON) output indicates the status of
the internal battery switchover comparator, which controls the internal V CC and BATT switches. For V CC
greater than V BATT (ignoring the small hysteresis
effect), BATT ON typically sinks 3.2mA at 0.4V. In battery-backup mode, this output sources approximately
5mA. Use BATT ON to indicate battery switchover status, or to supply gate or base drive for an external pass
transistor for higher current applications (see Typical
Operating Circuit).
______________________________________________________________________________________
13
MAX807L/M/N
Table 1. Input and Output Status in Battery-Backup Mode
MAX807L/M/N
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
BATT OK Output
The BATT OK comparator monitors the backup battery
voltage, comparing it with a 2.265V reference (VCC ≥
4V). BATT OK remains high as long as the backup battery voltage remains above 2.265V, signaling that the
backup battery has sufficient voltage to maintain the
memory of static RAM. When the battery voltage drops
below 2.265V, the BATT OK output drops low, signaling
that the backup battery needs to be changed.
Applications Information
The MAX807 is not short-circuit protected. Shorting
OUT to ground, other than power-up transients such as
charging a decoupling capacitor, may destroy the
device. If long leads connect to the IC’s inputs, ensure
that these lines are free from ringing and other conditions that would forward bias the IC’s protection diodes.
There are two distinct modes of operation:
1) Normal Operating Mode, with all circuitry powered
up. Typical supply current from VCC is 70µA, while
only leakage currents flow from the battery.
2) Battery-Backup Mode, where VCC is below VBATT
and VRST. The supply current from the battery is typically less than 1µA.
Using SuperCaps or
MaxCaps with the MAX807
BATT has the same operating voltage range as VCC, and
the battery-switchover threshold voltage is typically
VBATT when VCC is decreasing or VBATT + 0.06V when
V CC is increasing. This hysteresis allows use of a
SuperCap (e.g., order of 0.47F) and a simple charging
circuit as a backup source (Figure 13). Since VBATT can
exceed VCC while VCC is above the reset threshold,
there are no special precautions when using these µP
supervisors with a SuperCap.
Alternative Chip-Enable Gating
Using memory devices with CE and CE inputs allows
the MAX807 CE loop to be bypassed. To do this, connect CE IN to ground, pull up CE OUT to OUT, and
connect CE OUT to the CE input of each memory
device (Figure 14). The CE input of each part then connects directly to the chip-select logic, which does not
have to be gated by the MAX807.
Adding Hysteresis to the
Power-Fail Comparator
The power-fail comparator has a typical input hysteresis of 20mV. This is sufficient for most applications
where a power-supply line is being monitored through
an external voltage-divider (Figure 10).
Figure 15 shows how to add hysteresis to the power-fail
comparator. Select the ratio of R1 and R2 such that PFI
sees 2.265V when VIN falls to the desired trip point
(VTRIP). Resistor R3 adds hysteresis. It will typically be
an order of magnitude greater than R1 or R2. The current through R1 and R2 should be at least 1µA to
ensure that the 25nA (max) PFI input current does not
shift the trip point. R3 should be larger than 10kΩ to
prevent it from loading down the PFO pin. Capacitor C1
adds additional noise rejection.
Rp*
CE
RAM 1
+5V
CE
OUT
CE IN
VCC
1N4148
CE OUT
CE
RAM 2
CE
BATT
OUT
CE
MAX807
RAM 3
0.47F
CE
MAX807
GND
CE
RAM 4
CE
GND
*MAXIMUM Rp VALUE DEPENDS ON
THE NUMBER OF RAMs.
MINIMUM Rp VALUE IS 1kΩ.
Figure 13. SuperCap or MaxCap on BATT
14
ACTIVE-HIGH CE
LINES FROM LOGIC
Figure 14. Alternate CE Gating
______________________________________________________________________________________
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
Negative-Going VCC Transients
While issuing resets to the µP during power-up, powerdown, and brownout conditions, these supervisors are
relatively immune to short-duration negative-going VCC
transients (glitches). It is usually undesirable to reset
the µP when VCC experiences only small glitches.
The Typical Operating Characteristics show Maximum
Transient Duration vs. Reset Comparator Overdrive, for
which reset pulses are not generated. The graph was
produced using negative-going VCC pulses, starting at
5V and ending below the reset threshold by the magnitude indicated (reset comparator overdrive). The graph
shows the maximum pulse width that a negative-going
V CC transient may typically have without causing a
reset pulse to be issued. As the amplitude of the transient increases (i.e., goes farther below the reset
threshold), the maximum allowable pulse width
decreases.
Typically, a VCC transient that goes 40mV below the
reset threshold and lasts for 3µs or less will not cause a
reset pulse to be issued.
VIN
+5V
R1
VCC
PFI
C1*
R3
MAX807
R2
PFO
GND
TO µP
*OPTIONAL
MAX807L/M/N
Backup-Battery Replacement
The backup battery may be disconnected while VCC is
above the reset threshold, provided BATT is bypassed
with a 0.1µF capacitor to ground. No precautions are
necessary to avoid spurious reset pulses.
START
SET
WDI
LOW
SUBROUTINE
OR PROGRAM LOOP,
SET WDI
HIGH
RETURN
END
Figure 16. Watchdog Flow Diagram
A 0.1µF bypass capacitor mounted close to the VCC
pin provides additional transient immunity.
Watchdog Software Considerations
To help the watchdog timer keep a closer watch on software execution, you can use the method of setting and
resetting the watchdog input at different points in the
program, rather than “pulsing” the watchdog input highlow-high or low-high-low. This technique avoids a “stuck”
loop where the watchdog timer continues to be reset
within the loop, keeping the watchdog from timing out.
Figure 16 shows an example flow diagram where the
I/O driving the watchdog input is set high at the beginning of the program, set low at the beginning of every
subroutine or loop, then set high again when the program returns to the beginning. If the program should
“hang” in any subroutine, the I/O is continually set low
and the watchdog timer is allowed to time out, causing
a reset or interrupt to be issued.
Maximum VCC Fall Time
+5V
PFO
0
0
VTRIP = 2.265 R1 + R2
R2
VH = 2.265 /
R2 || R3
R1 + R2 || R3
VL VTRIP VH
VIN
VL - 2.265 + 5 - 2.265 = 2.265
R1
R3
R2
Figure 15. Adding Hysteresis to the Power-Fail Comparator
The VCC fall time is limited by the propagation delay of
the battery switchover comparator and should not
exceed 0.03V/µs. A standard rule for filter capacitance
on most regulators is on the order of 100µF per amp of
current. When the power supply is shut off or the main
battery is disconnected, the associated initial VCC fall
rate is just the inverse or 1A / 100µF = 0.01V/µs. The
VCC fall rate decreases with time as VCC falls exponentially, which more than satisfies the maximum fall-time
requirement.
______________________________________________________________________________________
15
MAX807L/M/N
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
Typical Operating Circuit
Ordering Information
†
+5V
0.1µF
0.1µF
VCC BATT
BATT ON
OUT
CMOS
RAM
CE OUT
MR
CE IN
PUSHBUTTON
SWITCH
A0–A15
I/O
WDI
LOW LINE
RESET
RESET
BATT OK
+12V
SUPPLY
PFO
WDO
PFI
0°C to +70°C
16 Plastic DIP
PIN-PACKAGE
MAX807_CUE
0°C to +70°C
16 TSSOP
0°C to +70°C
16 Wide SO
MAX807_EPE
-40°C to +85°C
16 Plastic DIP
MAX807_EUE
-40°C to +85°C
16 TSSOP
MAX807_EWE
MAX807_MJE
-40°C to +85°C
-55°C to +125°C
16 Wide SO
16 CERDIP
† This part offers a choice of reset threshold voltage. From the
table below, select the suffix corresponding to the desired
threshold and insert it into the blank to complete the part number.
ADDRESS
DECODE
MAX807
TEMP. RANGE
MAX807_CWE
REALTIME
CLOCK
0.47F*
OTHER
SYSTEM
RESET
SOURCES
PART
MAX807_CPE
NMI
µP
SUFFIX
RESET
RESET
INTERRUPT
L
N
M
RESET THRESHOLD (V)
MIN
TYP
MAX
4.60
4.50
4.35
4.675
4.575
4.425
4.75
4.65
4.50
+12V SUPPLY FAILURE
WATCHDOG FAILURE
GND
*MaxCap
___________________Chip Information
TRANSISTOR COUNT: 984
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.