ONSEMI MMSF3P02HDR2

MMSF3P02HD
Preferred Device
Power MOSFET
3 Amps, 20 Volts
P−Channel SO−8
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
drain−to−source diode has a very low reverse recovery time.
MiniMOSt devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dc−dc converters, and power management in portable
and battery powered products such as computers, printers, cellular and
cordless phones. They can also be used for low voltage motor controls
in mass storage products such as disk drives and tape drives. The
avalanche energy is specified to eliminate the guesswork in designs
where inductive loads are switched and offer additional safety margin
against unexpected voltage transients.
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3 AMPERES, 20 VOLTS
RDS(on) = 75 mW
P−Channel
D
G
Features
•
•
•
•
•
•
•
•
•
Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive − Can Be Driven by Logic ICs
Miniature SO−8 Surface Mount Package − Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Avalanche Energy Specified
Mounting Information for SO−8 Package Provided
Pb−Free Package is Available
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) (Note 1)
S
MARKING
DIAGRAM
8
SO−8
CASE 751
STYLE 13
8
1
S3P02
AYWWG
G
1
S3P02 = Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
20
Vdc
Drain−to−Gate Voltage (RGS = 1.0 MW)
VDGR
20
Vdc
Gate−to−Source Voltage − Continuous
VGS
± 20
Vdc
ID
ID
Adc
N−C
1
8
Drain
Apk
Rating
PIN ASSIGNMENT
Drain Current − Continuous @ TA = 25°C
Drain Current − Continuous @ TA = 100°C
Drain Current − Single Pulse (tp ≤ 10 ms)
IDM
5.6
3.6
30
Source
2
7
Drain
Total Power Dissipation @ TA = 25°C (Note 2)
PD
2.5
W
Source
3
6
Drain
Operating and Storage Temperature Range
TJ, Tstg
− 55 to 150
°C
Gate
4
5
Drain
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C (VDD = 20 Vdc,
VGS = 5.0 Vdc, Peak IL = 9.0 Apk, L = 14
mH, RG = 25 W)
EAS
567
mJ
Thermal Resistance, Junction−to−Ambient
(Note 2)
RqJA
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
TL
ORDERING INFORMATION
50
260
°C/
W
Device
Package
Shipping†
MMSF3P02HDR2
SO−8
2500 Tape & Reel
°C
MMSF3P02HDR2G
SO−8
(Pb−Free)
2500 Tape & Reel
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Negative sign for P−Channel device omitted for clarity.
2. Mounted on 2″ square FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided),
10 sec. max.
© Semiconductor Components Industries, LLC, 2006
February, 2006 − Rev. 7
1
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Preferred devices are recommended choices for future use
and best overall value.
Publication Order Number:
MMSF3P02HD/D
MMSF3P02HD
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Note 3)
Symbol
Characteristic
Min
Typ
Max
Unit
20
−
−
24
−
−
−
−
−
−
1.0
10
−
−
100
1.0
−
1.5
4.0
2.0
−
−
−
0.06
0.08
0.075
0.095
gFS
3.0
7.2
−
mhos
Ciss
−
1010
1400
pF
Coss
−
740
920
Crss
−
260
490
td(on)
−
25
50
tr
−
135
270
td(off)
−
54
108
tf
−
84
168
td(on)
−
16
32
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 mAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 20 Vdc, VGS = 0 Vdc)
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
IGSS
Vdc
mV/°C
mAdc
nAdc
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
(VDS = VGS, ID = 250 mAdc)
Temperature Coefficient (Negative)
VGS(th)
Static Drain−Source On−Resistance
(VGS = 10 Vdc, ID = 3.0 Adc)
(VGS = 4.5 Vdc, ID = 1.5 Adc)
RDS(on)
Forward Transconductance (VDS = 3.0 Vdc, ID = 1.5 Adc)
Vdc
mV/°C
W
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 16 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 10 Vdc, ID = 3.0 Adc,
VGS = 4.5 Vdc, RG = 6.0 W)
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 10 Vdc, ID = 3.0 Adc,
VGS = 10 Vdc, RG = 6.0 W)
Fall Time
Gate Charge
See Figure 8
(VDS = 16 Vdc, ID = 3.0 Adc,
VGS = 10 Vdc)
tr
−
40
80
td(off)
−
110
220
tf
−
97
194
QT
−
33
46
Q1
−
3.0
−
Q2
−
11
−
Q3
−
10
−
−
−
1.35
0.96
1.75
−
trr
−
76
−
ta
−
32
−
tb
−
44
−
QRR
−
0.133
−
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (Note 4)
(IS = 3.0 Adc, VGS = 0 Vdc)
(IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
See Figure 15
(IS = 3.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms)
Reverse Recovery Stored Charge
3. Negative sign for P−Channel device omitted for clarity.
4. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
5. Switching characteristics are independent of operating junction temperature.
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2
VSD
Vdc
ns
mC
MMSF3P02HD
TYPICAL ELECTRICAL CHARACTERISTICS
6
5
3.3 V
4.5 V
3.9 V
I D , DRAIN CURRENT (AMPS)
3.7 V
3.1 V
4
3
2.9 V
2
2.7 V
0
5
4
3
TJ = 100°C
2
25°C
1
1
R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
VDS ≥ 10 V
TJ = 25°C
2.5 V
0
0.2
0.4
0.6
0.8
1
1.2
1.4
− 55°C
1.6
1.8
0
1.6
2
2.2
2.4
2.6
2.8
3
Figure 2. Transfer Characteristics
0.4
0.2
0
1
2
3
4
5
6
7
8
9
10
3.4
3.2
Figure 1. On−Region Characteristics
ID = 1.5 A
TJ = 25°C
0.09
TJ = 25°C
0.08
VGS = 4.5 V
0.07
10 V
0.06
0.05
0
1
2
3
5
4
6
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus
Gate−To−Source Voltage
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1000
1.20
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
2
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0.6
0
1.8
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
I D , DRAIN CURRENT (AMPS)
6
3.5 V
VGS = 10 V
VGS = 0 V
VGS = 10 V
ID = 3.0 A
I DSS , LEAKAGE (nA)
1.10
1.00
0.90
0.80
−50
0
25
50
75
100
125
TJ = 125°C
100
10
150
0
4
8
12
16
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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3
20
MMSF3P02HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
3500
TJ = 25°C
VGS = 0 V
C, CAPACITANCE (pF)
3000
2500
Ciss
2000
1500
Crss
Ciss
1000
Coss
500
0
10
Crss
5
5
0
VGS
10
15
12
10
20
VGS
8
16
6
Q1
12
ID = 3 A
TJ = 25°C
Q2
8
4
2
4
VDS
Q3
0
20
24
QT
0
0
4
8
12
16
20
24
28
32
36
VDS
QT, TOTAL CHARGE (nC)
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (Volts)
Figure 7. Capacitance Variation
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
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VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VDS = 0 V
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
MMSF3P02HD
1000
t, TIME (ns)
VDD = 10 V
ID = 3 A
VGS = 10 V
TJ = 25°C
td(off)
100
tf
tr
td(on)
10
1
10
100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
high di/dts. The diode’s negative di/dt during ta is directly
controlled by the device clearing the stored charge.
However, the positive di/dt during tb is an uncontrollable
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of tb/ta serves as a good indicator of recovery
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter trr), have less stored charge and a softer
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, trr, due
to the storage of minority carrier charge, QRR, as shown in
the typical reverse recovery wave form of Figure 15. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short trr and low QRR specifications to
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
3
di/dt = 300 A/ms
VGS = 0 V
TJ = 25°C
Standard Cell Density
trr
High Cell Density
trr
tb
ta
I S , SOURCE CURRENT
I S , SOURCE CURRENT (AMPS)
2.5
2
1.5
1
0.5
0
0.3 0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
t, TIME
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
Figure 11. Reverse Recovery Time (trr)
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MMSF3P02HD
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded, and that the
transition time (tr, tf) does not exceed 10 ms. In addition the
total power averaged over a complete switching cycle must
not exceed (TJ(MAX) − TC)/(RqJC).
A power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non−linearly with an increase of peak current in avalanche
and peak junction temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 13). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
600
10
VGS = 20 V
SINGLE PULSE
TC = 25°C
1 ms
0.01
0.1
100 ms
10 ms
1
0.1
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)
100
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″
thick single sided), 10s max.
1
450
300
150
0
10
100
ID = 9 A
25
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
50
75
100
125
150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
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MMSF3P02HD
TYPICAL ELECTRICAL CHARACTERISTICS
Rthja(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE
10
1
0.1
D = 0.5
0.2
0.1
0.05
0.02
0.01
Normalized to qja at 10s.
Chip
0.0163 W
0.0652 W
0.1988 W
0.0307 F
0.1668 F
0.5541 F
0.6411 W
0.9502 W
0.01
1.9437 F
72.416 F
SINGLE PULSE
0.001
1.0E−05
1.0E−04
1.0E−03
1.0E−02
1.0E−01
t, TIME (s)
1.0E+00
1.0E+01
Figure 14. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 15. Diode Reverse Recovery Waveform
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1.0E+02
Ambient
1.0E+03
MMSF3P02HD
PACKAGE DIMENSIONS
SOIC−8
CASE 751−07
ISSUE AG
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
STYLE 13:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOLDERING FOOTPRINT*
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
N.C.
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
DRAIN
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
MiniMOS are trademarks of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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For additional information, please contact your
local Sales Representative.
MMSF3P02HD/D