TI V62/07608-01XE

SN65HVD1050-EP
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SLLS772A – DECEMBER 2006 – REVISED OCTOBER 2009
EMC OPTIMIZED CAN TRANSCEIVER
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FEATURES
1
•
2
•
•
•
•
•
•
•
•
•
•
•
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
Enhanced Diminishing Manufacturing Sources
(DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
Improved Replacement for the TJA1050
High Electromagnetic Immunity (EMI)
Very Low Electromagnetic Emissions (EME)
Meets or Exceeds the Requirements of
ISO 11898-2
Bus-Fault Protection of –27 V to 40 V
Dominant Time-Out Function
Thermal Shutdown Protection
Power-Up/Down Glitch-Free Bus Inputs and
Outputs
– High Input Impedance With Low VCC
– Monotonic Outputs During Power Cycling
APPLICATIONS
•
•
•
•
•
(1)
Industrial Automation
– DeviceNET™ Data Buses (Vendor ID #806)
SAE J2284 High-Speed CAN for Automotive
Applications
SAE J1939 Standard Data Bus Interface
ISO 11783 Standard Data Bus Interface
NMEA 2000 Standard Data Bus Interface
Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
D PACKAGE
(TOP VIEW)
TXD
GND
VCC
RXD
1
8
2
7
3
6
4
5
S
CANH
CANL
Vref
DESCRIPTION/
ORDERING INFORMATION
The SN65HVD1050 meets or exceeds the
specifications of the ISO 11898 standard for use in
applications employing a controller area network
(CAN). The device is also qualified for use in
automotive
applications
in
accordance
with
AEC-Q100. (2)
As a CAN transceiver, this device provides differential
transmit capability to the bus and differential receive
capability to a CAN controller at signaling rates up to
1 megabit per second (Mbps) (3).
Designed for operation in especially harsh
environments,
the
SN65HVD1050
features
cross-wire, overvoltage, and loss of ground protection
from –27 V to 40 V, overtemperature protection, a
–12-V to 12-V common-mode range, and withstands
voltage transients from –200 V to 200 V, according to
ISO 7637.
Pin 8 provides for two different modes of operation:
high-speed or silent mode. The high-speed mode of
operation is selected by connecting S (pin 8) to
ground.
(2)
(3)
The device is available with Q100 qualification as the
SN65HVD1050Q (Product Preview).
The signaling rate of a line is the number of voltage
transitions that are made, per second, expressed in the units
bps (bits per second).
blk
blk
ORDERING INFORMATION
PART NUMBER
PACKAGE
MARKED AS
ORDERING NUMBER
SN65HVD1050M
SOIC-8
1050EP
SN65HVD1050MDREP (reel)
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DeviceNET is a trademark of Open Devicenet Vendors Association, Inc.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2009, Texas Instruments Incorporated
SN65HVD1050-EP
SLLS772A – DECEMBER 2006 – REVISED OCTOBER 2009
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
If a high logic level is applied to the S pin of the SN65HVD1050, the device enters a listen-only silent mode,
during which the driver is switched off while the receiver remains fully functional.
In silent mode, all bus activity is passed by the receiver output to the local protocol controller. When data
transmission is required, the local protocol controller reverses this low-current silent mode by placing a logic low
on the S pin to resume full operation.
A dominant-time-out circuit in the SN65HVD1050 prevents the driver from blocking network communication with
a hardware or software failure. The time-out circuit is triggered by a falling edge on TXD (pin 1). If no rising edge
is seen before the time-out constant of the circuit expires, the driver is disabled. The circuit is then reset by the
next rising edge on TXD.
Vref (pin 5) is available as a VCC/2 voltage reference.
The SN65HVD1050M is characterized for operation from –55°C to 125°C.
FUNCTION BLOCK DIAGRAM
8
Silent Mode
VCC
S
VCC
3
Temperature
Protection
Dominant
Time-Out
30 mA
VCC/2
5
Vref
30 mA
TXD
7
1
Driver
6
CANH
CANL
2
RXD
4
Absolute Maximum Ratings (1)
UNIT
VCC
Supply voltage
(2)
–0.3 V to 7 V
Voltage range at any bus terminal (CANH, CANL, Vref)
IO
Receiver output current
VI
Voltage input, transient pulse
VI
Voltage input range (TXD, S)
TJ
Junction temperature
(1)
(2)
(3)
2
–27 V to 40 V
20 mA
(3)
(CANH, CANL)
–200 V to 200 V
–0.5 V to 6 V
–55°C to 170°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with ISO 7637, test pulses 1, 2, 3a, 3b, 5, 6, and 7
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SLLS772A – DECEMBER 2006 – REVISED OCTOBER 2009
Electrostatic Discharge Protection
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Human-Body Model (2)
Electrostatic discharge
(1)
Charged-Device Model (3)
UNIT
Bus terminals and GND
±8 kV
All pins
±4 kV
All pins
±1.5 kV
Machine Model
(1)
(2)
(3)
±200 V
All typical values at 25°C
Tested in accordance with JEDEC Standard 22, Test Method A114-A
Tested in accordance with JEDEC Standard 22, Test Method C101
Recommended Operating Conditions
MIN
MAX
UNIT
VCC
Supply voltage
4.75
5.25
V
VI or VIC
Voltage at any bus terminal (separately or common mode)
–12
12
V
VIH
High-level input voltage
TXD, S
2
5.25
V
VIL
Low-level input voltage
TXD, S
0
0.8
V
VID
Differential input voltage
–6
6
V
IOH
High-level output current
IOL
Low-level output current
TJ
Junction temperature
Driver
–70
Receiver
mA
–2
Driver
70
Receiver
2
See Thermal Characteristics table,
1-Mbps minimum signaling rate with RL = 54 Ω
150
mA
°C
Supply Current
over recommended operating conditions (unless otherwise noted)
PARAMETER
ICC
5-V supply current
TEST CONDITIONS
Silent mode
S at VCC, VI = VCC
Dominant
VI = 0 V, 60-Ω load, S at 0 V
Recessive
VI = VCC, No load, S at 0 V
MIN
TYP
MAX
6
10
50
70
6
10
UNIT
mA
Device Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
td(LOOP1)
td(LOOP2)
TEST CONDITIONS
Total loop delay, driver input to receiver output, recessive to
dominant
Total loop delay, driver input to receiver output, dominant to
recessive
MIN
MAX
90
230
90
230
S at 0 V, See Figure 9
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UNIT
ns
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SLLS772A – DECEMBER 2006 – REVISED OCTOBER 2009
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Driver Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
VO(D)
Bus output voltage (dominant)
VO(R)
Bus output voltage (recessive)
VOD(D)
TEST CONDITIONS
CANH
CANL
Differential output voltage (recessive)
TYP
MAX
2.9
3.4
4.5
(1)
0.8
VI = 3 V, S at 0 V, RL = 60 Ω,
See Figure 1 and Figure 2
Differential output voltage (dominant)
VOD(R)
VI = 0 V, S at 0 V, RL = 60 Ω,
See Figure 1 and Figure 2
MIN
2
2.3
3
VI = 0 V, RL = 60 Ω, S at 0 V,
See Figure 1, Figure 2, and Figure 3
1.5
3
VI = 0 V, RL = 45 Ω, S at 0 V,
See Figure 1, Figure 2, and Figure 3
1.4
3
VI = 3 V, S at 0 V,
See Figure 1 and Figure 2
–0.012
0.012
VI = 3 V, S at 0 V, No load
–0.5
0.05
ΔVOC(ss)
Change in steady-state common-mode
output voltage
S at 0 V, See Figure 8
IIH
High-level input current, TXD input
VI at VCC
–2
2
IIL
Low-level input current, TXD input
VI at 0 V
–50
–10
IO(off)
Power-off TXD output current
VCC at 0 V, TXD at 5 V
2
(1)
3
V
mV
μA
1
–105
VCANH = 12 V, CANL open, SeeFigure 11
VCANL = –12 V, CANH open, See Figure 11
–72
0.36
–1
VCANL = 12 V, CANH open, See Figure 11
Output capacitance
2.3
V
30
VCANH = –12 V, CANL open, See Figure 11
CO
V
V
Steady-state common-mode output voltage
Short-circuit steady-state output current
V
1.5
VOC(ss)
IOS(ss)
UNIT
1
mA
–0.5
71
105
MIN
TYP
MAX
25
65
120
25
45
120
See receiver input capacitance
All typical values are at 25°C, with a 5-V supply.
Driver Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay time, low- to high-level output
tPHL
Propagation delay time, high- to low-level output
tr
Differential output signal rise time
tf
Differential output signal fall time
ten
Enable time from silent mode to dominant
See Figure 7
t(dom)
Dominant time-out
↓VI, See Figure 10
4
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S at 0 V, See Figure 4
25
S at 0 V, See Figure 4
450
ns
ns
50
300
UNIT
1
μs
700
μs
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SLLS772A – DECEMBER 2006 – REVISED OCTOBER 2009
Receiver Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
(1)
MAX
UNIT
800
900
mV
TYP
VIT+
Positive-going input threshold voltage
S at 0 V, See Table 3
VIT–
Negative-going input threshold voltage
S at 0 V, See Table 3
Vhys
Hysteresis voltage (VIT+ – VIT–)
VOH
High-level output voltage
IO = –2 mA, See Figure 6
VOL
Low-level output voltage
IO = 2 mA, See Figure 6
0.2
0.4
V
II(off)
Power-off bus input current
CANH or CANL = 5 V,
Other pin at 0 V,
VCC at 0 V, TXD at 0 V
165
250
μA
IO(off)
Power-off RXD leakage current
VCC at 0 V, RXD at 5 V
20
μA
CI
Input capacitance to ground (CANH or CANL)
TXD at 3 V,
VI = 0.4 sin (4E6πt) + 2.5 V
CID
Differential input capacitance
TXD at 3 V, VI = 0.4 sin (4E6πt)
RID
Differential input resistance
TXD at 3 V, S at 0 V
30
80
kΩ
RIN
Input resistance (CANH or CANL)
TXD at 3 V, S at 0 V
15
30
40
kΩ
RI(m)
Input resistance matching
[1 – (RIN (CANH) / RIN (CANL))] ×100%
VO(CANH) = VO(CANL)
–3%
0%
3%
MIN
TYP
MAX
60
100
130
45
70
130
(1)
500
650
mV
100
125
mV
4
4.6
V
13
pF
5
pF
All typical values are at 25 C with a 5-V supply.
Receiver Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay time, low- to high-level output
tPHL
Propagation delay time, high- to low-level output
tr
Output signal rise time
tf
Output signal fall time
S at 0 V or VCC, See Figure 6
8
S at 0 V or VCC, See Figure 6
UNIT
ns
ns
8
S-Pin Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IIH
High-level input current
S at 2 V
IIL
Low-level input current
S at 0.8 V
MIN
TYP
MAX
UNIT
20
40
70
μA
5
20
30
μA
Vref-PIN Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VO
TEST CONDITIONS
–50 μA < IO < 50 μA
Reference output voltage
MIN
0.4 VCC
TYP
MAX
0.5 VCC 0.6 VCC
UNIT
V
Thermal Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Low-K thermal resistance
(1)
MIN
TYP
MAX
211
UNIT
θJA
Junction to Air
θJB
Junction-to-board thermal resistance
53
°C/W
θJC
Junction-to-case thermal resistance
79
°C/W
(1)
High-K thermal resistance
131
°C/W
Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface-mount packages
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Thermal Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
PD
TEST CONDITIONS
MIN
VCC = 5 V, TJ = 27°C, RL = 60 Ω, S at 0 V,
Input to TXD a 500-kHz, 50% duty-cycle square wave,
CL at RXD = 15 pF
Average power dissipation
TYP
MAX
UNIT
112
mW
VCC = 5.5 V, Tj = 130°C, RL = 45 Ω, S at 0 V,
Input to TXD a 500-kHz, 50% duty-cycle square wave,
CL at RXD = 15 pF
170
Thermal shutdown temperature
190
°C
FUNCTION TABLES
Table 1. DRIVER
INPUTS
TXD
(1)
(1)
OUTPUTS
S
(1)
CANH
(1)
BUS STATE
(1)
CANL
L
L or Open
H
L
Dominant
H
X
Z
Z
Recessive
Open
X
Z
Z
Recessive
X
H
Z
Z
Recessive
H = high level, L = low level, X = irrelevant, Z = high impedance
Table 2. RECEIVER
DIFFERENTIAL INPUTS
VID = V(CANH) – V(CANL)
(1)
6
OUTPUT RXD
(1)
BUS STATE
VID ≥ 0.9 V
L
0.5 V < VID < 0.9 V
?
?
VID ≤ 0.5 V
H
Recessive
Open
H
Recessive
Dominant
H = high level, L = low level, X = irrelevant, ? = indeterminate
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PARAMETER MEASUREMENT INFORMATION
IO(CANH)
VO (CANH)
TXD
II
VOD
RL
VO(CANH) + VO(CANL)
2
I I(S)
S
VI
VOC
I O(CANL)
+
VI(S)
_
V O(CANL)
Figure 1. Driver Voltage, Current, and Test Definition
Dominant
3.5 V
Recessive
VO(CANH)
2.5 V
VO(CANL)
1.5 V
Figure 2. Bus Logic State Voltage Definitions
CANH
0V
TXD
VOD
330 W +1%
RL
+
_
S
CANL
−2 V 3 VTEST 3 7 V
330 W +1%
Figure 3. Driver VOD Test Circuit
CANH
VCC
VI
TXD
VO
tPLH
CL = 100 pF
(see Note B)
VO
S
VCC/2
0V
RL = 60 W
±1%
VI
(See Note A)
VCC/2
tPHL
10%
CANL
VO(D)
90%
0.9 V
tr
tf
0.5 V
VO(R)
Figure 4. Driver Test Circuit and Voltage Waveforms
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PARAMETER MEASUREMENT INFORMATION (continued)
CANH
RXD
VI (CANH)
IO
VID
V
+ VI (CANL)
VIC = I (CANH)
2
VI (CANL)
VO
CANL
Figure 5. Receiver Voltage and Current Definitions
3.5 V
CANH
VI
V
RXD
1.5 V
tPLH
CANL
1.5 V
CL = 15 pF + 20%
(See Note B)
S
2.4 V
IO
I
(See Note A)
2V
VO
tPHL
90%
0.7 VCC
VO
10%
VOH
0.3 VCC
VOL
tf
tr
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle,
tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B.
CL includes instrumentation and fixture capacitance within ±20%.
Figure 6. Receiver Test Circuit and Voltage Waveforms
Table 3. Differential Input Voltage Threshold Test
INPUT
8
OUTPUT
VCANH
VCANL
|VID|
–11.1 V
–12 V
900 mV
L
12 V
11.1 V
900 mV
L
–6 V
–12 V
6V
L
12 V
6V
6V
L
–11.5 V
–12 V
500 mV
H
12 V
11.5 V
500 mV
H
–12 V
–6 V
6V
H
6V
12 V
6V
H
Open
Open
X
H
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R
VOL
VOH
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DUT
CANH
TXD
0V
CL
S
VI
60 W
+1%
0V
VOH
CANL
NOTE: CL = 100 pF
includes
instrumentation
and fixture capacitance
within ±20%
RXD
+
VO
_
VCC
50 %
VI
15 pF +20%
50 %
VO
VOL
ten
NOTE: All VI input pulses are supplied by a generator having the
following characteristics: tr or tf ≤ 6 ns, Pulse Repetition Rate
(PRR) = 25 kHz, 50% duty cycle
Figure 7. ten Test Circuit and Waveforms
27 W +1%
VI
DVOC(SS)
CANH
TXD
VOC
CANL
S
27 W +1%
47 nF V = VO(CANH) + VO(CANL)
+20% OC
2
NOTE: All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns.
Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle.
Figure 8. Common-Mode Output Voltage Test and Waveform
DUT
VCC
CANH
VI
TXD
S
CL
60 W
±1%
TXD Input
0V
+
tloop1
tloop2
VOH
CANL
RXD Output
RXD
50%
50%
50%
NOTE: CL = 100 pF
includes instrumentation
and fixture capacitance
within ±20%
VOL
VO
_
15 pF ±20%
A.
All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns.
Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle.
Figure 9. t(LOOP) Test Circuit and Waveform
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VCC
VI
TXD
RL = 60 W
+1%
VI
(See Note A)
S
0V
VOD
CL
(See Note B)
VOD(D)
VOD
900 mV
500 mV
CANH
0V
tdom
A.
All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns.
Pulse Repetition Rate (PRR) = 500 Hz, 50% duty cycle.
B.
CL = 100 pF includes instrumentation and fixture capacitance within ±20%.
Figure 10. Dominant Time-Out Test Circuit and Waveforms
| IOS(SS) |
| IOS(P) |
IOS
200 ms
CANH
TXD
0V
0 V or VCC
12 V
S
CANL
VIN
−12 V or 12 V
Vin
0V
or
0V
10 ms
Vin
−12 V
Figure 11. Driver Short-Circuit Current Test and Waveforms
10
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DEVICE INFORMATION
Table 4. Parametric Cross-Reference With the TJA1050
TJA1050
(1)
PARAMETER
HVD1050
Transmitter Section
VIH
High-level input voltage
Recommended VIH
VIL
Low-level input voltage
Recommended VIL
IIH
High-level input current
Driver IIH
IIL
Low-level input current
Driver IIL
ILI
Power-off bus input current
Receiver II(off)
IO(SC)
Short-circuit output current
Driver IOS(SS)
VO(dom)
Dominant output voltage
Driver VO(D)
Vi(dif)(th)
Differential input voltage
Receiver VIT and recommended VID
Vi(dif)(hys)
Differential input hysteresis
Receiver Vhys
VO(reces)
Recessive output voltage
Driver VO(R)
VO(dif)(bus)
Differential bus voltage
Driver VOD(D) and VOD(R)
Ri(cm)
CANH, CANL input resistance
Receiver RIN
Ri(dif)
Differential input resistance
Receiver RID
Ri(cm) (m)
Input resistance matching
Receiver RI (m)
CI
Input capacitance to ground
Receiver CI
Ci(dif)
Differential input capacitance
Receiver CID
Bus Section
Receiver Section
IOH
High-level output current
Recommended IOH
IOL
Low-level output current
Recommended IOL
Vref-Pin Section
Vref
Reference output voltage
VO
td(TXD-BUSon)
Delay TXD to bus active
Driver tPLH
td(TXD-BUSoff)
Delay TXD to bus inactive
Driver tPHL
td(BUSon-RXD)
Delay bus active to RXD
Receiver tPHL
td(BUSoff-RXD)
Delay bus inactive to RXD
Receiver tPLH
td(TXD-BUSon) + td(BUSon-RXD)
Device tLOOP1
td(TXD-BUSoff) + td(BUSoff-RXD)
Device tLOOP2
Dominant time-out
Driver t(dom)
VIH
High-level input voltage
Recommended VIH
VIL
Low-level input voltage
Recommended VIL
IIH
High-level input current
IIH
IIL
Low-level input current
IIL
Timing Section
tdom(TXD)
S-Pin Section
(1)
From TJA1050 Product Specification, Philips Semiconductors, 2002 May 16
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Equivalent Input and Output Schematic Diagrams
TXD Input
Vcc
RXD Output
Vcc
25 W
4.3 kW
Output
Input
6V
6V
CANL Input
CANH Input
Vcc
Vcc
10 kW
10 kW
20 kW
20 kW
Input
Input
10 kW
40 V
10 kW
40 V
CANH and CANL Outputs
S Input
Vcc
Vcc
CANH
4.3 kW
Input
6V
CANL
40 kW
40 V
40 V
Vref Output
Vcc
2 kW
Output
2 kW
40 V
12
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Product Folder Link(s) :SN65HVD1050-EP
SN65HVD1050-EP
www.ti.com
SLLS772A – DECEMBER 2006 – REVISED OCTOBER 2009
TYPICAL CHARACTERISTICS
150
145
140
DOMINANT-TO-RECESSIVE LOOP TIME
vs
FREE-AIR TEMPERATURE (Across VCC)
t LOOP2 − Dominant-to-Recessive Loop Time − ns
t LOOP1− Recessive-to-Dominant Loop Time − ns
RECESSIVE-TO-DOMINANT LOOP TIME
vs
FREE-AIR TEMPERATURE (Across VCC)
S at 0 V
RL = 60 W
CL = 100 pF
Air Flow at 7 cf/m
TXD Input is a 125-kHz
50% Duty Cycle Pulse
VCC = 4.75 V
135
130
VCC = 5 V
125
VCC = 5.25 V
120
−40
0
25
70
TA − Free-Air Temperature − °C
160
S at 0 V
RL = 60 W
CL = 100 pF
Air Flow at 7 cf/m
TXD Input is a 125-kHz
50% Duty Cycle Pulse
VCC = 5.25 V
155
VCC = 5 V
150
145
VCC = 4.75 V
140
−40
0
25
70
125
TA − Free-Air Temperature − °C
Figure 12.
Figure 13.
SUPPLY CURRENT (RMS)
vs
SIGNALING RATE
DRIVER LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
90
TA = 25°C
VCC = 5 V
S at 0 V
RL = 60 W
RXD = 15 pF
I OL − Low-Level Output Current − mA
I CC − RMS Supply Current − mA
40
165
125
50
45
170
35
30
25
20
15
10
5
80
70
60
50
40
30
20
TA = 25°C
VCC = 5 V
S at 0 V
TXD Input is a 125-kHz
1% Duty Cycle Pulse
10
0
0
200
400
500
600
800
Signaling Rate − kbps
1000
−10
0
1
2
3
4
5
VO(CANL) − Low-Level Output Voltage – V
Figure 14.
Figure 15.
Copyright © 2006–2009, Texas Instruments Incorporated
Product Folder Link(s) :SN65HVD1050-EP
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13
SN65HVD1050-EP
SLLS772A – DECEMBER 2006 – REVISED OCTOBER 2009
www.ti.com
TYPICAL CHARACTERISTICS (continued)
TA = 25°C
VCC = 5 V
S at 0 V
TXD Input is a 125-kHz
1% Duty Cycle Pulse
-70
-60
-50
-40
-30
-20
-10
-0
1
S at 0 V
RL = 60 W
Air Flow at 7 cf/m
TXD Input is a 125-kHz
1% Duty Cycle Pulse
0.5
0
25
70
TA − Free-Air Temperature − °C
Figure 16.
Figure 17.
DRIVER OUTPUT CURRENT
vs
SUPPLY VOLTAGE
RECEIVER OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
125
6
TA = 25°C
VCC = 5 V
S at 0 V
RL = 60 W
TXD Input is a 125-kHz
1% Duty Cycle Pulse
VIT+
VIT−
5
30
25
20
15
10
VCM = 12 V
4
VCM = 2.5 V
3
VCM = −12 V
2
TA = 255C,
VCC = 5 V,
S at 0 V,
RXD = 15 pF
1
0.60
0.65
0.70
5.25
0.75
3.5
4
4.5
5
VCC − Supply Voltage − V
0.80
3
0.85
2
0.85
1
−1
1
0.80
0
0.75
0
5
0.70
35
VCC = 4.75 V
1.5
0.65
40
VCC = 5.25 V
2
−40
VO − Receiver Output Voltage − V
I O − Differential Driver Output Current − mA
45
VCC = 5 V
2.5
0
0
1
2
3
4
5
VO(CANH) − High-Level Output Voltage − V
50
3
0.60
I OH − High-Level Output Current − mA
-80
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE (Across VCC)
Dominant Driver Differential Output Voltage − V
DRIVER HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VID − Differential Input Voltage − V
Figure 18.
14
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Figure 19.
Copyright © 2006–2009, Texas Instruments Incorporated
Product Folder Link(s) :SN65HVD1050-EP
SN65HVD1050-EP
www.ti.com
SLLS772A – DECEMBER 2006 – REVISED OCTOBER 2009
TYPICAL CHARACTERISTICS (continued)
TYPICAL ELECTROMAGNETIC EMISSIONS
UP TO 50 MHZ (Peak Amplitude)
TYPICAL ELECTROMAGNETIC
IMMUNITY PERFORMANCE
80
dBm
DB mV
60
40
20
0
0.1
Figure 20.
1
10
f − Frequency − MHz
100
1000
Figure 21.
Copyright © 2006–2009, Texas Instruments Incorporated
Product Folder Link(s) :SN65HVD1050-EP
Submit Documentation Feedback
15
PACKAGE OPTION ADDENDUM
www.ti.com
22-Oct-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN65HVD1050MDREP
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD1050MDREPG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
V62/07608-01XE
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65HVD1050-EP :
SN65HVD1050
• Catalog:
• Automotive: SN65HVD1050-Q1
NOTE: Qualified Version Definitions:
- TI's standard catalog product
• Catalog
Automotive
- Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN65HVD1050MDREP
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65HVD1050MDREP
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
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