SN54LVTH162245, SN74LVTH162245 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS260K – JUNE 1993 – REVISED APRIL 1999 D D D D D D D D D D D D D Members of the Texas Instruments Widebus Family State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation A-Port Outputs Have Equivalent 22-Ω Series Resistors, So No External Resistors Are Required Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC ) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Ioff and Power-Up 3-State Support Hot Insertion Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings SN54LVTH162245 . . . WD PACKAGE SN74LVTH162245 . . . DGG OR DL PACKAGE (TOP VIEW) 1DIR 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCC 2B5 2B6 GND 2B7 2B8 2DIR 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OE description The ’LVTH162245 devices are 16-bit (dual-octal) noninverting 3-state transceivers designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit transceivers or one 16-bit transceiver. The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LVTH162245, SN74LVTH162245 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS260K – JUNE 1993 – REVISED APRIL 1999 description (continued) The A-port outputs, which are designed to source or sink up to 12 mA, include equivalent 22-Ω series resistors to reduce overshoot and undershoot. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN54LVTH162245 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LVTH162245 is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each 8-bit section) INPUTS 2 OPERATION OE DIR L L B data to A bus L H A data to B bus H X Isolation POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LVTH162245, SN74LVTH162245 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS260K – JUNE 1993 – REVISED APRIL 1999 logic symbol† 48 1OE 1DIR G3 1 3 EN1 [BA] 3 EN2 [AB] 25 2OE 2DIR G6 24 6 EN4 [BA] 6 EN5 [AB] 1A1 47 2 1 1B1 2 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 46 3 44 5 43 6 41 8 40 9 38 11 37 12 36 13 4 5 35 14 33 16 32 17 30 19 29 20 27 22 26 23 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1DIR 1 2DIR 48 1A1 25 1OE 47 2A1 2 24 36 13 1B1 To Seven Other Channels POST OFFICE BOX 655303 2OE 2B1 To Seven Other Channels • DALLAS, TEXAS 75265 3 SN54LVTH162245, SN74LVTH162245 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS260K – JUNE 1993 – REVISED APRIL 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Current into any output in the low state, IO: SN54LVTH162245 (B port) . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74LVTH162245 (B port) . . . . . . . . . . . . . . . . . . . . . . . . 128 mA A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Current into any output in the high state, IO (see Note 2): SN54LVTH162245 (B port) . . . . . . . . . . . . . 48 mA SN74LVTH162245 (B port) . . . . . . . . . . . . . 64 mA A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) SN54LVTH162245 SN74LVTH162245 MIN MAX MIN MAX 2.7 3.6 2.7 3.6 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0.8 0.8 V Input voltage 5.5 5.5 V IOH High level output current High-level A port –12 –12 B port –24 –32 IOL Low level output current Low-level A port 12 12 B port 48 64 ∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature –55 High-level input voltage 2 2 V –40 mA mA ns/V µs/V 200 125 V 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LVTH162245, SN74LVTH162245 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS260K – JUNE 1993 – REVISED APRIL 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK A port VOH B port VCC = 2.7 V, VCC = 2.7 V to 3.6 V, II = –18 mA IOH = –100 µA VCC = 3 V, VCC = 2.7 V to 3.6 V, IOH = –12 mA IOH = –100 µA VCC = 2.7 V, IOH = –8 mA IOH = –24 mA VCC = 3 V A port VCC = 2.7 V to 3.6 V, VCC = 3 V, VCC = 2 2.7 7V VOL B port VCC = 3 V Control inputs VCC = 3.6 V, VCC = 0 or 3.6 V, A or B ports‡ VCC = 3.6 V II Ioff VCC = 0, VCC = 3 V II(hold) SN54LVTH162245 MIN TYP† MAX TEST CONDITIONS A or B ports orts VCC = 3.6 V§, SN74LVTH162245 MIN TYP† MAX –1.2 –1.2 VCC–0.2 2 VCC–0.2 2 VCC–0.2 2.4 VCC–0.2 2.4 UNIT V V 2 IOH = –32 mA IOL = 100 µA 2 0.2 0.2 IOL = 12 mA IOL = 100 µA 0.8 0.8 0.2 0.2 IOL = 24 mA IOL = 16 mA 0.5 0.5 0.4 0.4 0.5 0.5 IOL = 32 mA IOL = 48 mA V 0.55 IOL = 64 mA VI = VCC or GND 0.55 ±1 ±1 VI = 5.5 V VI = 5.5 V 10 10 20 20 VI = VCC VI = 0 5 5 –10 –10 VI or VO = 0 to 4.5 V VI = 0.8 V VI = 2 V ±100 75 75 –75 –75 500 –750 VI = 0 to 3.6 V µA µA µA IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don’t care ±100* ±100 µA IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don’t care ±100* ±100 µA VCC = 3.6 V, IO = 0, VI = VCC or GND 0.19 0.19 ICC 5 5 0.19 0.19 ∆ICC¶ VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND 0.3 0.2 Ci VI = 3 V or 0 VO = 3 V or 0 Cio Outputs high Outputs low Outputs disabled mA mA 4 4 pF 10 10 pF * On products compliant to MIL-PRF-38535, this parameter is not production tested. † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ Unused pins at VCC or GND. § This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LVTH162245, SN74LVTH162245 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS260K – JUNE 1993 – REVISED APRIL 1999 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54LVTH162245 PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A B tPLH tPHL B A tPZH tPZL OE B tPZH tPZL OE A tPHZ tPLZ OE B tPHZ tPLZ OE A VCC = 3.3 V ± 0.3 V SN74LVTH162245 VCC = 2.7 V VCC = 2.7 V MAX MIN TYP† MAX 3.5 4 1 2.3 3.3 3.7 3.5 3.9 1 2.2 3.3 3.5 1 4.3 5.3 1 2.8 4 4.6 1 4.2 4.5 1 2.5 3.4 3.6 1 4.8 5.9 1 2.8 4.6 5.4 1 4.8 5.5 1 3 4.6 5.2 1 5.5 7.2 1 3.3 5.3 6.3 1 5.4 6.4 1 3.3 5.1 5.8 1.5 5.5 5.8 1.5 3.8 5.2 5.5 1.5 5.5 5.8 1.5 3.5 5.1 5.4 1.5 5.8 6.5 1.5 4 5.6 5.9 1.2 6.3 6.3 1.5 3.8 5.5 5.5 MIN MAX 1 1 MIN tsk(o) † All typical values are at VCC = 3.3 V, TA = 25°C. 6 VCC = 3.3 V ± 0.3 V POST OFFICE BOX 655303 0.5 • DALLAS, TEXAS 75265 MIN UNIT MAX ns ns ns ns ns ns ns SN54LVTH162245, SN74LVTH162245 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS260K – JUNE 1993 – REVISED APRIL 1999 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test 6V Open S1 GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 2.7 V 1.5 V Input 1.5 V th 2.7 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V Input 1.5 V 0V tPHL tPLH VOH 1.5 V Output 1.5 V VOL 1.5 V 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V tPZL tPLZ 3V 1.5 V tPZH VOH Output Output Waveform 1 S1 at 6 V (see Note B) tPLH tPHL 2.7 V Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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