SN54LVTH162373, SN74LVTH162373 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS261J – JULY 1993 – REVISED APRIL 1999 D D D D D D D D D D D D D Members of the Texas Instruments Widebus Family State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Output Ports Have Equivalent 22-Ω Series Resistors, So No External Resistors Are Required Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC ) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Ioff and Power-Up 3-State Support Hot Insertion Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings SN54LVTH162373 . . . WD PACKAGE SN74LVTH162373 . . . DGG OR DL PACKAGE (TOP VIEW) 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1LE 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2LE description The ’LVTH162373 devices are16-bit transparent D-type latches with 3-state outputs designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LVTH162373, SN74LVTH162373 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS261J – JULY 1993 – REVISED APRIL 1999 description (continued) A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The outputs, which are designed to source or sink up to 12 mA, include equivalent 22-Ω series resistors to reduce overshoot and undershoot. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN54LVTH162373 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LVTH162373 is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each 8-bit section) INPUTS 2 OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LVTH162373, SN74LVTH162373 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS261J – JULY 1993 – REVISED APRIL 1999 logic symbol† 1OE 1LE 2OE 2LE 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 1 1EN 48 C3 24 2EN 25 C4 47 3D 2 1 46 3 44 5 43 6 41 8 40 9 38 11 37 12 36 4D 13 2 35 14 33 16 32 17 30 19 29 20 27 22 26 23 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1OE 1LE 1D1 1 2OE 48 47 2LE C1 2 1D 1Q1 24 25 C1 2D1 36 13 2Q1 To Seven Other Channels To Seven Other Channels POST OFFICE BOX 655303 1D • DALLAS, TEXAS 75265 3 SN54LVTH162373, SN74LVTH162373 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS261J – JULY 1993 – REVISED APRIL 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Current into any output in the high state, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) SN54LVTH162373 SN74LVTH162373 MIN MAX MIN MAX 2.7 3.6 2.7 3.6 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0.8 0.8 V Input voltage 5.5 5.5 V IOH IOL High-level output current –12 –12 mA Low-level output current 12 12 mA ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature –55 High-level input voltage 2 Outputs enabled 2 10 V 10 –40 ns/V µs/V 200 125 V 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LVTH162373, SN74LVTH162373 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS261J – JULY 1993 – REVISED APRIL 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN54LVTH162373 MIN TYP† MAX SN74LVTH162373 MIN TYP† MAX –1.2 –1.2 VIK VOH VCC = 2.7 V, VCC = 3 V, II = –18 mA IOH = –12 mA VOL VCC = 3 V, VCC = 0 or 3.6 V, IOL = 12 mA VI = 5.5 V 0.8 0.8 10 10 VCC = 3.6 V, VI = VCC or GND VI = VCC ±1 ±1 1 1 VI = 0 VI or VO = 0 to 4.5 V –5 –5 II Control inputs Data inputs inp ts Ioff VCC = 3 3.6 6V VCC = 0, VCC = 3 V VI = 0.8 V VI = 2 V VCC = 3.6 V‡, VI = 0 to 3.6 V IOZH IOZL VCC = 3.6 V, VCC = 3.6 V, VO = 3 V VO = 0.5 V IOZPU II(hold) Data in inputs uts 2 2 75 –75 –75 V V ±100 75 UNIT 500 –750 V µA µA µA 5 5 µA –5 –5 µA VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don’t care ±100* ± 100 µA IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don’t care ±100* ±100 µA VCC = 3.6 V, IO = 0, VI = VCC or GND 0.19 0.19 ICC 5 5 0.19 0.19 ∆ICC§ VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND 0.2 0.2 Ci VI = 3 V or 0 VO = 3 V or 0 Co Outputs high Outputs low Outputs disabled mA mA 3 3 pF 9 9 pF * On products compliant to MIL-PRF-38535, this parameter is not production tested. † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. § This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN54LVTH162373 VCC = 3.3 V ± 0.3 V MIN tw tsu Pulse duration, LE high th Hold time, data after LE↓ Setup time, data before LE↓ MAX SN74LVTH162373 VCC = 2.7 V MIN MAX VCC = 3.3 V ± 0.3 V MIN MAX VCC = 2.7 V MIN UNIT MAX 3 3 3 3 ns 1.3 0.6 1 0.6 ns 1 1.1 1 1.1 ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LVTH162373, SN74LVTH162373 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS261J – JULY 1993 – REVISED APRIL 1999 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54LVTH162373 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.3 V MIN tPLH tPHL D Q tPLH tPHL LE Q tPZH tPZL OE Q tPHZ tPLZ OE Q SN74LVTH162373 VCC = 2.7 V MAX MIN VCC = 2.7 V MAX MIN TYP† MAX MIN 5 5.7 1.9 3.1 4.6 5.1 1.8 4.4 4.8 1.9 2.8 4 4.3 2.1 5.4 6.2 2.2 3.4 5.1 5.8 2.1 4.9 4.7 2.2 3.2 4.6 4.3 1.7 5.6 7 1.8 3.2 5.4 6.6 1.7 5.3 5.9 1.8 3.2 4.9 5.5 2.3 6.3 6.6 2.4 3.8 5.4 5.7 1 7.4 6.4 2.2 3.5 5.1 5 POST OFFICE BOX 655303 0.5 • DALLAS, TEXAS 75265 UNIT MAX 1.8 tsk(o) † All typical values are at VCC = 3.3 V, TA = 25°C. 6 VCC = 3.3 V ± 0.3 V ns ns ns ns ns SN54LVTH162373, SN74LVTH162373 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS261J – JULY 1993 – REVISED APRIL 1999 PARAMETER MEASUREMENT INFORMATION 6V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V LOAD CIRCUIT 1.5 V Timing Input 0V tw tsu 2.7 V 1.5 V Input th 2.7 V 1.5 V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V Input 1.5 V 1.5 V 0V tPHL tPLH VOH Output 1.5 V 1.5 V VOL tPHL Output Waveform 1 S1 at 6 V (see Note B) 1.5 V 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V tPZL tPLZ 3V 1.5 V Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ tPZH tPLH VOH Output 2.7 V Output Control 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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