fax id: 5413 1CY 7C42 65 CY7C4255 CY7C4265 PRELIMINARY 8K/16Kx18 Deep Sync FIFOs Features are 18 bits wide and are pin/functionally compatible to the CY7C42X5 Synchronous FIFO family. The CY7C4255/65 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. • High-speed, low-power, first-in first-out (FIFO) memories • 8K x 18 (CY7C4255) • 16K x 18 (CY7C4265) • 0.5 micron CMOS for optimum speed/power • High-speed 100-MHz operation (10 ns read/write cycle times) • Low power — ICC=45 mA • Fully asynchronous and simultaneous read and write operation • Empty, Full, Half Full, and programmable Almost Empty and Almost Full status flags • TTL compatible • Retransmit function • Output Enable (OE) pins • Independent read and write enable pins • Center power and ground pins for reduced noise • Supports free-running 50% duty cycle clock inputs • Width Expansion Capability • Depth Expansion Capability • 64-pin PLCC and 64-pin TQFP • Pin-compatible density upgrade to CY7C42X5 family • Pin-compatible density upgrade to IDT72205/15/25/35/45 These FIFOs have 18-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock (WCLK) and a write enable pin (WEN). When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is continually written into the FIFO on each cycle. The output port is controlled in a similar manner by a free-running read clock (RCLK) and a read enable pin (REN). In addition, the CY7C4255/65 have an output enable pin (OE). The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable. Retransmit and Synchronous Almost Full/Almost Empty flag features are available on these devices. Depth expansion is possible using the cascade input (WXI, RXI), cascade output (WXO, RXO), and First Load (FL) pins. The WXO and RXO pins are connected to the WXI and RXI pins of the next device, and the WXO and RXO pins of the last device should be connected to the WXI and RXI pins of the first device. The FL pin of the first device is tied to VSS and the FL pin of all the remaining devices should be tied to VCC. Functional Description The CY7C4255/65 are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. All D0 – Logic Block Diagram 17 INPUT REGISTER WCLK WEN FLAG PROGRAM REGISTER WRITE CONTROL FLAG LOGIC RAM ARRAY 8K x 18 16K x 18 WRITE POINTER RS FL/RT WXI WXO/HF RXI RXO FF EF PAE PAF SMODE READ POINTER RESET LOGIC THREE–STATE OUTPUT REGISTER EXPANSION LOGIC Cypress Semiconductor Corporation Q0 – • 17 READ CONTROL OE 3901 North First Street RCLK • REN San Jose 4255–1 • CA 95134 • 408-943-2600 July 1995 – Revised November 1996 CY7C4255 CY7C4265 PRELIMINARY Pin Configurations PLCC Top View 9 8 7 D14 D13 D12 D11 D10 D9 VCC D8 GND D7 D6 D5 D4 D3 D2 D1 D0 10 11 12 13 14 15 16 17 18 19 20 6 5 4 TQFP Top View 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 CY7C4255 CY7C4265 21 22 23 24 25 26 47 46 45 44 2728 2930 3132 33 34 35 36 37 38 3940 VCC/SMODE D15 Q14 D14 Q13 D13 GND D12 Q12 D11 Q11 D10 VCC D9 Q10 D8 Q9 D7 GND D6 Q8 D5 Q7 D4 VCC D3 D2 Q6 Q5 D1 D0 GND Q4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CY7C4255 CY7C4265 Q14 Q13 GND Q12 Q11 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCC Q10 Q9 GND Q8 Q7 Q6 Q5 GND Q4 VCC 4142 43 4255–3 4255–2 Functional Description (continued) The Empty and Full flags are synchronous, i.e., they change state relative to either the read clock (RCLK) or the write clock (WCLK). When entering or exiting the Empty states, the flag is updated exclusively by the RCLK. The flag denoting Full states is updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags will remain valid from one clock cycle to the next. The Almost Empty/Almost Full flags become synchronous if the VCC/SMODE is tied to VSS. All configurations are fabricated using an advanced 0.5µ CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. The CY7C4255/65 provides five status pins. These pins are decoded to determine one of five states: Empty, Almost Empty, Half Full, Almost Full, and Full (see Table 2). The Half Full flag shares the WXO pin. This flag is valid in the stand-alone and width-expansion configurations. In the depth expansion, this pin provides the expansion out (WXO) information that is used to signal the next FIFO when it will be activated. Selection Guide 7C4255/65–10 7C4255/65–15 7C4255/65–25 7C4255/65–35 100 66.7 40 28.6 Maximum Access Time (ns) 8 10 15 20 Minimum Cycle Time (ns) 10 15 25 35 Maximum Frequency (MHz) Minimum Data or Enable Set-Up (ns) Minimum Data or Enable Hold (ns) Maximum Flag Delay (ns) Active Power Supply Current (ICC1) (mA) 3 4 6 7 0.5 1 1 2 8 10 15 20 Commercial 45 45 45 45 Industrial 50 50 50 50 CY7C4255 CY7C4265 Density 8K x 18 16K x 18 Package 64-pin PLCC,TQFP 64-pin PLCC,TQFP 2 CY7C4255 CY7C4265 PRELIMINARY Pin Definitions Signal Name Description I/O Function D0 –17 Data Inputs I Data inputs for an 18-bit bus Q 0–17 Data Outputs O Data outputs for an 18-bit bus WEN Write Enable I Enables the WCLK input REN Read Enable I Enables the RCLK input WCLK Write Clock I The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-offset register. RCLK Read Clock I The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not Empty. When LD is asserted, RCLK reads data out of the programmable flag-offset register. WXO/HF Write Expansion Out/Half Full Flag O Dual-Mode Pin: Single device or width expansion – Half Full status flag. Cascaded – Write Expansion Out signal, connected to WXI of next device. EF Empty Flag O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK. FF Full Flag O When FF is LOW, the FIFO is full. FF is synchronized to WCLK. PAE Programmable Almost Empty O When PAE is LOW, the FIFO is almost empty based on the almost-empty offset value programmed into the FIFO. PAE is asynchronous when V CC/SMODE is tied to V CC; it is synchronized to RCLK when V CC/SMODE is tied to VSS. PAF Programmable Almost Full O When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed into the FIFO. PAF is asynchronous when VCC/SMODE is tied to V CC; it is synchronized to WCLK when V CC/SMODE is tied to V SS. LD Load I When LD is LOW, D 0 – 17 (Q 0 – 17) are written (read) into (from) the programmable-flag-offset register. FL/RT First Load/ Retransmit I Dual-Mode Pin: Cascaded – The first device in the daisy chain will have FL tied to V SS; all other devices will have FL tied to V CC. In standard mode or width expansion, FL is tied to V SS on all devices. Not Cascaded – Tied to VSS. Retransmit function is also available in stand-alone mode by strobing RT. WXI Write Expansion Input I Cascaded – Connected to WXO of previous device. Not Cascaded – Tied to VSS. RXI Read Expansion Input I Cascaded – Connected to RXO of previous device. Not Cascaded – Tied to VSS. RXO Read Expansion Output O Cascaded – Connected to RXI of next device. RS Reset I Resets device to empty condition. A reset is required before an initial read or write operation after power-up. OE Output Enable I When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state. VCC/SMODE Synchronous Almost Empty/ Almost Full Flags I Dual-Mode Pin Asynchronous Almost Empty/Almost Full flags – tied to VCC. Synchronous Almost Empty/Almost Full flags – tied to VSS. (Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.) 3 CY7C4255 CY7C4265 PRELIMINARY Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage ........................................... >2001V (per MIL–STD–883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................–65°C to +150° C Latch-Up Current ..................................................... >200 mA Ambient Temperature with Power Applied............................................–55°C to +125° C Operating Range Supply Voltage to Ground Potential ............... –0.5V to +7.0V Range Ambient Temperature VCC DC Voltage Applied to Outputs in High Z State ............................................... –0.5V to +7.0V Commercial 0° C to +70° C 5V ± 10% DC Input Voltage ........................................... −0.5V to Vcc+0.5V Industrial –40° C to +85° C 5V ± 10%  Electrical Characteristics Over the Operating Range Parameter Description Test Conditions 7C42X5–10 7C42X5–15 7C42X5–25 7C42X5– 35 Min. Min. Min. Min. Max. Output HIGH Voltage VCC = Min., I OH = –2.0 mA VOL Output LOW Voltage VCC = Min., I OL = 8.0 mA VIH  Input HIGH Voltage 2.0 VCC 2.0 VCC 2.0 VCC VIL  Input LOW Voltage –0.5 0.8 –0.5 0.8 –0.5 0.8 IIX Input Leakage Current VCC = Max. –10 +10 –10 +10 –10 +10 IOZL I OZH Output OFF, High Z Current OE > VIH, VSS < VO < VCC –10 +10 –10 +10 –10 +10 ICC1 Active Power Supply Current Com’l 45 45 Ind 50 Average Standby Current Com’l Ind ICC2 2.4 Max. VOH  2.4 Max. 0.4 2.4 0.4 Max. 2.4 0.4 Unit V 0.4 V 2.0 VCC V –0.5 0.8 V –10 +10 µA –10 +10 µA 45 45 mA 50 50 50 mA 10 10 10 10 mA 15 15 15 15 mA Capacitance[7,8] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = 5.0V Max. Unit 5 pF 7 pF Notes: 1. TA is the “instant on” case temperature. 2. See the last page of this specification for Group A subgroup testing information. 3. The VIH and VIL specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the previous device or VSS. 4. The VIH and VIL specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the previous device or VSS. 5. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20MHz, while data inputs switch at 10MHz. Outputs are unloaded. Icc1(typical) = (25mA+(freq-20MHz)*(1.0mA/MHz)) 6. All inputs = VCC – 0.2V, except RCLK and WCLK (which are switching at frequency = 20 MHz), and FL/RT which is at Vss. All outputs are unloaded. 7. Tested initially and after any design changes that may affect these parameters. 8. Tested initially and after any process changes that may affect these parameters. 4 CY7C4255 CY7C4265 PRELIMINARY AC Test Loads and Waveforms[9, 10] ALL INPUT PULSES R1 1.1KΩ 5V 3.0V CL GND ≤ 3 ns R2 680Ω INCLUDING JIG AND SCOPE 90% 10% 90% 10% OUTPUT ≤ 3 ns 4255–4 4255–5 Equivalent to: THÉVENIN EQUIVALENT 410Ω OUTPUT 1.91V Switching Characteristics Over the Operating Range Parameter 7C42X5–10 7C42X5–15 7C42X5–25 7C42X5–35 Min. Min. Min. Min. Description Max. 100 Max. Unit 28.6 MHz 20 ns Clock Cycle Frequency tA Data Access Time 2 tCLK Clock Cycle Time 10 15 25 35 ns tCLKH Clock HIGH Time 4.5 6 10 14 ns tCLKL Clock LOW Time 4.5 6 10 14 ns tDS Data Set-Up Time tDH Data Hold Time tENS Enable Set-Up Time tENH Enable Hold Time 2 10 40 Max. tS 8 66.7 Max. 2 15 2 3 4 6 7 ns 0.5 1 1 2 ns 3 4 6 7 ns 0.5 1 1 2 ns tRS Reset Pulse Width 10 15 25 35 ns tRSR Reset Recovery Time 8 tRSF Reset to Flag and Output Time tPRT Retransmit Pulse Width tRTR Retransmit Recovery Time 10 10 Z 15 15 20 25 ns 35 ns 30 35 45 55 ns 60 65 75 85 ns 0 0 0 0 ns tOLZ Output Enable to Output in Low tOE Output Enable to Output Valid 3 7 3 8 3 12 3 15 ns tOHZ Output Enable to Output in High Z 3 7 3 8 3 12 3 15 ns tWFF Write Clock to Full Flag tREF Read Clock to Empty Flag Flag 8 10 15 20 ns 8 10 15 20 ns tPAFasynch Clock to Programmable Almost-Full (Asynchronous mode, VCC/SMODE tied to VCC) 12 16 20 25 ns tPAFsynch Clock to Programmable Almost-Full Flag (Synchronous mode, VCC/SMODE tied to VSS) 8 10 15 20 ns tPAEasynch Clock to Programmable Almost-Empty Flag (Asynchronous mode, VCC/SMODE tied to VCC) 12 16 20 25 ns Notes: 9. CL = 30 pF for all AC parameters except for t OHZ . 10. CL = 5 pF for t OHZ . 11. Pulse widths less than minimum values are not allowed. 12. Values guaranteed by design, not currently tested. 13. tPAFasynch, tPAEasynch, after program register write will not be valid until 5 ns + tPAF(E). 5 CY7C4255 CY7C4265 PRELIMINARY Switching Characteristics Over the Operating Range (continued) Parameter 7C42X5–10 7C42X5–15 7C42X5–25 7C42X5–35 Min. Min. Min. Min. Description Max. Max. Max. Max. Unit tPAEsynch Clock to Programmable Almost-Full Flag (Synchronous mode, VCC/SMODE tied to VSS) 8 10 15 20 ns tHF Clock to Half-Full Flag 12 16 20 25 ns tXO Clock to Expansion Out 6 10 15 20 ns tXI Expansion in Pulse Width 4.5 6.5 10 14 ns tXIS Expansion in Set-Up Time 4 5 10 15 ns tSKEW1 Skew Time between Read Clock and Write Clock for Full Flag 5 6 10 12 ns tSKEW2 Skew Time between Read Clock and Write Clock for Empty Flag 5 6 10 12 ns tSKEW3 Skew Time between Read Clock and Write Clock for Programmable Almost Empty and Programmable Almost Full Flags (Synchronous Mode only) 10 15 18 20 ns 6 CY7C4255 CY7C4265 PRELIMINARY Switching Waveforms Write Cycle Timing tCLK tCLKH tCLKL WCLK tDS tDH D0 –D17 tENS tENH WEN NO OPERATION tWFF tWFF FF tSKEW1  RCLK REN 4255–6 Read Cycle Timing tCLK tCLKH tCLKL RCLK tENS tENH REN NO OPERATION tREF tREF EF tA VALID DATA Q0 –Q17 tOLZ tOHZ tOE OE tSKEW2 WCLK WEN 4255–7 Notes: 14. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge. 15. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK rising edge. 7 CY7C4255 CY7C4265 PRELIMINARY Switching Waveforms (continued) Reset Timing  tRS RS tRSR REN, WEN, LD tRSF EF,PAE tRSF FF,PAF, HF tRSF  OE=1 Q0 – Q17 OE=0 4255–8 First Data Word Latency after Reset with Simultaneous Read and Write WCLK tDS D0 –D17 D0 (FIRSTVALID WRITE) D1 D2 D3 D4 tENS  tFRL WEN tSKEW2 RCLK tREF EF REN tA Q0 –Q17  tA D0 D1 tOLZ tOE OE 4255–9 Notes: 16. The clocks (RCLK, WCLK) can be free-running during reset. 17. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1. 18. When tSKEW2 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or tCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW). 19. The first word is available the cycle after EF goes HIGH, always. 8 CY7C4255 CY7C4265 PRELIMINARY Switching Waveforms (continued) Empty Flag Timing WCLK tDS tDS D0 D0 –D17 D1 tENH tENS tENH tENS WEN tFRL tFRL RCLK tREF tSKEW2 tREF tREF tSKEW2 EF REN OE tA D0 Q0 –Q17 4255–10 Full FlagTiming NO WRITE NO WRITE WCLK tSKEW1  tDS tSKEW1  DATA WRITE DATA WRITE D0 –D17 tWFF tWFF tWFF FF WEN RCLK tENH tENH tENS tENS REN OE LOW tA Q0 –Q17 tA DATA READ DATA IN OUTPUT REGISTER NEXT DATA READ 4255–11 9 CY7C4255 CY7C4265 PRELIMINARY Switching Waveforms (continued) Half–Full Flag Timing tCLKL tCLKH WCLK tENS tENH WEN tHF HF HALF FULL + 1 OR MORE HALF FULL OR LESS HALF FULLOR LESS tHF RCLK tENS REN 4255–12 Programmable Almost Empty Flag Timing tCLKL tCLKH WCLK tENS tENH WEN tPAE N + 1 WORDS IN FIFO tPAE PAE  n WORDS IN FIFO RCLK tENS REN 4255–13 Notes: 20. PAE is offset = n. Number of data words into FIFO already = n. 10 CY7C4255 CY7C4265 PRELIMINARY Switching Waveforms (continued) Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW)) tCLKL tCLKH WCLK tENS tENH WEN WEN2 tENS tENH PAE Note 21 N + 1 WORDS INFIFO tSKEW3  tPAE synch Note 23 tPAE synch RCLK tENS tENS tENH REN 4255–14 Programmable Almost Full Flag Timing tCLKL tCLKH Note 24 WCLK tENS tENH WEN tPAF FULL– M WORDS INFIFO  PAF  FULL– (M+1) WORDS  IN FIFO tPAF RCLK tENS REN 4255–15 Notes: 21. PAE offset − n. 22. tSKEW3 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK. 23. If a read is preformed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW. 24. PAF offset = m. Number of data words written into FIFO already = 8192 − (m + 1) for the CY7C4255 and 16384 − (m + 1) for the CY7C4265. 25. PAF is offset = m. 26. 8192 − m words in CY7C4255 and 16384 - m words in CY7C4265. 27. 8192 − (m + 1) words in CY7C4255 and 16384 - (m + 1) CY7C4265. 11 CY7C4255 CY7C4265 PRELIMINARY Switching Waveforms (continued) Programmable Almost Full Flag Timing (applies only in SMODE (SMODE is LOW)) Note tCLKL tCLKH 28 WCLK tENS tENH WEN Note 29 WEN2 tPAF tENS tENH PAF FULL– M WORDS IN FIFO  FULL– M + 1 WORDS IN FIFO tSKEW3 tPAF synch RCLK tENS tENS tENH REN 4255–16 Write Programmable Registers tCLK tCLKL tCLKH WCLK tENS tENH LD tENS WEN tDS tDH PAE OFFSET D0 –D17 PAE OFFSET PAF OFFSET D0 – D11 4255–17 Notes: 28. If a write is performed on this rising edge of the write clock, there will be Full − (m−1) words of the FIFO when PAF goes LOW. 29. PAF offset = m. 30. tSKEW3 is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of RCLK and the rising edge of WCLK is less than tSKEW3, then PAF may not change state until the next WCLK rising edge. 12 CY7C4255 CY7C4265 PRELIMINARY Switching Waveforms (continued) Read Programmable Registers tCLK tCLKL tCLKH RCLK tENS tENH LD tENS WEN tA UNKNOWN Q0 –Q17 PAE OFFSET PAF OFFSET PAE OFFSET 4255–18 Write Expansion Out Timing tCLKH WCLK Note 31 tXO Note 31 WXO tXO tENS WEN 4255–19 Read Expansion Out Timing tCLKH WCLK Note 32 tXO RXO tXO tENS REN 4255–20 Write Expansion In Timing tXI WXI WCLK tXIS 4255–21 Notes: 31. Write to Last Physical Location. 32. Read from Last Physical Location. 13 CY7C4255 CY7C4265 PRELIMINARY Switching Waveforms (continued) Read Expansion In Timing tXI RXI tXIS RCLK 4255–22 Retransmit Timing [33, 34, 35] FL/RT tPRT tRTR REN/WEN EF/FF and all async flags HF/PAE/PAF 4255–23 Notes: 33. Clocks are free running in this case. 34. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR. 35. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after tRTR to update these flags. 14 CY7C4255 CY7C4265 PRELIMINARY Architecture ation. When the LD pin is set LOW, and WEN is LOW, the next offset register in sequence is written. The CY7C4256/65 consists of an array of 8K/16K words of 18 bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN, WEN, RS), and flags (EF, PAE, HF, PAF, FF). The CY7C4255/65 also includes the control signals WXI, RXI, WXO, RXO for depth expansion. The contents of the offset registers can be read on the output lines when the LD pin is set LOW and REN is set LOW; then, data can be read on the LOW-to-HIGH transition of the read clock (RCLK). Table 1. Write Offset Register. Resetting the FIFO Upon power-up, the FIFO must be reset with a Reset (RS) cycle. This causes the FIFO to enter the Empty condition signified by EF being LOW. All data outputs go LOW after the falling edge of RS only if OE is asserted. In order for the FIFO to reset to its default state, a falling edge must occur on RS and the user must not read or write while RS is LOW. WCLK LD WEN 0 0 Writing to offset registers: Empty Offset Full Offset Selection 0 1 No Operation 1 0 Write Into FIFO 1 1 No Operation FIFO Operation When the WEN signal is active (LOW), data present on the D0–17 pins is written into the FIFO on each rising edge of the WCLK signal. Similarly, when the REN signal is active LOW, data in the FIFO memory will be presented on the Q0 – 17 outputs. New data will be presented on each rising edge of RCLK while REN is active LOW and OE is LOW. REN must set up tENS before RCLK for it to be a valid read function. WEN must occur tENS before WCLK for it to be a valid write function. Flag Operation The CY7C4255/65 devices provide five flag pins to indicate the condition of the FIFO contents. Empty and Full are synchronous. PAE and PAF are synchronous if VCC/SMODE is tied to VSS. An output enable (OE) pin is provided to three-state the Q0 – 17 outputs when OE is deasserted. When OE is enabled (LOW), data in the output register will be available to the Q0 – 17 outputs after tOE. If devices are cascaded, the OE function will only output data on the FIFO that is read enabled. Full Flag The Full Flag (FF) will go LOW when device is Full. Write operations are inhibited whenever FF is LOW regardless of the state of WEN. FF is synchronized to WCLK, i.e., it is exclusively updated by each rising edge of WCLK. The FIFO contains overflow circuitry to disallow additional writes when the FIFO is full, and under flow circuitry to disallow additional reads when the FIFO is empty. An empty FIFO maintains the data of the last valid read on its Q 0 – 17 outputs even after additional reads occur. Empty Flag The Empty Flag (EF) will go LOW when the device is empty. Read operations are inhibited whenever EF is LOW, regardless of the state of REN. EF is synchronized to RCLK, i.e., it is exclusively updated by each rising edge of RCLK. Programming The CY7C4255/65 devices contain two 14-bit offset registers. Data present on D0–13 during a program write will determine the distance from Empty (Full) that the Almost Empty (Almost Full) flags become active. If the user elects not to program the FIFO’s flags, the default offset values are used (see Table 2). When the Load LD pin is set LOW and WEN is set LOW, data on the inputs D0 – 13 is written into the Empty offset register on the first LOW-to-HIGH transition of the write clock (WCLK). When the LD pin and WEN are held LOW then data is written into the Full offset register on the second LOW-to-HIGH transition of the write clock (WCLK). The third transition of the write clock (WCLK) again writes to the Empty offset register (see Table 1). Writing all offset registers does not have to occur at one time. One or two offset registers can be written and then, by bringing the LD pin HIGH, the FIFO is returned to normal read/write oper- Programmable Almost Empty/Almost Full Flag The CY7C4255/65 features programmable Almost Empty and Almost Full Flags. Each flag can be programmed (described in the Programming section) a specific distance from the corresponding boundary flags (Empty or Full). When the FIFO contains the number of words or fewer for which the flags have been programmed, the PAF or PAE will be asserted, signifying that the FIFO is either Almost Full or Almost Empty. See Table 2 for a description of programmable flags. When the SMODE pin is tied LOW, the PAF flag signal transition is caused by the rising edge of the write clock and the PAE flag transition is caused by the rising edge of the read clock. 15 CY7C4255 CY7C4265 PRELIMINARY Retransmit nal read pointer to the first physical location of the FIFO. WCLK and RCLK may be free running but must be disabled during and tRTR after the retransmit pulse. With every valid read cycle after retransmit, previously accessed data is read and the read pointer is incriminated until it is equal to the write pointer. Flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Data written to the FIFO after activation of RT are transmitted also. The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. The Retransmit (RT) input is active in the stand-alone and width expansion modes. The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred and at least one word has been read since the last RS cycle. A HIGH pulse on RT resets the inter- The full depth of the FIFO can be repeatedly retransmitted. Table 2. Flag Truth Table. Number of Words in FIFO 7C4255 – 8K x 18 7C4265 – 16K x 18 FF PAF HF PAE EF 0 0 H H H L L 1 to n 1 to n H H H L H (n+1) to 4096 (n+1) to 8192 H H H H H 4097 to (8192–(m+1)) 8193 to (16384 –(m+1)) H H L H H (8192–m) to 8191 (16384–m) to 16383 H L L H H 8192 16384 L L L H H Notes: 36. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK. 37. n = Empty Offset (Default Values: CY7C4255/CY7C4265 n = 127). 38. m = Full Offset (Default Values: CY7C4255/CY7C4265 n = 127). 16 CY7C4255 CY7C4265 PRELIMINARY Width Expansion Configuration the Empty (Full) flags of every FIFO; the PAE and PAF flags can be detected from any one device. This technique will avoid reading data from, or writing data to the FIFO that is “staggered” by one clock cycle due to the variations in skew between RCLK and WCLK. Figure 1 demonstrates a 36-word width by using two CY7C4255/65s. The CY7C4255/65 can be expanded in width to provide word widths greater than 18 in increments of 18. During width expansion mode all control line inputs are common and all flags are available. Empty (Full) flags should be created by ANDing RESET (RS) DATA IN (D) 36 RESET (RS) 18 18 READ CLOCK (RCLK) WRITE CLOCK (WCLK) READ ENABLE (REN) WRITE ENABLE (WEN) OUTPUT ENABLE (OE) LOAD (LD) PROGRAMMABLE(PAE) 7C4255 7C4265 7C4255 7C4265 HALF FULL FLAG (HF) PROGRAMMABLE (PAF) EMPTY FLAG (EF) FF FF EF EF 18 FULL FLAG (FF) DATA OUT (Q) 36 18 FIRST LOAD (FL) WRITE EXPANSION IN (WXI) READ EXPANSION IN (RXI) 4255–24 Figure 1. Block Diagram of 8K x18/16K x 18Synchronous FIFO Memory Used in a Width Expansion Configuration. 17 CY7C4255 CY7C4265 PRELIMINARY Depth Expansion Configuration (with Programmable Flags) 3. The Write Expansion Out (WXO) pin of each device must be tied to the Write Expansion In (WXI) pin of the next device. 4. The Read Expansion Out (RXO) pin of each device must be tied to the Read Expansion In (RXI) pin of the next device. The CY7C4255/65 can easily be adapted to applications requiring more than 8192/16384 words of buffering. Figure 2 shows Depth Expansion using three CY7C42X5s. Maximum depth is limited only by signal loading. Follow these steps: 5. All Load (LD) pins are tied together. 6. The Half-Full Flag (HF) is not available in the Depth Expansion Configuration. 1. The first device must be designated by grounding the First Load (FL) control input. 7. EF, FF, PAE, and PAF are created with composite flags by ORing together these respective flags for monitoring. The composite PAE and PAF flags are not precise. 2. All other devices must have FL in the HIGH state. WXO RXO 7C4255 7C4265 VCC FL FF EF PAF PAE WXI RXI WXO RXO 7C4255 7C4265 DATAIN (D) DATA OUT (Q) VCC FL FF EF PAF PAE WXI RXI WRITECLOCK (WCLK) WXO RXO WRITEENABLE (WEN) READ CLOCK (RCLK) READ ENABLE (REN) 7C4255 7C4265 RESET (RS) OUTPUTENABLE (OE) LOAD (LD) FF FF PAF EF EF PAFWXI RXI PAE PAE FIRST LOAD (FL) 4255–25 Figure 2. Block Diagram of 8Kx18/16Kx18 Synchronous FIFO Memory with Programmable Flags used in Depth Expansion Configuration. 18 CY7C4255 CY7C4265 PRELIMINARY Ordering Information 8Kx18 Deep Sync FIFO Speed (ns) 10 15 25 35 Ordering Code Package Name Package Type CY7C4255–10AC A65 64-Lead Thin Quad Flatpack CY7C4255–10JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4255–10AI A65 64-Lead Thin Quad Flatpack CY7C4255–10JI J81 68-Lead Plastic Leaded Chip Carrier CY7C4255–15AC A65 64-Lead Thin Quad Flatpack CY7C4255–15JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4255–15AI A65 64-Lead Thin Quad Flatpack CY7C4255–15JI J81 68-Lead Plastic Leaded Chip Carrier CY7C4255–25AC A65 64-Lead Thin Quad Flatpack CY7C4255–25JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4255–25AI A65 64-Lead Thin Quad Flatpack CY7C4255–25JI J81 68-Lead Plastic Leaded Chip Carrier CY7C4255–35AC A65 64-Lead Thin Quad Flatpack CY7C4255–35JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4255–35AI A65 64-Lead Thin Quad Flatpack CY7C4255–35JI J81 68-Lead Plastic Leaded Chip Carrier Package Name Package Type Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial 16Kx18 Deep Sync FIFO Speed (ns) 10 15 25 35 Ordering Code CY7C4265–10AC A65 64-Lead Thin Quad Flatpack CY7C4265–10JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4265–10AI A65 64-Lead Thin Quad Flatpack CY7C4265–10JI J81 68-Lead Plastic Leaded Chip Carrier CY7C4265–15AC A65 64-Lead Thin Quad Flatpack CY7C4265–15JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4265–15AI A65 64-Lead Thin Quad Flatpack CY7C4265–15JI J81 68-Lead Plastic Leaded Chip Carrier CY7C4265–25AC A65 64-Lead Thin Quad Flatpack CY7C4265–25JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4265–25AI A65 64-Lead Thin Quad Flatpack CY7C4265–25JI J81 68-Lead Plastic Leaded Chip Carrier CY7C4265–35AC A65 64-Lead Thin Quad Flatpack CY7C4265–35JC J81 68-Lead Plastic Leaded Chip Carrier CY7C4265–35AI A65 64-Lead Thin Quad Flatpack CY7C4265–35JI J81 68-Lead Plastic Leaded Chip Carrier Document #: 38-00468-A 19 Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial PRELIMINARY CY7C4255 CY7C4265 Package Diagrams 64-Lead Thin Plastic Quad Flat Pack A65 68-Lead Plastic Leaded Chip Carrier J81 © Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.